ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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cpu1_main.c
Go to the documentation of this file.
1
31
32#include <stdint.h>
33
35extern uint32_t g_ra8_ls_cpu1_stack_top;
37extern uint32_t g_ra8_ls_cpu1_data_start;
39extern uint32_t g_ra8_ls_cpu1_data_end;
41extern uint32_t g_ra8_ls_cpu1_data_load;
43extern uint32_t g_ra8_ls_cpu1_bss_start;
45extern uint32_t g_ra8_ls_cpu1_bss_end;
46
47[[noreturn]] void cpu1_reset_handler(void);
48
57typedef enum : uintptr_t {
58 k_port6_pcntr1_addr = 0x404000C0U,
60
69typedef enum : uint32_t {
70 k_led1_pdr_out = 0x00000001U,
71 k_led1_podr_on = 0x00010000U,
72 k_blink_spins = 3000000U,
74
94[[noreturn]] static void cpu1_main(void)
95{
96 volatile uint32_t* pcntr1 = (volatile uint32_t*)k_port6_pcntr1_addr;
97 uint32_t level = 0U;
98
99 while (1) {
100 for (volatile uint32_t d = 0U; d < (uint32_t)k_blink_spins; d++) {
101 __asm volatile("nop");
102 }
103 level ^= 1U;
104 uint32_t value = (uint32_t)k_led1_pdr_out;
105 if (level != 0U) {
106 value |= (uint32_t)k_led1_podr_on;
107 }
108 /* HUM Ch 20.2 "PCNTR1 : Port Control Register 1" p 840 -- write {PODR, PDR}:
109 * hold PORT6 pin 0 an output and drive LED1 (BLUE, P600) to the new level. */
110 *pcntr1 = value;
111 }
112}
113
132[[noreturn]] void cpu1_reset_handler(void)
133{
134 uint32_t* dst = &g_ra8_ls_cpu1_data_start;
135 uint32_t* src = &g_ra8_ls_cpu1_data_load;
136 while (dst < &g_ra8_ls_cpu1_data_end) {
137 *dst = *src;
138 dst++;
139 src++;
140 }
141
142 uint32_t* bss = &g_ra8_ls_cpu1_bss_start;
143 while (bss < &g_ra8_ls_cpu1_bss_end) {
144 *bss = 0U;
145 bss++;
146 }
147
148 cpu1_main();
149}
150
168[[noreturn]] static void cpu1_fault_handler(void)
169{
170 while (1) {
171 __asm volatile("nop");
172 }
173}
174
185#ifndef RA8_OFF_TARGET
186/* The vector table is only meaningful in the cross-compiled M33 image. The host
187 * unit-test build compile-checks this TU but never links it as an executable, so
188 * dropping the table there costs no coverage. */
189[[gnu::used, gnu::section(".cpu1_vectors")]] const uintptr_t g_cpu1_vector_table[] = {
190 (uintptr_t)&g_ra8_ls_cpu1_stack_top,
191 (uintptr_t)&cpu1_reset_handler,
192 (uintptr_t)&cpu1_fault_handler,
193 (uintptr_t)&cpu1_fault_handler,
194 (uintptr_t)&cpu1_fault_handler,
195 (uintptr_t)&cpu1_fault_handler,
196 (uintptr_t)&cpu1_fault_handler,
197 (uintptr_t)&cpu1_fault_handler,
198};
199#endif
void cpu1_reset_handler(void)
CPU1 reset handler.
Definition cpu1_main.c:266
uint32_t g_ra8_ls_cpu1_data_end
uint32_t g_ra8_ls_cpu1_bss_start
uint32_t g_ra8_ls_cpu1_data_load
uint32_t g_ra8_ls_cpu1_bss_end
const uintptr_t g_cpu1_vector_table[]
Minimal Armv8-M vector table for CPU1.
Definition cpu1_main.c:337
uint32_t g_ra8_ls_cpu1_stack_top
uint32_t g_ra8_ls_cpu1_data_start
m33_port_addr_t
MMIO addresses of the PORT registers the M33 hold loop drives.
Definition cpu1_main.c:71
@ k_port6_pcntr1_addr
PORT6 PCNTR1: {PODR[31:16], PDR[15:0]} (LED1).
Definition cpu1_main.c:72
@ k_led1_pdr_out
PCNTR1 PDR pin 0 = output direction.
Definition cpu1_main.c:87
@ k_led1_podr_on
PCNTR1 PODR pin 0 = drive high (bit 16).
Definition cpu1_main.c:88