main.c File Reference

Bare-metal ra8_eth_open() bring-up probe (tracker issue #524). More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_eth.h"
#include "ra8_isr.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Go to the source code of this file.

Enumerations
enum	eop_consts_t : uint32_t {   k_eop_uart_baud = 115200U ,   k_eop_channel = 1U ,   k_eop_hex_chars = 8U ,   k_eop_hex_shift = 4U ,   k_eop_hex_mask = 0xFU ,   k_eop_dec_base = 10U ,   k_eop_dec_max = 10U }
	Console + probe knobs (no magic numbers). More...
enum	eop_pad_t : uint32_t { k_eop_pad_bytes = RA8_ETH_PROBE_PAD_BYTES }
	Size of the leading .bss pad that steers where the HAL's Ethernet statics land in SRAM. More...
enum	eop_mac_t : uint8_t {   k_eop_mac_0 = 0x02U ,   k_eop_mac_1 = 0x00U ,   k_eop_mac_2 = 0x00U ,   k_eop_mac_3 = 0x00U ,   k_eop_mac_4 = 0x00U ,   k_eop_mac_5 = 0x01U }
	Locally-administered MAC the probe opens with. More...

Functions
static void	eop_print (const uint8_t *msg, uint32_t len)
	Push bytes at the SCI8 console, discarding the write status.
static void	eop_log_sink (void *ctx, uint8_t byte)
	ra8_log byte sink forwarding every log byte to the console.
static void	eop_print_hex (uint32_t value)
	Print a 32-bit value as 0x + eight upper-case hex digits.
static void	eop_print_uint (uint32_t value)
	Print an unsigned 32-bit value in decimal.
static uint32_t	eop_bss_pad_anchor (void)
	Touch s_eop_bss_pad and report where it starts.
static void	eop_panic_halt (void)
	Print the negative banner and park the CPU.
static void	eop_setup_or_halt (uint32_t *out_cpuclk_hz)
	Bring up clocks, MSTP, SysTick and the SCI8 console; halt on failure.
static ra8_err_t	eop_run_once (void)
	Run the board Ethernet bring-up and the one ra8_eth_open call.
void	main (void)
	The application entry point Reset_Handler hands control to.

Variables
static volatile uint8_t	s_eop_bss_pad [k_eop_pad_bytes]
	Leading .bss filler that positions every library static behind it.
static const uint8_t	k_eop_msg_boot [] = "eth-open-probe: boot\r\n"
static const uint8_t	k_eop_msg_clock [] = "eth-open-probe: cpuclk0="
static const uint8_t	k_eop_msg_pad [] = " bss_pad="
static const uint8_t	k_eop_msg_padlen [] = " pad_bytes="
static const uint8_t	k_eop_msg_board [] = "eth-open-probe: board_eth rc="
static const uint8_t	k_eop_msg_opening [] = "eth-open-probe: calling ra8_eth_open ch=1\r\n"
static const uint8_t	k_eop_msg_open_rc [] = "eth-open-probe: eth_open rc="
static const uint8_t	k_eop_msg_pass [] = "eth-open-probe: PASS\r\n"
static const uint8_t	k_eop_msg_fail [] = "eth-open-probe: FAIL\r\n"
static const uint8_t	k_eop_msg_hw_fail [] = "eth-open-probe: hw_init_failed\r\n"
static const uint8_t	k_eop_msg_newline [] = "\r\n"
static const uint8_t	k_eop_hex_digits [] = "0123456789ABCDEF"
static const uint8_t	k_eop_msg_hex_lead [] = "0x"

Detailed Description

Bare-metal ra8_eth_open() bring-up probe (tracker issue #524).

Tag

[Ring 6 / APP] {World: S}

The smallest program that reaches ra8_eth_open() on real silicon: clocks, module-stop, SysTick, the SCI8 J-Link VCOM console, the board Ethernet pin/PHY bring-up, then one ra8_eth_open() on channel 1 – exactly the sequence port/netxduo/src/nx_ether_driver_ra8_eth.c performs from NX_LINK_INITIALIZE, with no RTOS, no IP stack and no packet pool in between.

It exists because that sequence has been reported to take a HardFault inside the GWCA TX-ring init, with the descriptor-chain pointer the caller loaded out of the HAL's GWCA state block arriving with address bit 25 clear (0x220664B0 -> 0x200664B0), while the SRAM word itself reads back correct over J-Link. Bit 25 is the bit that separates the Cortex-M85 DTCM window at 0x20000000 from system SRAM at 0x22000000 (HUM Ch 5 "Address Space" pp 236-243), so a cleared bit 25 turns an SRAM pointer into an address just above the 64 KiB DTCM – unimplemented, and therefore a precise BusFault.

The app narrates every step and registers the console as the ra8_log byte sink, so if the fault does occur the shared decoder in libs/ra8_core/src/ra8_exception.c prints the stacked frame (pc, r0..r3) plus cfsr / bfar on the bench UART instead of dropping them into ITM. Those are the numbers the report turns on: r0 is the descriptor-chain pointer as the CPU actually loaded it.

Sequence:

1. ra8_cgc_init + ra8_cgc_get_clock_hz + ra8_mstp_init + ra8_time_init + ra8_board_uart_console_init.
2. ra8_log_set_byte_sink -> console, so a fault dump is visible.
3. ra8_board_ethernet_init (pins, PHY reset, RMII/RGMII select).
4. ra8_eth_open with channel 1 – the EK-RA8D2 RJ45 is wired to ETHA1 / RMAC1.
5. Print the verdict line and idle.

Reaching the verdict line proves the open path completed; a HardFault dump instead of it is the #524 signature.

Note

Headless-emulator status. tools/ra8_emulator models enough of the ESWM register file for the open path to run, so an EIL run reaches the PASS line. It does NOT model SRAM access timing, so it never reproduced the fault; only the bench could, which is exactly why the wire gate and this app both matter.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file main.c.

Enumeration Type Documentation

eop_consts_t

enum eop_consts_t : uint32_t

Console + probe knobs (no magic numbers).

Enumerator
k_eop_uart_baud	SCI8 J-Link VCOM console baud.
k_eop_channel	EK-RA8D2 RJ45 is ETHA1 / RMAC1.
k_eop_hex_chars	Hex digits printed per 32-bit value.
k_eop_hex_shift	Bits consumed per emitted hex digit.
k_eop_hex_mask	Nibble mask for one hex digit.
k_eop_dec_base	Decimal base for the status-code printer.
k_eop_dec_max	Digits in the widest uint32 (4294967295).

Definition at line 70 of file main.c.

eop_mac_t

enum eop_mac_t : uint8_t

Locally-administered MAC the probe opens with.

Enumerator
k_eop_mac_0	Octet 0 – locally administered, unicast.
k_eop_mac_1	Octet 1.
k_eop_mac_2	Octet 2.
k_eop_mac_3	Octet 3.
k_eop_mac_4	Octet 4.
k_eop_mac_5	Octet 5.

Definition at line 133 of file main.c.

eop_pad_t

enum eop_pad_t : uint32_t

Size of the leading .bss pad that steers where the HAL's Ethernet statics land in SRAM.

RA8_ETH_PROBE_PAD_BYTES is a build-time knob (-D... from CMake, see this app's CMakeLists.txt) and the whole point of the app as an instrument. libs/ra8_board_ek_ra8d2/ld/linker_script.ld emits *(.bss) before *(.bss.*), and -fdata-sections puts every ordinary variable in its own .bss.<name>; so a pad forced into the plain .bss section lands ahead of every library static, and growing it slides the whole GWCA block – s_gwca_state, the descriptor chains and the buffer pools – up SRAM by exactly that many bytes with no other change to the program.

That makes "where the Ethernet DMA structures live" a single build-time variable, which is what tracker issue #499 needs and could not get by growing an application array (that moves the rings and every unrelated static, and pulling the rings out of .bss into a placed section moves everything that followed them instead).

Invariant

Value is a multiple of 16 so the pad cannot itself change the alignment of anything behind it.

See also

eop_bss_pad_anchor()

Enumerator
k_eop_pad_bytes	Leading .bss pad, bytes.

Definition at line 107 of file main.c.

Function Documentation

eop_bss_pad_anchor()

uint32_t eop_bss_pad_anchor ( void )

static

Touch s_eop_bss_pad and report where it starts.

Two jobs in one place. The write keeps --gc-sections from dropping the pad, which would silently turn the address sweep into a no-op; and the returned address anchors the transcript to the link map, so a run log says which layout produced it without anyone having to guess which build it came from. Every library static sits at a fixed offset from this address, so it identifies the layout completely.

Returns

uint32_t Address of the first pad byte.

Return values

0x22000030..0x2219FFFF

Somewhere in the .bss output section.

Precondition

.bss has been zero-filled by the reset handler.

The pad is at least one byte long (static_assert above).

Postcondition

The first pad byte reads back as written.

No other state is modified.

Note

Not thread-safe (single-threaded app).

Since

0.1.0

< Byte written to defeat –gc-sections.

< Arbitrary non-zero witness value.

Definition at line 287 of file main.c.

References s_eop_bss_pad.

Referenced by main().

eop_log_sink()

void eop_log_sink ( void * ctx, uint8_t byte )

static

ra8_log byte sink forwarding every log byte to the console.

ra8_exception_report() narrates the decoded fault through ra8_log, whose default ITM backend deliberately drops every byte in fault context. A registered byte sink bypasses that gate, so the dump (pc, r0..r3, cfsr, bfar) lands on the bench UART where the transcript can be read without a debugger attached.

Parameters

[in]	ctx	Unused opaque cookie (sink ABI).
[in]	byte	Log byte to emit.

Precondition

ra8_board_uart_console_init succeeded.

Registered via ra8_log_set_byte_sink.

Postcondition

The byte was pushed to the console (or dropped on error).

No other state is modified.

Note

Callable from fault context – the console write is polled.

Since

0.1.0

Definition at line 199 of file main.c.

References ra8_board_uart_console_write().

Referenced by main().

eop_panic_halt()

void eop_panic_halt ( void )

static

Print the negative banner and park the CPU.

Mirrors the sibling apps' panic idiom: one banner the HIL gate can match, then a debugger-visible stop.

Precondition

Called only on an unrecoverable bring-up failure.

The console is up (best effort – the write may be dropped).

Postcondition

Never returns; the CPU parks in a BKPT + WFI loop.

The negative banner was pushed to the console.

Note

Not thread-safe (terminal path).

Since

0.1.0

Definition at line 311 of file main.c.

References eop_print(), and k_eop_msg_hw_fail.

Referenced by eop_setup_or_halt().

eop_print()

void eop_print ( const uint8_t * msg, uint32_t len )

static

Push bytes at the SCI8 console, discarding the write status.

Console loss is acceptable for a narration helper – the HIL gate re-checks the transcript it actually received.

Parameters

[in]	msg	Bytes to send (not NUL-inspected).
[in]	len	Number of bytes to send.

Precondition

msg points at len readable bytes.

ra8_board_uart_console_init succeeded.

Postcondition

len bytes were pushed to the console (or dropped on error).

No other state is modified.

Note

Not thread-safe (single-threaded app).

Since

0.1.0

Definition at line 173 of file main.c.

References ra8_board_uart_console_write().

Referenced by eop_panic_halt(), eop_print_hex(), eop_print_uint(), eop_run_once(), and main().

eop_print_hex()

void eop_print_hex ( uint32_t value )

static

Print a 32-bit value as 0x + eight upper-case hex digits.

Fixed width so a transcript diff lines up column-wise; the addresses this probe reports are only legible in hex.

Parameters

[in]

value

Value to print.

Precondition

The console is up (best effort – bytes may be dropped).

value is any uint32 (full range supported).

Postcondition

Ten characters were pushed to the console.

No other state is modified.

Note

Not thread-safe (single-threaded app).

Since

0.1.0

Definition at line 221 of file main.c.

References eop_print(), k_eop_hex_chars, k_eop_hex_digits, k_eop_hex_mask, k_eop_hex_shift, and k_eop_msg_hex_lead.

Referenced by main().

eop_print_uint()

void eop_print_uint ( uint32_t value )

static

Print an unsigned 32-bit value in decimal.

Digits are pushed LSB-first into a local buffer then emitted MSB-first; zero prints as a single 0.

Parameters

[in]

value

Value to print.

Precondition

The console is up (best effort – bytes may be dropped).

value is any uint32 (full range supported).

Postcondition

The decimal text was pushed to the console.

No other state is modified.

Note

Not thread-safe (single-threaded app).

Since

0.1.0

Definition at line 247 of file main.c.

References eop_print(), k_eop_dec_base, and k_eop_dec_max.

Referenced by eop_run_once().

eop_run_once()

ra8_err_t eop_run_once ( void )

staticnodiscard

Run the board Ethernet bring-up and the one ra8_eth_open call.

Narrates both status codes so a transcript distinguishes "the board layer refused" from "the HAL open path refused" from "the CPU faulted inside the open path and never returned a code at all" – the last of which is the #524 signature and is why every line is flushed before the call rather than after it.

Returns

ra8_err_t Status of the last call attempted.

Return values

k_ra8_ok	Both the board layer and ra8_eth_open succeeded.
k_ra8_err_invalid_arg	ra8_eth_open rejected the channel or sizes.
k_ra8_err_timeout	GWCA / RMAC mode change did not complete.

Precondition

eop_setup_or_halt has run (clocks, MSTP, SysTick, console).

No other agent owns the ESWM.

Postcondition

On success the GWCA is in OPERATION with both rings primed.

Both status codes have been narrated on the console.

Note

Not thread-safe (single-threaded app).

MC/DC:

Decision: board_rc != k_ra8_ok then open_rc != k_ra8_ok – two independent single-condition decisions rather than one compound, so two vectors each (taken / not taken) fully cover them. Both dependency outcomes are exercised on host in tests/misc/src/test_ra8_board_ek_ra8d2_ethernet_cov.c and tests/misc/src/test_ra8_eth.c through the HAL fault-injection seams.

Since

0.1.0

Definition at line 391 of file main.c.

References eop_print(), eop_print_uint(), k_eop_channel, k_eop_mac_0, k_eop_mac_1, k_eop_mac_2, k_eop_mac_3, k_eop_mac_4, k_eop_mac_5, k_eop_msg_board, k_eop_msg_newline, k_eop_msg_open_rc, k_eop_msg_opening, k_ra8_ok, ra8_board_ethernet_init(), and ra8_eth_open().

Referenced by main().

eop_setup_or_halt()

void eop_setup_or_halt ( uint32_t * out_cpuclk_hz )

static

Bring up clocks, MSTP, SysTick and the SCI8 console; halt on failure.

The minimum the Ethernet bring-up below depends on: ra8_board_ethernet_init needs a running SysTick for its PHY reset delays, and ra8_eth_open needs the ESWM module clock ra8_mstp_init releases.

Parameters

[out]

out_cpuclk_hz

Receives the measured CPUCLK0 frequency in Hz.

Precondition

Running after Reset_Handler with .data / .bss initialised.

out_cpuclk_hz points at writable storage.

Postcondition

The console accepts writes at k_eop_uart_baud.

On any init failure the CPU is parked via eop_panic_halt.

Note

Not thread-safe; boot context only.

Since

0.1.0

Definition at line 338 of file main.c.

References eop_panic_halt(), k_eop_uart_baud, k_ra8_clock_id_cpuclk0, k_ra8_ok, ra8_board_uart_console_init(), ra8_cgc_get_clock_hz(), ra8_cgc_init(), ra8_mstp_init(), and ra8_time_init().

Referenced by main().

main()

void main

(

void

)

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has configured the clock tree and VTOR.

Postcondition

Control does not return; the image runs until reset or halt.

Any value the application wanted to report has been logged, not returned.

Note

Not thread-safe; single-threaded startup context only.

Warning

Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also

SystemInit()

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the playback loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the sweep loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition

Reset_Handler has copied .data and zeroed .bss.

Postcondition

On clean entry the kernel runs the worker thread once.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the kernel runs the worker thread forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition

Reset_Handler has copied .data + zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

CPUCLK0 is raised to the PLL1 target before the kernel starts.

On clean entry the SD card thread runs forever.

On any HAL init failure the function halts in __WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the iso-IN feed loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition

Boot init has completed.

The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition

Diagnostic counter latched, CPU parked in a halt loop.

Function never returns.

Note

Single-threaded entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.

On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.

On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition

The shelf scans on the panel; taps open books, browse, and read.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the cache globals are latched and g_pc_heartbeat advances.

On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the profile + blink loop.

On any HAL hard error LED2 latches ON.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

The shared board boot files installed the vector table.

Postcondition

The demo has run once and its verdict banner is streaming steadily.

The CPU idles re-emitting the banner (or halts after a fatal init error).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On a clean run the CPU loops forever after the PASS banner.

On any failure the function prints FAIL and halts in WFI.

Note

Not thread-safe; this is the single-threaded app entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition

SystemInit configured VTOR / FPU / priority grouping.

The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition

Exactly one PASS or FAIL verdict line has been queued on SCI8.

Control parks in an infinite loop; the function never returns.

Note

Single-threaded; runs to the park loop on the main stack.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The page-count + render-hash banner is emitted; the CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The cal=OK / cal=SKIP result and the finger-free touchcal: ready sentinel are emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The open=OK touch banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Both USB controllers' clocks and pins come up before the kernel so the workers only deal with stack bring-up.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR, FPU, priority grouping.

Postcondition

On clean entry the CPU stays in tx_kernel_enter forever.

On any HAL init failure the function halts in WFI.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging and the clock tree, releases the Cortex-M33 (which then blinks LED1 via ra8_pcntr_set_output()), and idles. See the file header.

Precondition

SystemInit has completed core bring-up.

The M33 is held in reset by hardware until released here.

Postcondition

The M33 has been released and is blinking LED1.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

The application links ra8_c6link and ESP-hosted generated codecs.

No hardware validation is inferred from this function.

Postcondition

No c6link operation is attempted.

No network or storage state is modified.

Note

Single-threaded compile fixture.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the cacheable-SRAM round-trip with the D-cache that SystemInit() enabled through ra8_cache_dcache_enable(), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU + RA8_BOOT_CACHE_VIA_HAL).

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit enabled the MPU + I-cache + D-cache via the ra8_cache HAL.

Postcondition

Exactly one banner (PASS or FAIL) has been emitted.

The core is parked in WFI.

Note

Single-threaded; no RTOS and no IRQ sources in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, releases the Cortex-M33 into the emitter, yields until it signals done, validates the blob the M33 built, then logs the PASS/FAIL verdict and the chapter count read back from the blob. See the file header for the offload narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held inactive by hardware until released here.

Postcondition

The M33 has built a RABOOK1 blob and the M85 has validated it.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this example.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the CPU heartbeats after epaper: PASS.

On any HAL error the console prints epaper: FAIL and the red LED latches on.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The chapters/toc/cover banner is emitted; CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The reader loop runs forever, redrawing on each tap.

A page-1 banner is emitted once after the first render.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The cover-size / framebuffer-CRC banner is emitted; CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The panel shows the reader screen and the input loop runs forever.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, arms the IPC0 wake and configures the LPM block, releases the Cortex-M33 into the reader, waits for the first held page, logs the page-0 verdict, then runs the #150 mode-switch cycle – parking in low-power WFI and waking on the M33's page-turn pokes – before logging the handoff verdict and parking for good. See the file header for the narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held inactive by hardware until released here.

Postcondition

The M33 has rendered + re-rendered the held page and the M85 is parked.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this example.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The boot banner is emitted; the reader loop services taps forever.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the timebase then measures forever.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the measure + blink loop forever.

On any HAL init failure the function halts in WFI.

Note

Never returns.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Arms the RIIC1 target and polls the dispatcher.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

The CPU stays in the dispatch poll loop forever.

On any fatal init error the CPU parks in riic_target_panic_halt.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On a clean run the PASS banner is printed and the CPU loops in WFI.

On any failure the function prints a FAIL line and halts.

Note

Not thread-safe; single-threaded app entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the read + print loop forever.

On any HAL hard error LED2 latches ON and the loop exits.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the LIN commander then drives frames.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the LIN-frame + blink loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, "renders" page 0 into the shared mailbox, releases the Cortex-M33 into its hold loop, and parks the M85 in low-power WFI sleep. See the file header for the power-saving narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held inactive by hardware until released here.

Postcondition

The M33 owns the held page and the M85 is parked.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this example.

Since

0.1.0

The application entry point Reset_Handler hands control to.

The USB clock, pins, console, and the SD card all come up before the kernel so the worker only deals with USB stack bring-up.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR, FPU, priority grouping.

Postcondition

On clean entry the CPU stays in tx_kernel_enter forever.

On any HAL init failure the function halts in WFI.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit configured VTOR / FPU.

Postcondition

On clean bring-up the CPU stays in the poll loop.

On any HAL init failure the function halts in WFI.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler initialized static storage.

SystemInit configured VTOR, FPU, and priority grouping.

Postcondition

The startup banner is printed once.

Control enters ThreadX and never returns normally.

Note

The #707 freestanding contract is declared by ra8_boot_entry.h.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On a clean run the PASS banner is printed and the CPU heartbeats forever.

On any failure LED2 latches ON and the CPU parks.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (MPU enabled, canonical boot map, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit installed the boot map via ra8_mpu_apply_boot_map().

Postcondition

Exactly one banner (PASS or a step-specific FAIL) has been emitted.

The core is parked in WFI.

Note

Single-threaded; no RTOS and no IRQ sources in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler initialised the C runtime; SystemInit ran.

The EK-RA8D2 J-Link OB VCOM console is attached for the banner.

Postcondition

The commit + rollback attempts have executed against extra-MRAM.

The verdict banner is emitted once per report cycle.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the wear-levelling + power-cycle-survival flow, and prints a single PASS/FAIL verdict.

Precondition

SystemInit configured VTOR / FPU / priority grouping.

The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).

Postcondition

Exactly one PASS or FAIL verdict line has been queued on SCI8.

Control parks in an infinite loop; the function never returns.

Note

Single-threaded; runs to the park loop on the main stack.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the program/erase round-trip, and prints a single PASS/FAIL verdict.

Precondition

SystemInit configured VTOR / FPU / priority grouping.

The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).

Postcondition

Exactly one PASS or FAIL verdict line has been queued on SCI8.

Control parks in an infinite loop; the function never returns.

Note

Single-threaded; runs to the park loop on the main stack.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then runs the full ra8_io VFS round-trip over the native-SDHI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On a clean run the CPU loops forever after the PASS banner.

On any failure the function prints FAIL and halts in WFI.

Note

Not thread-safe; this is the single-threaded app entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the console and both stdio sinks, retargets the engine's stdio to the in-RAM capture sink, runs the two-backend swap, replays the RAM capture out of the UART, and prints a single PASS/FAIL verdict per abstraction before parking in an infinite loop.

Precondition

SystemInit configured VTOR / FPU / priority grouping.

The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition

A PASS or FAIL verdict line has been queued on SCI8 for each abstraction.

Control parks in an infinite loop; the function never returns.

Note

Single-threaded; runs to the park loop on the main stack.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then writes + reads + compares one raw 512-byte block straight against ra8_sdcard. On success it prints the exact PASS banner; on any failure it prints FAIL and parks the core.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On a clean run the CPU loops forever after the PASS banner.

On any failure the function prints FAIL and halts in WFI.

Note

Not thread-safe; this is the single-threaded app entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The whoami PASS banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII + RSIP, then ThreadX.

Precondition

Reset_Handler has copied .data and zeroed .bss.

Postcondition

On clean entry the kernel runs the worker thread once.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition

The banner was printed exactly once.

Control passed to ThreadX and never came back.

Note

Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition

The banner and the resolved pin map were printed exactly once.

Control passed to ThreadX and never came back.

Note

Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, the FPU and priority grouping.

Postcondition

The probe ran exactly once and printed its verdict.

The CPU stays in a slow heartbeat loop afterwards.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition

The banner was printed exactly once.

Control passed to ThreadX and never came back.

Note

Everything after tx_kernel_enter runs on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Initializes and arms ADC_B, formats each successful channel sample without variadic I/O, emits the verdict, toggles LED1, and delays.

Precondition

Reset startup and SystemInit completed successfully.

The selected ADC channel matches the board analog connection.

Postcondition

Every PASS verdict follows a successful channel read.

Any read or LED failure leads to the terminal panic helper.

Note

Does not return during normal operation.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the PASS banner is emitted; otherwise a FAIL line is.

The CPU parks in WFI (observable on ra8_emulator until its budget).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33 (which then blinks LED1), and idles. See the file header for the teaching narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held in reset by hardware until released here.

Postcondition

The M33 has been released and is blinking LED1.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The IDCODE/checks PASS banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

See the file header for the full behaviour summary.

Precondition

SystemInit has enabled the caches + MPU (this build defines RA8_BOOT_ENABLE_CACHE_MPU).

The M33 is held in reset by hardware until released here.

Postcondition

The M33 has been released and the round-trip loop is running.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (cacheable SRAM, RO MRAM const, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches and MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU).

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit enabled the MPU + I-cache + D-cache (cache+MPU build).

Postcondition

Exactly one banner (PASS or a step-specific FAIL) has been emitted.

The core is parked in WFI.

Note

Single-threaded; no RTOS and no IRQ sources in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR, FPU and priority grouping.

Postcondition

The verdict banner is on SCI8 and the CPU parks.

The result globals hold the outcome for SWD probing.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Lights HOCO + PLL, then runs a 1 Hz blink.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the toggle loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

See file header for behaviour summary.

Precondition

Boot init has completed.

CPU1 is held in reset.

Postcondition

CPU1 released and the ping-pong loop running.

Function never returns.

Note

Single-threaded entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR, FPU, priority grouping.

Postcondition

Control passes to the active app, or to the ThreadX-hosted DFU device.

On any HAL init failure the function halts in WFI.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss; SystemInit ran.

The embedded image's first two words are a valid MSP + Thumb reset vector.

Postcondition

On success, control is at the image's reset vector in the SRAM run window.

On a failed run-target check, control parks in internal_dcr_panic_halt.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR, FPU, priority grouping.

Postcondition

On clean entry the CPU stays in tx_kernel_enter forever.

On any HAL init failure the function halts in WFI.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit enabled the MPU + caches via RA8_BOOT_ENABLE_CACHE_MPU.

Postcondition

Exactly one PASS/FAIL banner is emitted, then the core parks.

The core ends in WFI so ra8_emulator's idle-stop terminates the run.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Initializes the demo, executes one comparison per period, increments the exported match or mismatch counter, and toggles the matching LED.

Precondition

Reset startup and SystemInit completed successfully.

DOC and the status LEDs are not owned by another context.

Postcondition

Every iteration increments exactly one HIL result counter.

LED1 represents matches and LED2 represents failures or mismatches.

Note

Does not return during normal operation.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clock tree, MSTP, ISR/ELC, and the VCOM console, programs a software-triggered DTC block copy, runs it with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit enabled the MPU + caches via RA8_BOOT_ENABLE_CACHE_MPU.

Postcondition

Exactly one PASS/FAIL banner is emitted, then the core parks.

The core ends in WFI so ra8_emulator's idle-stop terminates the run.

Note

Single-threaded; the completion IRQ is left masked and the result polled.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, zeros the shared control block, releases the Cortex-M33, waits for its boot signature, then yields while the M33 counts autonomously to k_bg_target_count. After the M33 sets done, the M85 reads the counter and logs the PASS/FAIL verdict.

Precondition

SystemInit has completed core bring-up.

The M33 is held in reset by hardware until released here.

Postcondition

The M33 has autonomously incremented the counter and set done.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this example.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33, confirms it booted, runs k_m85_demo_rounds narrated mailbox rounds, then drops into the idle heartbeat. See the file header for the teaching narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held in reset by hardware until released here.

Postcondition

The M33 has been released and the mailbox exchange is running.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this example.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Fires ELC software events once a second.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the trigger + blink loop.

On any HAL hard error LED2 latches ON.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The geometry-hash banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The framebuffer hash banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The bmp/gif framebuffer-CRC banner is emitted; CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The hit-test / nav result banner is emitted; the CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The nav-result banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The per-chapter page-count + render-hash banner is emitted; loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The svg-size / framebuffer-CRC banner is emitted; CPU loops in WFI.

Since

0.1.0

Definition at line 422 of file main.c.

References eop_bss_pad_anchor(), eop_log_sink(), eop_print(), eop_print_hex(), eop_run_once(), eop_setup_or_halt(), k_eop_msg_boot, k_eop_msg_clock, k_eop_msg_fail, k_eop_msg_newline, k_eop_msg_pad, k_eop_msg_padlen, k_eop_msg_pass, k_eop_pad_bytes, k_ra8_ok, ra8_isr_globals_enable(), and ra8_log_set_byte_sink().

Variable Documentation

k_eop_hex_digits

const uint8_t k_eop_hex_digits[] = "0123456789ABCDEF"

static

Definition at line 153 of file main.c.

Referenced by eop_print_hex().

k_eop_msg_board

const uint8_t k_eop_msg_board[] = "eth-open-probe: board_eth rc="

static

Definition at line 146 of file main.c.

Referenced by eop_run_once().

k_eop_msg_boot

const uint8_t k_eop_msg_boot[] = "eth-open-probe: boot\r\n"

static

Definition at line 142 of file main.c.

Referenced by main().

k_eop_msg_clock

const uint8_t k_eop_msg_clock[] = "eth-open-probe: cpuclk0="

static

Definition at line 143 of file main.c.

Referenced by main().

k_eop_msg_fail

const uint8_t k_eop_msg_fail[] = "eth-open-probe: FAIL\r\n"

static

Definition at line 150 of file main.c.

Referenced by main().

k_eop_msg_hex_lead

const uint8_t k_eop_msg_hex_lead[] = "0x"

static

Definition at line 154 of file main.c.

Referenced by eop_print_hex().

k_eop_msg_hw_fail

const uint8_t k_eop_msg_hw_fail[] = "eth-open-probe: hw_init_failed\r\n"

static

Definition at line 151 of file main.c.

Referenced by eop_panic_halt().

k_eop_msg_newline

const uint8_t k_eop_msg_newline[] = "\r\n"

static

Definition at line 152 of file main.c.

Referenced by eop_run_once(), and main().

k_eop_msg_open_rc

const uint8_t k_eop_msg_open_rc[] = "eth-open-probe: eth_open rc="

static

Definition at line 148 of file main.c.

Referenced by eop_run_once().

k_eop_msg_opening

const uint8_t k_eop_msg_opening[] = "eth-open-probe: calling ra8_eth_open ch=1\r\n"

static

Definition at line 147 of file main.c.

Referenced by eop_run_once().

k_eop_msg_pad

const uint8_t k_eop_msg_pad[] = " bss_pad="

static

Definition at line 144 of file main.c.

Referenced by main().

k_eop_msg_padlen

const uint8_t k_eop_msg_padlen[] = " pad_bytes="

static

Definition at line 145 of file main.c.

Referenced by main().

k_eop_msg_pass

const uint8_t k_eop_msg_pass[] = "eth-open-probe: PASS\r\n"

static

Definition at line 149 of file main.c.

Referenced by main().

s_eop_bss_pad

volatile uint8_t s_eop_bss_pad[k_eop_pad_bytes]

static

Leading .bss filler that positions every library static behind it.

Forced into the plain .bss input section (not the -fdata-sections .bss.s_eop_bss_pad it would otherwise get) so the linker emits it in the *(.bss) group, ahead of every *(.bss.*). volatile plus the single write in eop_bss_pad_anchor keeps --gc-sections from discarding it.

Note

Read-only to everything except eop_bss_pad_anchor.

Warning

Never size this from a runtime value – the address sweep it exists for is only meaningful if the layout is static.

Since

0.1.0

Definition at line 130 of file main.c.

Referenced by eop_bss_pad_anchor().