DRW 2D-engine blit + per-pixel alpha-blend headless CRC demo (EK-RA8D2). More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_check.h"
#include "ra8_drw.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Enumerations
enum	drw_blend_config_t : uint32_t { k_drw_blend_baud = 115200U , k_drw_blend_period_ms = 1000U , k_drw_blend_idle_budget = 200000U , k_drw_blend_alpha = 0x80U , k_drw_blend_fnv_offset = 2166136261U , k_drw_blend_fnv_prime = 16777619U }
	Compile-time scalar settings for the demo. More...
enum	drw_blend_hash_t : uint32_t { k_drw_blend_byte_bits = 8U , k_drw_blend_byte_mask = 0xFFU , k_drw_blend_hex_digit = 8U , k_drw_blend_hi_nibble = 7U , k_drw_blend_nib_bits = 4U , k_drw_blend_nib_mask = 0xFU }
	Byte / nibble constants for the FNV hash and hex banner formatting. More...
enum	drw_blend_color_t : uint32_t { k_drw_blend_bg_argb = 0xFF202060U , k_drw_blend_sp_argb = 0xFF40C040U , k_drw_blend_fg_argb = 0xFFE04040U , k_drw_blend_fg_a80 = 0x80E04040U }
	ARGB8888 colours used by the three render layers. More...
enum	drw_blend_geom_t : uint16_t { k_drw_blend_fb_dim = 32U , k_drw_blend_sp_xy = 8U , k_drw_blend_sp_wh = 16U , k_drw_blend_fg_xy = 4U , k_drw_blend_fg_wh = 16U , k_drw_blend_full_org = 0U }
	Framebuffer + layer rectangle geometry, in pixels. More...

Functions
static void	drw_blend_panic_halt (void)
	Park forever after a fatal init failure.
static void	drw_blend_setup_or_halt (void)
	Bring CGC + SysTick + SCI8 + LEDs + MSTP up.
static ra8_err_t	drw_blend_configure (void)
	Bring up the DRW engine pointed at g_drw_blend_fb.
static ra8_err_t	drw_blend_fill (int16_t x, int16_t y, uint16_t w, uint16_t h, uint32_t argb)
	Issue one opaque ra8_drw_fill_rect and wait for the engine.
static ra8_err_t	drw_blend_arm (void)
	Arm the blend unit for opaque-over (source-over) global-alpha mixing.
static uint32_t	drw_blend_framebuffer_hash (void)
	FNV-1a-32 over the rendered framebuffer bytes.
static ra8_err_t	drw_blend_render (uint32_t *out_crc)
	Render the three layers (background, sprite, blended foreground).
static void	drw_blend_print_hex (uint32_t value)
	Print one hex nibble's worth of the 32-bit CRC over the console.
static void	drw_blend_print_pass (uint32_t crc)
	Emit the success banner: prefix + 8 hex CRC + " PASS\r\n".
void	main (void)
	The application entry point Reset_Handler hands control to.

Variables
static const char *	s_tag = "drw_blend"
	Diagnostic / log tag.
static const uint8_t	k_drw_blend_pass_pfx [] = "drw: blit+blend crc="
	Success / failure banner text.
static const uint8_t	k_drw_blend_pass_sfx [] = " PASS\r\n"
static const uint8_t	k_drw_blend_fail_msg [] = "drw: blit+blend FAIL\r\n"
volatile uint32_t	g_drw_blend_fb [(uint32_t) k_drw_blend_fb_dim *(uint32_t) k_drw_blend_fb_dim]
	32 x 32 ARGB8888 framebuffer the DRW composites into.
volatile uint32_t	g_drw_blend_crc = 0U
	FNV-1a-32 hash of the last rendered framebuffer.
volatile uint32_t	g_drw_blend_err = 0U
	Non-zero if a DRW call returned an error during the last render.
volatile uint32_t	g_drw_blend_heartbeat = 0U
	Bumps once per main-loop pass – liveness for headless probes.

Detailed Description

DRW 2D-engine blit + per-pixel alpha-blend headless CRC demo (EK-RA8D2).

Tag: [Ring 6 / APP] {World: S}

Issue #120 asks for a demo that exercises the DRW ("D/AVE 2D") engine's blit AND alpha-blend path (ra8_drw_blend_t), not just the solid fill the sibling drw_fill_demo covers. This app renders three layers into a small 32x32 ARGB8888 framebuffer in SRAM and then folds an FNV-1a-32 hash over the whole framebuffer, exactly like ereader_chrome does for its chrome:

Background – an opaque dark-blue ra8_drw_fill_rect over the whole FB.
Sprite blit – an opaque green ra8_drw_fill_rect sub-rectangle (the "sprite" laid down over the background).
Alpha blend – a half-transparent red foreground composited over the background + sprite via ra8_drw_set_blend (source-over, global alpha 0x80) followed by a final ra8_drw_fill_rect. With the blend unit armed the DRW reads each destination pixel back and mixes the COLOR1 source in by the global alpha, so the overlap region carries a deterministic mix of red over blue and red over green.

The rendered framebuffer is byte-deterministic, so its hash is constant on every boot. The app prints "drw: blit+blend crc=<8hex> PASS" over the J-Link OB CDC channel once a second; the headless gate (ra8_emulator_smoke.sh / hil.conf uart_scrape) asserts that banner. No display panel is touched – this is a pure compute + memory test.

Note: Headless-emulator status. tools/ra8_emulator models the DRW engine as INERT (board_periph_drw.c), faithful to real silicon where the D/AVE 2D engine never rasterizes (issue #247): register writes are accepted, STATUS reads idle so ra8_drw_wait_idle returns, HWREVISION reads 0, and the ORIGIN render trigger synthesises no pixel. The framebuffer therefore stays zero, so the FNV-1a-32 hash is 0x76EFDDC5 – the SAME value a real board produces from its all-zero framebuffer. EIL == HIL: the EIL gate and the bench print the identical banner. This app lives in hw_validated/hil/ because that zero-framebuffer result is confirmed on silicon; the demo will only report a genuinely composited CRC once #247 brings the engine to life.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file main.c.

Enumeration Type Documentation

◆ drw_blend_color_t

enum drw_blend_color_t : uint32_t

ARGB8888 colours used by the three render layers.

Background, sprite, and foreground source colours. The foreground is the COLOR1 source fed through the blend unit at k_drw_blend_alpha.

Enumerator
k_drw_blend_bg_argb	Opaque dark-blue background.
k_drw_blend_sp_argb	Opaque green sprite.
k_drw_blend_fg_argb	Red foreground source RGB.
k_drw_blend_fg_a80	Foreground at global alpha 0x80. ra8_drw_fill_rect writes the FULL COLOR1 (including alpha), so the blended fill must carry the global alpha in its colour argument or it would clobber the armed 0x80 back to opaque and blend nothing.

Definition at line 106 of file main.c.

◆ drw_blend_config_t

enum drw_blend_config_t : uint32_t

Compile-time scalar settings for the demo.

Baud, loop period, the bounded ra8_drw_wait_idle poll budget, the global-alpha value driven into the blend unit, and the FNV-1a-32 constants used to hash the framebuffer.

Enumerator
k_drw_blend_baud	SCI8 baud rate.
k_drw_blend_period_ms	Delay between renders.
k_drw_blend_idle_budget	Bounded wait_idle poll budget.
k_drw_blend_alpha	Global source-over alpha (128).
k_drw_blend_fnv_offset	FNV-1a-32 offset basis.
k_drw_blend_fnv_prime	FNV-1a-32 prime.

Definition at line 72 of file main.c.

◆ drw_blend_geom_t

enum drw_blend_geom_t : uint16_t

Framebuffer + layer rectangle geometry, in pixels.

A 32x32 ARGB8888 framebuffer. The sprite is a centred 16x16 box; the blended foreground is a 16x16 box offset up-left so it overlaps both the background and the sprite, giving a deterministic three-region composite.

Enumerator
k_drw_blend_fb_dim	32 x 32 framebuffer.
k_drw_blend_sp_xy	Sprite top-left (8, 8).
k_drw_blend_sp_wh	Sprite 16 x 16.
k_drw_blend_fg_xy	Foreground top-left (4, 4).
k_drw_blend_fg_wh	Foreground 16 x 16.
k_drw_blend_full_org	Full-FB origin (0, 0).

Definition at line 128 of file main.c.

◆ drw_blend_hash_t

enum drw_blend_hash_t : uint32_t

Byte / nibble constants for the FNV hash and hex banner formatting.

The FNV pass extracts one byte per shift; the hex printer emits eight nibbles, most-significant first. Naming these clears the magic-number gate.

Enumerator
k_drw_blend_byte_bits	Bits per byte (FNV shift step).
k_drw_blend_byte_mask	Low-byte mask for the FNV input.
k_drw_blend_hex_digit	Hex digits in a 32-bit CRC.
k_drw_blend_hi_nibble	Index of the most-significant nibble.
k_drw_blend_nib_bits	Bits per hex nibble.
k_drw_blend_nib_mask	Low-nibble mask for the hex digit.

Definition at line 89 of file main.c.

Function Documentation

◆ drw_blend_arm()

ra8_err_t drw_blend_arm ( void )

staticnodiscard

Arm the blend unit for opaque-over (source-over) global-alpha mixing.

Sets COLOR1 to the foreground source via ra8_drw_set_gradient (COLOR2 is unused here but written for determinism), then programs ra8_drw_blend_t for the standard source-over combination at the demo's global alpha. The subsequent ra8_drw_fill_rect composites COLOR1 over each destination pixel instead of overwriting it.

MC/DC:: Single decision err != k_ra8_ok per call – no compound condition.

Returns: ra8_err_t – k_ra8_ok once COLOR1/COLOR2 and CONTROL2 are set.

Return values

k_ra8_ok	Blend unit armed.
k_ra8_err_null_ptr	Internal descriptor pointer was NULL (cannot happen; both descriptors are stack locals).

Precondition: drw_blend_configure succeeded.; The foreground source colour fits ARGB8888.

Postcondition: COLOR1 holds the foreground RGB with alpha = k_drw_blend_alpha.; CONTROL2 source-over + USEACB bits are set for the next fill.

Since: 0.1.0

Definition at line 302 of file main.c.

References k_drw_blend_alpha, k_drw_blend_bg_argb, k_drw_blend_fg_argb, k_ra8_ok, ra8_drw_set_blend(), and ra8_drw_set_gradient().

Referenced by drw_blend_render().

◆ drw_blend_configure()

ra8_err_t drw_blend_configure ( void )

staticnodiscard

Bring up the DRW engine pointed at g_drw_blend_fb.

MC/DC:: Single decision err != k_ra8_ok in the caller – no compound condition.

Returns: ra8_err_t from ra8_drw_init.

Return values

k_ra8_ok	DRW configured for ARGB8888 over the demo framebuffer.
k_ra8_err_null_ptr	Internal config pointer was NULL (cannot happen).
k_ra8_err_hw_init_failed	MSTP enable failed.

Precondition: CGC + MSTP up; IRQs masked or single-threaded init.; g_drw_blend_fb is 4-byte aligned (ARGB8888).

Postcondition: DRW ORIGIN/PITCH/CONTROL2 target g_drw_blend_fb (ARGB8888).; FB + texture caches are left off so the CPU reads fresh pixels.

Since: 0.1.0

Definition at line 227 of file main.c.

References g_drw_blend_fb, k_drw_blend_fb_dim, k_ra8_drw_writefmt_argb8888, and ra8_drw_init().

Referenced by main().

◆ drw_blend_fill()

ra8_err_t drw_blend_fill	(	int16_t	x,
		int16_t	y,
		uint16_t	w,
		uint16_t	h,
		uint32_t	argb )

staticnodiscard

Issue one opaque ra8_drw_fill_rect and wait for the engine.

Parameters

[in]	x	Top-left X in pixels.
[in]	y	Top-left Y in pixels.
[in]	w	Width in pixels.
[in]	h	Height in pixels.
[in]	argb	0xAARRGGBB fill colour.

MC/DC:: Single decision ferr != k_ra8_ok – no compound condition.

Returns: ra8_err_t – k_ra8_ok once the fill is issued and the engine goes idle, else the fill / wait error.

Return values

k_ra8_ok	Fill rasterized.
k_ra8_err_invalid_arg	Geometry rejected by ra8_drw_fill_rect.
k_ra8_err_hw_timeout	Engine stayed busy past the poll budget.

Precondition: drw_blend_configure succeeded.; w and h are within the DRW's accepted range.

Postcondition: On success the rectangle is present in g_drw_blend_fb.; The DRW engine is idle on return.

Since: 0.1.0

Definition at line 263 of file main.c.

References k_drw_blend_idle_budget, k_ra8_ok, ra8_drw_fill_rect(), and ra8_drw_wait_idle().

Referenced by drw_blend_render().

◆ drw_blend_framebuffer_hash()

uint32_t drw_blend_framebuffer_hash ( void )

static

FNV-1a-32 over the rendered framebuffer bytes.

Definition at line 334 of file main.c.

References g_drw_blend_fb, k_drw_blend_byte_bits, k_drw_blend_byte_mask, k_drw_blend_fb_dim, k_drw_blend_fnv_offset, and k_drw_blend_fnv_prime.

Referenced by drw_blend_render().

◆ drw_blend_panic_halt()

void drw_blend_panic_halt ( void )

static

Park forever after a fatal init failure.

Definition at line 176 of file main.c.

Referenced by drw_blend_setup_or_halt(), and main().

◆ drw_blend_print_hex()

void drw_blend_print_hex ( uint32_t value )

static

Print one hex nibble's worth of the 32-bit CRC over the console.

Definition at line 419 of file main.c.

References k_drw_blend_hex_digit, k_drw_blend_hi_nibble, k_drw_blend_nib_bits, k_drw_blend_nib_mask, and ra8_board_uart_console_write().

Referenced by drw_blend_print_pass().

◆ drw_blend_print_pass()

void drw_blend_print_pass ( uint32_t crc )

static

Emit the success banner: prefix + 8 hex CRC + " PASS\r\n".

Definition at line 431 of file main.c.

References drw_blend_print_hex(), k_drw_blend_pass_pfx, k_drw_blend_pass_sfx, and ra8_board_uart_console_write().

Referenced by main().

◆ drw_blend_render()

ra8_err_t drw_blend_render ( uint32_t * out_crc )

staticnodiscard

Render the three layers (background, sprite, blended foreground).

Parameters

[out] out_crc Receives the FNV-1a-32 hash of the rendered framebuffer.

MC/DC:: Each step is a single err != k_ra8_ok early-return decision; no compound conditions. The host test drives the success path plus one failure-injection vector per step.

Returns: ra8_err_t – k_ra8_ok once all three layers are composited.

Return values

k_ra8_ok	Framebuffer rendered and hashed.
k_ra8_err_null_ptr	out_crc was NULL.
k_ra8_err_invalid_arg	A layer rectangle was rejected.
k_ra8_err_hw_timeout	The engine stayed busy past the budget.

Precondition: drw_blend_configure succeeded.; out_crc is non-null.

Postcondition: On success *out_crc holds the framebuffer hash.; g_drw_blend_err reflects the last DRW call.

Since: 0.1.0

Definition at line 370 of file main.c.

References drw_blend_arm(), drw_blend_fill(), drw_blend_framebuffer_hash(), g_drw_blend_err, k_drw_blend_bg_argb, k_drw_blend_fb_dim, k_drw_blend_fg_a80, k_drw_blend_fg_wh, k_drw_blend_fg_xy, k_drw_blend_full_org, k_drw_blend_sp_argb, k_drw_blend_sp_wh, k_drw_blend_sp_xy, k_ra8_ok, RA8_CHECK_NULL_PTR, and s_tag.

Referenced by main().

◆ drw_blend_setup_or_halt()

void drw_blend_setup_or_halt ( void )

static

Bring CGC + SysTick + SCI8 + LEDs + MSTP up.

Definition at line 184 of file main.c.

References drw_blend_panic_halt(), k_drw_blend_baud, k_ra8_board_led1, k_ra8_board_led2, k_ra8_clock_id_cpuclk0, k_ra8_ok, ra8_board_led_init(), ra8_board_uart_console_init(), ra8_cgc_get_clock_hz(), ra8_cgc_init(), ra8_mstp_init(), and ra8_time_init().

Referenced by main().

◆ main()

void main ( void )

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has configured the clock tree and VTOR.

Postcondition: Control does not return; the image runs until reset or halt.; Any value the application wanted to report has been logged, not returned.

Note: Not thread-safe; single-threaded startup context only.

Warning: Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also: SystemInit()

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the playback loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the sweep loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.

Postcondition: On clean entry the kernel runs the worker thread once.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the kernel runs the worker thread forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition: Reset_Handler has copied .data + zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: CPUCLK0 is raised to the PLL1 target before the kernel starts.; On clean entry the SD card thread runs forever.; On any HAL init failure the function halts in __WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the iso-IN feed loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition: Boot init has completed.; The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition: Diagnostic counter latched, CPU parked in a halt loop.; Function never returns.

Note: Single-threaded entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.; On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.; On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition: The shelf scans on the panel; taps open books, browse, and read.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the cache globals are latched and g_pc_heartbeat advances.; On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the profile + blink loop.; On any HAL hard error LED2 latches ON.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; The shared board boot files installed the vector table.

Postcondition: The demo has run once and its verdict banner is streaming steadily.; The CPU idles re-emitting the banner (or halts after a fatal init error).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The page-count + render-hash banner is emitted; the CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The cal=OK / cal=SKIP result and the finger-free touchcal: ready sentinel are emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The open=OK touch banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Both USB controllers' clocks and pins come up before the kernel so the workers only deal with stack bring-up.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging and the clock tree, releases the Cortex-M33 (which then blinks LED1 via ra8_pcntr_set_output()), and idles. See the file header.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and is blinking LED1.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: The application links ra8_c6link and ESP-hosted generated codecs.; No hardware validation is inferred from this function.

Postcondition: No c6link operation is attempted.; No network or storage state is modified.

Note: Single-threaded compile fixture.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the cacheable-SRAM round-trip with the D-cache that SystemInit() enabled through ra8_cache_dcache_enable(), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU + RA8_BOOT_CACHE_VIA_HAL).

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + I-cache + D-cache via the ra8_cache HAL.

Postcondition: Exactly one banner (PASS or FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, releases the Cortex-M33 into the emitter, yields until it signals done, validates the blob the M33 built, then logs the PASS/FAIL verdict and the chapter count read back from the blob. See the file header for the offload narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 has built a RABOOK1 blob and the M85 has validated it.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the CPU heartbeats after epaper: PASS.; On any HAL error the console prints epaper: FAIL and the red LED latches on.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/toc/cover banner is emitted; CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The reader loop runs forever, redrawing on each tap.; A page-1 banner is emitted once after the first render.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The cover-size / framebuffer-CRC banner is emitted; CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The panel shows the reader screen and the input loop runs forever.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, arms the IPC0 wake and configures the LPM block, releases the Cortex-M33 into the reader, waits for the first held page, logs the page-0 verdict, then runs the #150 mode-switch cycle – parking in low-power WFI and waking on the M33's page-turn pokes – before logging the handoff verdict and parking for good. See the file header for the narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 has rendered + re-rendered the held page and the M85 is parked.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The boot banner is emitted; the reader loop services taps forever.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the timebase then measures forever.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the measure + blink loop forever.; On any HAL init failure the function halts in WFI.

Note: Never returns.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Arms the RIIC1 target and polls the dispatcher.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: The CPU stays in the dispatch poll loop forever.; On any fatal init error the CPU parks in riic_target_panic_halt.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the PASS banner is printed and the CPU loops in WFI.; On any failure the function prints a FAIL line and halts.

Note: Not thread-safe; single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the read + print loop forever.; On any HAL hard error LED2 latches ON and the loop exits.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the LIN commander then drives frames.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the LIN-frame + blink loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, "renders" page 0 into the shared mailbox, releases the Cortex-M33 into its hold loop, and parks the M85 in low-power WFI sleep. See the file header for the power-saving narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 owns the held page and the M85 is parked.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

The USB clock, pins, console, and the SD card all come up before the kernel so the worker only deals with USB stack bring-up.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit configured VTOR / FPU.

Postcondition: On clean bring-up the CPU stays in the poll loop.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler initialized static storage.; SystemInit configured VTOR, FPU, and priority grouping.

Postcondition: The startup banner is printed once.; Control enters ThreadX and never returns normally.

Note: The #707 freestanding contract is declared by ra8_boot_entry.h.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the PASS banner is printed and the CPU heartbeats forever.; On any failure LED2 latches ON and the CPU parks.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (MPU enabled, canonical boot map, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit installed the boot map via ra8_mpu_apply_boot_map().

Postcondition: Exactly one banner (PASS or a step-specific FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler initialised the C runtime; SystemInit ran.; The EK-RA8D2 J-Link OB VCOM console is attached for the banner.

Postcondition: The commit + rollback attempts have executed against extra-MRAM.; The verdict banner is emitted once per report cycle.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the wear-levelling + power-cycle-survival flow, and prints a single PASS/FAIL verdict.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the program/erase round-trip, and prints a single PASS/FAIL verdict.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then runs the full ra8_io VFS round-trip over the native-SDHI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the console and both stdio sinks, retargets the engine's stdio to the in-RAM capture sink, runs the two-backend swap, replays the RAM capture out of the UART, and prints a single PASS/FAIL verdict per abstraction before parking in an infinite loop.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition: A PASS or FAIL verdict line has been queued on SCI8 for each abstraction.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then writes + reads + compares one raw 512-byte block straight against ra8_sdcard. On success it prints the exact PASS banner; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The whoami PASS banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII + RSIP, then ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.

Postcondition: On clean entry the kernel runs the worker thread once.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition: The banner was printed exactly once.; Control passed to ThreadX and never came back.

Note: Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition: The banner and the resolved pin map were printed exactly once.; Control passed to ThreadX and never came back.

Note: Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and priority grouping.

Postcondition: The probe ran exactly once and printed its verdict.; The CPU stays in a slow heartbeat loop afterwards.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition: The banner was printed exactly once.; Control passed to ThreadX and never came back.

Note: Everything after tx_kernel_enter runs on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initializes and arms ADC_B, formats each successful channel sample without variadic I/O, emits the verdict, toggles LED1, and delays.

Precondition: Reset startup and SystemInit completed successfully.; The selected ADC channel matches the board analog connection.

Postcondition: Every PASS verdict follows a successful channel read.; Any read or LED failure leads to the terminal panic helper.

Note: Does not return during normal operation.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the PASS banner is emitted; otherwise a FAIL line is.; The CPU parks in WFI (observable on ra8_emulator until its budget).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33 (which then blinks LED1), and idles. See the file header for the teaching narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and is blinking LED1.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The IDCODE/checks PASS banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

See the file header for the full behaviour summary.

Precondition: SystemInit has enabled the caches + MPU (this build defines RA8_BOOT_ENABLE_CACHE_MPU).; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and the round-trip loop is running.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (cacheable SRAM, RO MRAM const, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches and MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU).

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + I-cache + D-cache (cache+MPU build).

Postcondition: Exactly one banner (PASS or a step-specific FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU and priority grouping.

Postcondition: The verdict banner is on SCI8 and the CPU parks.; The result globals hold the outcome for SWD probing.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Lights HOCO + PLL, then runs a 1 Hz blink.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the toggle loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

See file header for behaviour summary.

Precondition: Boot init has completed.; CPU1 is held in reset.

Postcondition: CPU1 released and the ping-pong loop running.; Function never returns.

Note: Single-threaded entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: Control passes to the active app, or to the ThreadX-hosted DFU device.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss; SystemInit ran.; The embedded image's first two words are a valid MSP + Thumb reset vector.

Postcondition: On success, control is at the image's reset vector in the SRAM run window.; On a failed run-target check, control parks in internal_dcr_panic_halt.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + caches via RA8_BOOT_ENABLE_CACHE_MPU.

Postcondition: Exactly one PASS/FAIL banner is emitted, then the core parks.; The core ends in WFI so ra8_emulator's idle-stop terminates the run.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initializes the demo, executes one comparison per period, increments the exported match or mismatch counter, and toggles the matching LED.

Precondition: Reset startup and SystemInit completed successfully.; DOC and the status LEDs are not owned by another context.

Postcondition: Every iteration increments exactly one HIL result counter.; LED1 represents matches and LED2 represents failures or mismatches.

Note: Does not return during normal operation.

Since: 0.1.0

Definition at line 440 of file main.c.

References drw_blend_configure(), drw_blend_panic_halt(), drw_blend_print_pass(), drw_blend_render(), drw_blend_setup_or_halt(), g_drw_blend_crc, g_drw_blend_heartbeat, k_drw_blend_fail_msg, k_drw_blend_period_ms, k_ra8_board_led1, k_ra8_board_led2, k_ra8_ok, ra8_board_led_toggle(), ra8_board_uart_console_write(), ra8_delay_ms(), and ra8_isr_globals_enable().

Variable Documentation

◆ g_drw_blend_crc

volatile uint32_t g_drw_blend_crc = 0U

FNV-1a-32 hash of the last rendered framebuffer.

Note: Read externally only (HIL / board emulator).

Since: 0.1.0

Definition at line 157 of file main.c.

Referenced by main().

◆ g_drw_blend_err

volatile uint32_t g_drw_blend_err = 0U

Non-zero if a DRW call returned an error during the last render.

Note: Read externally only.

Since: 0.1.0

Definition at line 165 of file main.c.

Referenced by drw_blend_render().

◆ g_drw_blend_fb

volatile uint32_t g_drw_blend_fb[(uint32_t) k_drw_blend_fb_dim *(uint32_t) k_drw_blend_fb_dim]

32 x 32 ARGB8888 framebuffer the DRW composites into.

Note: 4-byte aligned (ARGB8888 invariant). Read externally (HIL / emulator).

Since: 0.1.0

Definition at line 149 of file main.c.

Referenced by drw_blend_configure(), and drw_blend_framebuffer_hash().

◆ g_drw_blend_heartbeat

volatile uint32_t g_drw_blend_heartbeat = 0U

Bumps once per main-loop pass – liveness for headless probes.

Note: Read externally only.

Since: 0.1.0

Definition at line 173 of file main.c.

Referenced by main().

◆ k_drw_blend_fail_msg

const uint8_t k_drw_blend_fail_msg[] = "drw: blit+blend FAIL\r\n"

static

Definition at line 140 of file main.c.

Referenced by main().

◆ k_drw_blend_pass_pfx

const uint8_t k_drw_blend_pass_pfx[] = "drw: blit+blend crc="

static

Success / failure banner text.

Definition at line 138 of file main.c.

Referenced by drw_blend_print_pass().

◆ k_drw_blend_pass_sfx

const uint8_t k_drw_blend_pass_sfx[] = " PASS\r\n"

static

Definition at line 139 of file main.c.

Referenced by drw_blend_print_pass().

◆ s_tag

const char* s_tag = "drw_blend"

static

Diagnostic / log tag.

Definition at line 61 of file main.c.

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ drw_blend_color_t

◆ drw_blend_config_t

◆ drw_blend_geom_t

◆ drw_blend_hash_t

Function Documentation

◆ drw_blend_arm()

◆ drw_blend_configure()

◆ drw_blend_fill()

◆ drw_blend_framebuffer_hash()

◆ drw_blend_panic_halt()

◆ drw_blend_print_hex()

◆ drw_blend_print_pass()

◆ drw_blend_render()

◆ drw_blend_setup_or_halt()

◆ main()

Variable Documentation

◆ g_drw_blend_crc

◆ g_drw_blend_err

◆ g_drw_blend_fb

◆ g_drw_blend_heartbeat

◆ k_drw_blend_fail_msg

◆ k_drw_blend_pass_pfx

◆ k_drw_blend_pass_sfx

◆ s_tag