board_periph_drw.c File Reference

Bench-validated DRW ("D/AVE 2D") rasterizer model for ra8_emulator. More...

#include <stdint.h>
#include <stdio.h>
#include "board_periph_block.h"
#include "board_periph_pdctr_internal.h"
#include "emu_host_io_internal.h"

Include dependency graph for board_periph_drw.c:

Go to the source code of this file.

Data Structures
struct	drw_state_t
	Shadow of the write-only DRW register file plus render statistics. More...

Enumerations
enum	drw_geom_t : uint64_t {   k_drw_base = 0x40444000UL ,   k_drw_span = 0x104UL }
	DRW block geometry (ra8_drw_regs.h, HUM Ch 62). More...
enum	drw_off_t : uint64_t {   k_drw_off_control = 0x000UL ,   k_drw_off_control2 = 0x004UL ,   k_drw_off_color1 = 0x064UL ,   k_drw_off_color2 = 0x068UL ,   k_drw_off_size = 0x078UL ,   k_drw_off_pitch = 0x07CUL ,   k_drw_off_origin = 0x080UL ,   k_drw_off_cachectl = 0x0C4UL ,   k_drw_off_dliststart = 0x0C8UL }
	Register offsets this model tracks (HUM Ch 62.2, ra8_drw_regs.h). More...
enum	drw_dlr_t : uint32_t {   k_drw_dlr_index_mask = 0xFFU ,   k_drw_dlr_b1_boundary = 0x00008000U ,   k_drw_dlr_eol_low = 0xFFU ,   k_drw_dlr_eol_arg_pos = 8U ,   k_drw_dlr_arg_wait = 2U ,   k_drw_dlr_idx_dliststart = 50U ,   k_drw_dlr_bytes_per_word = 4U ,   k_drw_dlr_max_words = 4096U }
	Display-list encoding constants (HUM Ch 62.6; TES D/AVE format). More...
enum	drw_control_t : uint32_t { k_drw_control_limiter_mask = 0x3FU }
	CONTROL bit-field constants (HUM Ch 62.2.1 p 3689). More...
enum	drw_c2_t : uint32_t {   k_drw_c2_patternenable = (1U << 0U) ,   k_drw_c2_textureenable = (1U << 1U) ,   k_drw_c2_useacb = (1U << 3U) ,   k_drw_c2_bsfa = (1U << 6U) ,   k_drw_c2_bdfa = (1U << 7U) ,   k_drw_c2_wfmt_hi_bit = (1U << 8U) ,   k_drw_c2_bsf = (1U << 9U) ,   k_drw_c2_bdf = (1U << 10U) ,   k_drw_c2_bsi = (1U << 11U) ,   k_drw_c2_bdi = (1U << 12U) ,   k_drw_c2_wfmt_lo_pos = 20U ,   k_drw_c2_wfmt_lo_mask = 0x3U ,   k_drw_c2_walpha_pos = 22U ,   k_drw_c2_walpha_mask = 0x3U ,   k_drw_c2_bsia = (1U << 28U) ,   k_drw_c2_bdia = (1U << 29U) }
	CONTROL2 bit-field constants (HUM Ch 62.2.2 pp 3691-3694). More...
enum	drw_cachectl_t : uint32_t { k_drw_cachectl_cenablefx = (1U << 0U) }
	CACHECTL bit-field constants (HUM Ch 62.2.4 p 3694). More...
enum	drw_walpha_t : uint32_t {   k_drw_walpha_color2 = 0U ,   k_drw_walpha_pixel_cov = 1U ,   k_drw_walpha_zero = 2U ,   k_drw_walpha_fb = 3U }
	WRITEALPHA[1:0] codes (HUM Ch 62.2.2 p 3694, USEACB = 0). More...
enum	drw_wfmt_t : uint32_t {   k_drw_wfmt_a8 = 0U ,   k_drw_wfmt_rgb565 = 1U ,   k_drw_wfmt_argb8888 = 2U ,   k_drw_wfmt_argb4444 = 3U }
	WRITEFORMAT[2:0] codes (HUM Ch 62.2.2 p 3692). More...
enum	drw_layout_t : uint32_t {   k_drw_byte_mask = 0xFFU ,   k_drw_a_shift = 24U ,   k_drw_r_shift = 16U ,   k_drw_g_shift = 8U ,   k_drw_alpha_full = 255U ,   k_drw_alpha_round = 127U ,   k_drw_size_w_mask = 0xFFFFU ,   k_drw_size_h_pos = 16U ,   k_drw_rgb565_r_pos = 11U ,   k_drw_rgb565_g_pos = 5U ,   k_drw_argb4444_a_pos = 12U ,   k_drw_nibble_shift = 4U ,   k_drw_r565_shift = 3U ,   k_drw_g565_shift = 2U }
	ARGB8888 channel layout + fixed-point blend constants. More...
enum	drw_bpp_t : uint32_t {   k_drw_bpp_8 = 1U ,   k_drw_bpp_16 = 2U ,   k_drw_bpp_32 = 4U }
	Bytes per framebuffer pixel (HUM Ch 62.3.1.1 p 3707). More...
enum	drw_hwrev_t : uint32_t { k_drw_hwrevision_value = 0x0FBE0107U }
	Hardware revision stamp read back from real EK-RA8D2 silicon. More...
enum	drw_order_t : uint32_t { k_drw_block_order = 160U }
	Per-tick order slot for the DRW block (relative order only). More...

Functions
static uint32_t	internal_drw_chan (uint32_t argb, uint32_t shift)
	Extract one 8-bit channel of an ARGB8888 word.
static uint32_t	internal_drw_bpp (void)
	Framebuffer bytes per pixel for the programmed WRITEFORMAT.
static uint32_t	internal_drw_factor (bool is_alpha, bool invert, uint32_t alpha)
	Resolve one blend factor to its 0..255 numerator.
static uint32_t	internal_drw_mix (uint32_t src, uint32_t dst, uint32_t fs, uint32_t fd)
	Apply one channel of src * fs + dst * fd, rounded and saturated.
static uint32_t	internal_drw_out_alpha (uint32_t src_a, uint32_t dst_a)
	Framebuffer alpha byte per the WRITEALPHA mux or the alpha blend.
static uint32_t	internal_drw_shade (uint32_t dst)
	Composite COLOR1 over one destination pixel, in ARGB8888 space.
static uint32_t	internal_drw_pack (uint32_t argb, uint32_t bpp)
	Narrow an ARGB8888 result to the programmed framebuffer format.
static bool	internal_drw_render_modelled (uint32_t w, uint32_t h)
	Decide whether this render is one the model reproduces faithfully.
static void	internal_drw_render (uc_engine *uc)
	Rasterize the programmed bounding box into emulated memory.
static uint64_t	internal_drw_read (uc_engine *uc, uint64_t addr, unsigned size)
	MMIO read inside the DRW window.
static bool	internal_drw_latch (uint64_t off, uint32_t val)
	Latch one shadowed DRW register; returns false for unknown offsets.
static void	internal_drw_dlr_exec_reg (uc_engine *uc, uint32_t index, uint32_t val)
	Apply one display-list register write; ORIGIN triggers a render.
static void	internal_drw_run_dlist (uc_engine *uc, uint32_t dlist_addr)
	Execute a display list the DLR fetches from emulated memory.
static void	internal_drw_write (uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
	MMIO write inside the DRW window; ORIGIN or DLISTSTART renders.
static void	internal_drw_reset (void)
	Reset the DRW model to power-on state.
static void	internal_drw_report (void)
	End-of-run summary line.
static void	internal_drw_block_register (void)
	Register the DRW block before main (host constructor).

Variables
static drw_state_t	s_drw
	Module-private DRW model state.
static const board_periph_block_t	s_k_drw_block
	DRW block descriptor (self-registered with the core).

Detailed Description

Bench-validated DRW ("D/AVE 2D") rasterizer model for ra8_emulator.

Models the RA8D2 DRW 2D graphics engine (ra8_drw_regs.h, ra8_drw.c) at 0x40444000. ra8_emulator's governing invariant is EIL == HIL: an app must produce the IDENTICAL result in the emulator and on hardware, hardware defects included. Every rule encoded here was measured on an EK-RA8D2 over J-Link, not inferred from the datasheet ideal.

Why the engine looked dead, then looked wrong (issues #247, #170)

The DRW never rasterized on the bench because it was never POWERED: it sits in the graphics power domain, which PDCTRGD gates OFF at reset (HUM Ch 11.2.14 p 452, reset value 0x81; domain contents – MIPI DSI, MIPI CSI, VIN, DRW, GLCDC – in HUM Ch 11.5.1 Table 11.7 p 480). With the domain on, an EK-RA8D2 reads HWREVISION = 0x0FBE0107 and the engine rasterizes. The render was then still wrong in two ways – a 16x16 request painted 8x8, and the alpha byte never reached the framebuffer – because the driver was feeding the spatial limiters absolute pixel coordinates and leaving CONTROL2.WRITEALPHA at its reset value. Both are fixed in ra8_drw.c; the model below reproduces the CORRECTED behaviour.

The geometry rule (bench-measured)

HUM Ch 62.6.2 p 3716: "the 2D Drawing Engine scans the whole bounding box". The bounding box is SIZE (width in [15:0], height in [31:16], HUM Ch 62.2.29 p 3704) anchored at the pixel ORIGIN addresses (HUM Ch 62.2.31 p 3705), stepping PITCH pixels per row. Writing ORIGIN is also the render TRIGGER. So an axis-aligned solid rectangle needs NO spatial limiter: ORIGIN positions it and SIZE sizes it. Confirmed on the bench – with all limiters disabled, SIZE=16x16 at ORIGIN=fb+priv_px(8,8) paints exactly pixels (8,8)..(23,23), and the same SIZE at ORIGIN=fb paints (0,0)..(15,15).

The colour rule (bench-measured)

Colour goes through the blend unit, HUM Ch 62.6.5.1 p 3733: dst = src*fS + dst*fD with fS/fD selected by CONTROL2.{BSF,BSI,BDF,BDI} per Table 62.9. Note the RESET factors are fS = fD = 1, i.e. dst = src + dst: a fill ADDS unless BDI is set. Bench: filling 0xFF00FF00 over a 0x00000010 framebuffer gives 0xFF00FF10 without BDI and 0xFF00FF00 with it.

The alpha rule (bench-measured)

With CONTROL2.USEACB = 0 the framebuffer alpha byte comes from the WRITEALPHA[1:0] mux (CONTROL2 bits 23:22, HUM Ch 62.2.2 p 3694 and Figure 62.23 p 3734), NOT from the colour blend. Its reset value 00 means "use alpha from COLOR2", and COLOR2 is 0 for a plain fill – which is why an opaque 0xFF00FF00 fill read back 0x0000FF00 on the bench. Measured behaviour of all four codes, with COLOR1 = 0xFF00FF00 unless noted:

• 00 -> COLOR2's alpha byte (COLOR2 = 0x80000000 gave 0x8000FF00, and COLOR2's RGB did NOT leak into the result)
• 01 -> source alpha, i.e. COLOR1's alpha scaled by coverage (COLOR1 0x8000FF00 gave 0x8000FF00; opaque gave 0xFF)
• 10 -> forced 0
• 11 -> the framebuffer's existing alpha With USEACB = 1 the alpha channel is blended by the same formula shape using CONTROL2.{BSFA,BSIA,BDFA,BDIA} (HUM Ch 62.6.5.2 p 3734).

Rounding

The bench composite is reproduced bit-exactly by out = (src*fS_num + dst*fD_num + 127) / 255 with the factors expressed in 0..255. Checked against all four channels of drw_blend_demo's source-over layer: source 0x80E04040 over 0xFF202060 gives 0xBF803050 on silicon and from this formula.

What is deliberately NOT modelled

Two configurations are left un-rasterized rather than guessed, because inventing pixels the bench does not produce is the divergence this file exists to prevent. Both fail SAFE – the emulator renders nothing, so an app relying on them goes visibly blank here instead of reporting a false PASS:

• Spatial limiters enabled. The limiter half-plane semantics are only partly characterised. Bench sweeps of a single limiter show the selected half-plane boundary sitting at 16 - START/16 with XADD = +16, and the resulting coverage arriving as alpha 0x01-0x02 rather than 0xFF, so a limiter-driven fill does not composite the way the linear setup in HUM Ch 62.6.2.1 predicts. No in-tree primitive needs them: the corrected rect fill and textured blit both use the bounding box alone.
• Framebuffer cache enabled (CACHECTL.CENABLEFX). On silicon the rendered pixels then sit in the DRW cache and are invisible to the CPU until a CFLUSHFX; bench-confirmed both ways. The cache geometry and its eviction write-back are undocumented, so a partial model would be a guess. The corrected driver leaves the framebuffer cache exactly as ra8_drw_init configured it and no in-tree app enables it.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file board_periph_drw.c.

Enumeration Type Documentation

drw_bpp_t

enum drw_bpp_t : uint32_t

Bytes per framebuffer pixel (HUM Ch 62.3.1.1 p 3707).

Enumerator
k_drw_bpp_8	A8.
k_drw_bpp_16	RGB565 / ARGB4444.
k_drw_bpp_32	ARGB8888.

Definition at line 207 of file board_periph_drw.c.

drw_c2_t

enum drw_c2_t : uint32_t

CONTROL2 bit-field constants (HUM Ch 62.2.2 pp 3691-3694).

Enumerator
k_drw_c2_patternenable	Pattern source.
k_drw_c2_textureenable	Texture source.
k_drw_c2_useacb	Alpha channel blending.
k_drw_c2_bsfa	Alpha src factor is a.
k_drw_c2_bdfa	Alpha dst factor is a.
k_drw_c2_wfmt_hi_bit	WRITEFORMAT[2].
k_drw_c2_bsf	Colour src factor is a.
k_drw_c2_bdf	Colour dst factor is a.
k_drw_c2_bsi	Colour src factor invert.
k_drw_c2_bdi	Colour dst factor invert.
k_drw_c2_wfmt_lo_pos	WRITEFORMAT[1:0] @ 20.
k_drw_c2_wfmt_lo_mask	WRITEFORMAT[1:0] mask.
k_drw_c2_walpha_pos	WRITEALPHA[1:0] @ 22.
k_drw_c2_walpha_mask	WRITEALPHA[1:0] mask.
k_drw_c2_bsia	Alpha src factor invert.
k_drw_c2_bdia	Alpha dst factor invert.

Definition at line 148 of file board_periph_drw.c.

drw_cachectl_t

enum drw_cachectl_t : uint32_t

CACHECTL bit-field constants (HUM Ch 62.2.4 p 3694).

Enumerator
k_drw_cachectl_cenablefx	Framebuffer cache enable.

Definition at line 168 of file board_periph_drw.c.

drw_control_t

enum drw_control_t : uint32_t

CONTROL bit-field constants (HUM Ch 62.2.1 p 3689).

Enumerator
k_drw_control_limiter_mask	LIM1..LIM6 enable bits [5:0].

Definition at line 143 of file board_periph_drw.c.

drw_dlr_t

enum drw_dlr_t : uint32_t

Display-list encoding constants (HUM Ch 62.6; TES D/AVE format).

The DLR fetches 32-bit words. This model executes exactly the encoding the ra8_drw display-list builder emits and bench-verified on the EK-RA8D2 for issue #247: single-register entries – a tag 0x80808000 | index (byte 1 bit 7 marks a one-index entry) followed by one value word – and end-of-list words whose low byte is 0xFF with an argument in byte 1 (2 = wait for the pipeline+cache then continue, the only wait the builder emits; anything else terminates). Register index == byte offset / 4. Any other tag encoding (multi-index packing) is deliberately NOT modelled: it was never observed on the bench, so the model STOPS rather than guess, and an app that relied on it under-renders visibly here instead of a false PASS – the same fail-safe stance as the limiter and FB-cache paths above.

Enumerator
k_drw_dlr_index_mask	Register index in a tag byte.
k_drw_dlr_b1_boundary	Byte 1 bit 7 -> one-index entry.
k_drw_dlr_eol_low	Low byte of an end-of-list word.
k_drw_dlr_eol_arg_pos	End-of-list argument position.
k_drw_dlr_arg_wait	Wait pipe+cache, keep reading.
k_drw_dlr_idx_dliststart	DLISTSTART index (jump / stop).
k_drw_dlr_bytes_per_word	Register index -> byte offset.
k_drw_dlr_max_words	NASA Rule 2 fetch bound.

Definition at line 131 of file board_periph_drw.c.

drw_geom_t

enum drw_geom_t : uint64_t

DRW block geometry (ra8_drw_regs.h, HUM Ch 62).

Enumerator
k_drw_base	DRW Secure base (HUM Ch 62).
k_drw_span	Register window (260 bytes).

Definition at line 97 of file board_periph_drw.c.

drw_hwrev_t

enum drw_hwrev_t : uint32_t

Hardware revision stamp read back from real EK-RA8D2 silicon.

Captured over J-Link with the graphics power domain enabled (HUM Ch 62.2.6 "HWREVISION" p 3696). Reads 0 while the domain is gated.

Enumerator
k_drw_hwrevision_value	Bench-observed HWREVISION.

Definition at line 219 of file board_periph_drw.c.

drw_layout_t

enum drw_layout_t : uint32_t

ARGB8888 channel layout + fixed-point blend constants.

Enumerator
k_drw_byte_mask	One colour channel.
k_drw_a_shift	ARGB8888 alpha byte position.
k_drw_r_shift	ARGB8888 red byte position.
k_drw_g_shift	ARGB8888 green byte position.
k_drw_alpha_full	Blend factor 1.0.
k_drw_alpha_round	Round-to-nearest bias.
k_drw_size_w_mask	SIZE width / height field.
k_drw_size_h_pos	SIZE height in [31:16].
k_drw_rgb565_r_pos	RGB565 red position.
k_drw_rgb565_g_pos	RGB565 green position.
k_drw_argb4444_a_pos	ARGB4444 alpha position.
k_drw_nibble_shift	8 bpc -> 4 bpc.
k_drw_r565_shift	8 bpc -> 5 bpc.
k_drw_g565_shift	8 bpc -> 6 bpc.

Definition at line 189 of file board_periph_drw.c.

drw_off_t

enum drw_off_t : uint64_t

Register offsets this model tracks (HUM Ch 62.2, ra8_drw_regs.h).

Enumerator
k_drw_off_control	W CONTROL / R STATUS.
k_drw_off_control2	W CONTROL2 / R HWREVISION.
k_drw_off_color1	W COLOR1: base colour.
k_drw_off_color2	W COLOR2: secondary colour.
k_drw_off_size	W SIZE: bounding box W/H.
k_drw_off_pitch	W PITCH: framebuffer pitch.
k_drw_off_origin	W ORIGIN: bbox anchor + trigger.
k_drw_off_cachectl	W CACHECTL: cache enable / flush.
k_drw_off_dliststart	W DLISTSTART: kick display list.

Definition at line 103 of file board_periph_drw.c.

drw_order_t

enum drw_order_t : uint32_t

Per-tick order slot for the DRW block (relative order only).

Enumerator
k_drw_block_order	After the DOC block; report order.

Definition at line 224 of file board_periph_drw.c.

drw_walpha_t

enum drw_walpha_t : uint32_t

WRITEALPHA[1:0] codes (HUM Ch 62.2.2 p 3694, USEACB = 0).

Enumerator
k_drw_walpha_color2	Alpha from COLOR2.
k_drw_walpha_pixel_cov	Source alpha (coverage).
k_drw_walpha_zero	Forced 0.0.
k_drw_walpha_fb	Alpha from framebuffer.

Definition at line 173 of file board_periph_drw.c.

drw_wfmt_t

enum drw_wfmt_t : uint32_t

WRITEFORMAT[2:0] codes (HUM Ch 62.2.2 p 3692).

Enumerator
k_drw_wfmt_a8	8 bpp A8.
k_drw_wfmt_rgb565	16 bpp RGB565.
k_drw_wfmt_argb8888	32 bpp ARGB8888.
k_drw_wfmt_argb4444	16 bpp ARGB4444.

Definition at line 181 of file board_periph_drw.c.

Function Documentation

internal_drw_block_register()

void internal_drw_block_register ( void )

static

Register the DRW block before main (host constructor).

Definition at line 824 of file board_periph_drw.c.

References board_periph_register_block(), RA8_INTERNAL, and s_k_drw_block.

internal_drw_bpp()

uint32_t internal_drw_bpp ( void )

static

Framebuffer bytes per pixel for the programmed WRITEFORMAT.

Framebuffer bytes per pixel for the programmed writeformat; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Returns

The drw bpp result produced by the board periph drw model.

Return values

value

The operation-specific drw bpp value.

Precondition

Arguments satisfy the ranges documented for drw bpp.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 292 of file board_periph_drw.c.

References k_drw_bpp_16, k_drw_bpp_32, k_drw_bpp_8, k_drw_c2_wfmt_hi_bit, k_drw_c2_wfmt_lo_mask, k_drw_c2_wfmt_lo_pos, k_drw_wfmt_a8, k_drw_wfmt_argb4444, k_drw_wfmt_rgb565, RA8_INTERNAL, and s_drw.

Referenced by internal_drw_render().

internal_drw_chan()

uint32_t internal_drw_chan ( uint32_t argb, uint32_t shift )

static

Extract one 8-bit channel of an ARGB8888 word.

Extract one 8-bit channel of an argb8888 word; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in]	argb	Argb input used by the operation.
[in]	shift	Shift input used by the operation.

Returns

The drw chan result produced by the board periph drw model.

Return values

value

The operation-specific drw chan value.

Precondition

Arguments satisfy the ranges documented for drw chan.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 277 of file board_periph_drw.c.

References k_drw_byte_mask, and RA8_INTERNAL.

Referenced by internal_drw_out_alpha(), internal_drw_pack(), and internal_drw_shade().

internal_drw_dlr_exec_reg()

void internal_drw_dlr_exec_reg ( uc_engine * uc, uint32_t index, uint32_t val )

static

Apply one display-list register write; ORIGIN triggers a render.

Apply one display-list register write; origin triggers a render; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	index	Index input used by the operation.
[in]	val	Register or payload value processed by the operation.

Precondition

Arguments satisfy the ranges documented for drw dlr exec reg.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 658 of file board_periph_drw.c.

References internal_drw_latch(), internal_drw_render(), k_drw_dlr_bytes_per_word, k_drw_off_origin, RA8_INTERNAL, and s_drw.

Referenced by internal_drw_run_dlist().

internal_drw_factor()

uint32_t internal_drw_factor ( bool is_alpha, bool invert, uint32_t alpha )

static

Resolve one blend factor to its 0..255 numerator.

HUM Ch 62.6.5.1 p 3733: the factor is 1 when the "is alpha" flag and the invert flag are both clear, alpha when "is alpha" is set alone, 0 when invert is set alone, and 1 - alpha when both are set. Shared by the colour and the alpha channel because HUM Ch 62.6.5.2 p 3734 uses the identical formula shape.

Parameters

[in]	is_alpha	CONTROL2 BSF / BDF / BSFA / BDFA for this factor.
[in]	invert	CONTROL2 BSI / BDI / BSIA / BDIA for this factor.
[in]	alpha	Source alpha in 0..255.

Returns

Factor numerator in 0..255 (denominator 255).

MC/DC:

Two independent single-condition branches, four reachable outcomes, all four exercised by the bench vectors in the file header: reset factors (both clear -> 1), SRC_ONE (invert alone -> 0), and source-over (is_alpha alone -> alpha; both -> 1 - alpha).

Return values

value

The operation-specific drw factor value.

Precondition

Arguments satisfy the ranges documented for drw factor.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 335 of file board_periph_drw.c.

References k_drw_alpha_full, and RA8_INTERNAL.

Referenced by internal_drw_out_alpha(), and internal_drw_shade().

internal_drw_latch()

bool internal_drw_latch ( uint64_t off, uint32_t val )

static

Latch one shadowed DRW register; returns false for unknown offsets.

Latch one shadowed drw register; returns false for unknown offsets; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in]	off	Register or byte offset addressed by the operation.
[in]	val	Register or payload value processed by the operation.

Returns

The drw latch result produced by the board periph drw model.

Return values

true	The drw latch condition holds or completed successfully; false otherwise.

Precondition

Arguments satisfy the ranges documented for drw latch.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 616 of file board_periph_drw.c.

References k_drw_off_cachectl, k_drw_off_color1, k_drw_off_color2, k_drw_off_control, k_drw_off_control2, k_drw_off_pitch, k_drw_off_size, RA8_INTERNAL, and s_drw.

Referenced by internal_drw_dlr_exec_reg(), and internal_drw_write().

internal_drw_mix()

uint32_t internal_drw_mix ( uint32_t src, uint32_t dst, uint32_t fs, uint32_t fd )

static

Apply one channel of src * fs + dst * fd, rounded and saturated.

Multiplies the source and destination channels by their respective blend factors, rounds the combined numerator, and clamps the result to one byte.

Parameters

[in]	src	Source storage consumed by the operation.
[in]	dst	Destination storage receiving the result.
[in]	fs	Fs input used by the operation.
[in]	fd	Open raw descriptor used for the transfer.

Returns

The drw mix result produced by the board periph drw model.

Return values

value

The operation-specific drw mix value.

Precondition

Each channel and factor is within its documented unsigned range.

The call executes on the emulator's single owning thread.

Postcondition

The returned value is no greater than k_drw_byte_mask.

Caller-supplied storage and model state remain unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 361 of file board_periph_drw.c.

References k_drw_alpha_full, k_drw_alpha_round, k_drw_byte_mask, and RA8_INTERNAL.

Referenced by internal_drw_out_alpha(), and internal_drw_shade().

internal_drw_out_alpha()

uint32_t internal_drw_out_alpha ( uint32_t src_a, uint32_t dst_a )

static

Framebuffer alpha byte per the WRITEALPHA mux or the alpha blend.

Framebuffer alpha byte per the writealpha mux or the alpha blend; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in]	src_a	Src a input used by the operation.
[in]	dst_a	Dst a input used by the operation.

Returns

The drw out alpha result produced by the board periph drw model.

Return values

value

The operation-specific drw out alpha value.

Precondition

Arguments satisfy the ranges documented for drw out alpha.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 380 of file board_periph_drw.c.

References internal_drw_chan(), internal_drw_factor(), internal_drw_mix(), k_drw_a_shift, k_drw_c2_bdfa, k_drw_c2_bdia, k_drw_c2_bsfa, k_drw_c2_bsia, k_drw_c2_useacb, k_drw_c2_walpha_mask, k_drw_c2_walpha_pos, k_drw_walpha_color2, k_drw_walpha_pixel_cov, k_drw_walpha_zero, RA8_INTERNAL, and s_drw.

Referenced by internal_drw_shade().

internal_drw_pack()

uint32_t internal_drw_pack ( uint32_t argb, uint32_t bpp )

static

Narrow an ARGB8888 result to the programmed framebuffer format.

Narrow an argb8888 result to the programmed framebuffer format; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in]	argb	Argb input used by the operation.
[in]	bpp	Bpp input used by the operation.

Returns

The drw pack result produced by the board periph drw model.

Return values

value

The operation-specific drw pack value.

Precondition

Arguments satisfy the ranges documented for drw pack.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 456 of file board_periph_drw.c.

References internal_drw_chan(), k_drw_a_shift, k_drw_argb4444_a_pos, k_drw_bpp_32, k_drw_bpp_8, k_drw_c2_wfmt_lo_mask, k_drw_c2_wfmt_lo_pos, k_drw_g565_shift, k_drw_g_shift, k_drw_nibble_shift, k_drw_r565_shift, k_drw_r_shift, k_drw_rgb565_g_pos, k_drw_rgb565_r_pos, k_drw_wfmt_argb4444, RA8_INTERNAL, and s_drw.

Referenced by internal_drw_render().

internal_drw_read()

uint64_t internal_drw_read ( uc_engine * uc, uint64_t addr, unsigned size )

static

MMIO read inside the DRW window.

MMIO read inside the drw window; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.

Returns

The drw read result produced by the board periph drw model.

Return values

value

The operation-specific drw read value.

Precondition

Arguments satisfy the ranges documented for drw read.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 569 of file board_periph_drw.c.

References k_drw_base, k_drw_hwrevision_value, k_drw_off_control, k_drw_off_control2, priv_board_pdctr_graphics_powered(), and RA8_INTERNAL.

internal_drw_render()

void internal_drw_render ( uc_engine * uc )

static

Rasterize the programmed bounding box into emulated memory.

Rasterize the programmed bounding box into emulated memory; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in,out]

uc

Unicorn engine whose emulated state is read or updated.

Precondition

Arguments satisfy the ranges documented for drw render.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 527 of file board_periph_drw.c.

References emu_mem_read(), emu_mem_write(), internal_drw_bpp(), internal_drw_pack(), internal_drw_render_modelled(), internal_drw_shade(), k_drw_size_h_pos, k_drw_size_w_mask, RA8_INTERNAL, and s_drw.

Referenced by internal_drw_dlr_exec_reg(), and internal_drw_write().

internal_drw_render_modelled()

bool internal_drw_render_modelled ( uint32_t w, uint32_t h )

static

Decide whether this render is one the model reproduces faithfully.

Parameters

[in]	w	Bounding box width in pixels, from SIZE.
[in]	h	Bounding box height in pixels, from SIZE.

Returns

true when the render may proceed.

Return values

false

Domain dark, geometry unprogrammed, or an unmodelled path.

MC/DC:

A chain of independent single-condition rejects. Vectors: powered + geometry programmed + no limiter + no FB cache + solid source -> true (control); each reject condition flipped alone -> false, proving each independently determines the outcome.

Decide whether this render is one the model reproduces faithfully; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Precondition

Arguments satisfy the ranges documented for drw render modelled.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 500 of file board_periph_drw.c.

References k_drw_c2_patternenable, k_drw_c2_textureenable, k_drw_cachectl_cenablefx, k_drw_control_limiter_mask, priv_board_pdctr_graphics_powered(), RA8_INTERNAL, and s_drw.

Referenced by internal_drw_render().

internal_drw_report()

void internal_drw_report ( void )

static

End-of-run summary line.

End-of-run summary line; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Precondition

Arguments satisfy the ranges documented for drw report.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 788 of file board_periph_drw.c.

References priv_emu_io_errf(), RA8_INTERNAL, and s_drw.

internal_drw_reset()

void internal_drw_reset ( void )

static

Reset the DRW model to power-on state.

Reset the drw model to power-on state; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Precondition

Arguments satisfy the ranges documented for drw reset.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 775 of file board_periph_drw.c.

References RA8_INTERNAL, and s_drw.

internal_drw_run_dlist()

void internal_drw_run_dlist ( uc_engine * uc, uint32_t dlist_addr )

static

Execute a display list the DLR fetches from emulated memory.

Mirrors the DRW display-list reader for the encoding the ra8_drw builder emits: single-register entries and end-of-list words (see drw_dlr_t). Each ORIGIN write inside the list rasterizes exactly as a CPU ORIGIN write does, so a clear+fill list reproduces the byte-identical framebuffer the bench produced for issue #247. The fetch loop is bounded by k_drw_dlr_max_words (NASA Rule 2). Any tag encoding the builder never emits stops the list – unmodelled rather than guessed.

Parameters

[in]	uc	Emulator engine (framebuffer + display-list memory).
[in]	dlist_addr	Display-list base address (DLISTSTART value).

Precondition

Arguments satisfy the ranges documented for drw run dlist.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 689 of file board_periph_drw.c.

References emu_mem_read(), internal_drw_dlr_exec_reg(), k_drw_dlr_arg_wait, k_drw_dlr_b1_boundary, k_drw_dlr_bytes_per_word, k_drw_dlr_eol_arg_pos, k_drw_dlr_eol_low, k_drw_dlr_idx_dliststart, k_drw_dlr_index_mask, k_drw_dlr_max_words, and RA8_INTERNAL.

Referenced by internal_drw_write().

internal_drw_shade()

uint32_t internal_drw_shade ( uint32_t dst )

static

Composite COLOR1 over one destination pixel, in ARGB8888 space.

Composite color1 over one destination pixel, in argb8888 space; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in]

dst

Destination storage receiving the result.

Returns

The drw shade result produced by the board periph drw model.

Return values

value

The operation-specific drw shade value.

Precondition

Arguments satisfy the ranges documented for drw shade.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 418 of file board_periph_drw.c.

References internal_drw_chan(), internal_drw_factor(), internal_drw_mix(), internal_drw_out_alpha(), k_drw_a_shift, k_drw_c2_bdf, k_drw_c2_bdi, k_drw_c2_bsf, k_drw_c2_bsi, k_drw_g_shift, k_drw_r_shift, RA8_INTERNAL, and s_drw.

Referenced by internal_drw_render().

internal_drw_write()

void internal_drw_write ( uc_engine * uc, uint64_t addr, unsigned size, uint64_t value )

static

MMIO write inside the DRW window; ORIGIN or DLISTSTART renders.

MMIO write inside the drw window; origin or dliststart renders; this step is contained within the board periph drw model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.
[in]	value	Register or payload value involved in the operation.

Precondition

Arguments satisfy the ranges documented for drw write.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph drw model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 737 of file board_periph_drw.c.

References internal_drw_latch(), internal_drw_render(), internal_drw_run_dlist(), k_drw_base, k_drw_off_dliststart, k_drw_off_origin, priv_board_pdctr_graphics_powered(), and s_drw.

Variable Documentation

s_drw

drw_state_t s_drw

static

Module-private DRW model state.

Note

Reset by internal_drw_reset on every emulated system reset.

Warning

Not thread-safe; ra8_emulator drives one CPU thread.

Definition at line 263 of file board_periph_drw.c.

Referenced by internal_drw_bpp(), internal_drw_dlr_exec_reg(), internal_drw_latch(), internal_drw_out_alpha(), internal_drw_pack(), internal_drw_render(), internal_drw_render_modelled(), internal_drw_report(), internal_drw_reset(), internal_drw_shade(), and internal_drw_write().

s_k_drw_block

const board_periph_block_t s_k_drw_block

static

Initial value:

                                                = {
  .base   = (uint64_t)k_drw_base,
  .span   = (uint64_t)k_drw_span,
  .order  = (uint32_t)k_drw_block_order,
  .read   = internal_drw_read,
  .write  = internal_drw_write,
  .tick   = nullptr,
  .reset  = internal_drw_reset,
  .report = internal_drw_report,
  .name   = "DRW",
}

DRW block descriptor (self-registered with the core).

Definition at line 811 of file board_periph_drw.c.

Referenced by internal_drw_block_register().