board_periph_drw.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_periph_block.h"
#include "board_periph_pdctr_internal.h"
#include "emu_host_io_internal.h"

typedef enum : uint64_t {
  k_drw_base = 0x40444000UL, 
  k_drw_span = 0x104UL,      
} drw_geom_t;

typedef enum : uint64_t {
  k_drw_off_control    = 0x000UL, 
  k_drw_off_control2   = 0x004UL, 
  k_drw_off_color1     = 0x064UL, 
  k_drw_off_color2     = 0x068UL, 
  k_drw_off_size       = 0x078UL, 
  k_drw_off_pitch      = 0x07CUL, 
  k_drw_off_origin     = 0x080UL, 
  k_drw_off_cachectl   = 0x0C4UL, 
  k_drw_off_dliststart = 0x0C8UL, 
} drw_off_t;

typedef enum : uint32_t {
  k_drw_dlr_index_mask     = 0xFFU,       
  k_drw_dlr_b1_boundary    = 0x00008000U, 
  k_drw_dlr_eol_low        = 0xFFU,       
  k_drw_dlr_eol_arg_pos    = 8U,          
  k_drw_dlr_arg_wait       = 2U,          
  k_drw_dlr_idx_dliststart = 50U,         
  k_drw_dlr_bytes_per_word = 4U,          
  k_drw_dlr_max_words      = 4096U,       
} drw_dlr_t;

typedef enum : uint32_t {
  k_drw_control_limiter_mask = 0x3FU, 
} drw_control_t;

typedef enum : uint32_t {
  k_drw_c2_patternenable = (1U << 0U),  
  k_drw_c2_textureenable = (1U << 1U),  
  k_drw_c2_useacb        = (1U << 3U),  
  k_drw_c2_bsfa          = (1U << 6U),  
  k_drw_c2_bdfa          = (1U << 7U),  
  k_drw_c2_wfmt_hi_bit   = (1U << 8U),  
  k_drw_c2_bsf           = (1U << 9U),  
  k_drw_c2_bdf           = (1U << 10U), 
  k_drw_c2_bsi           = (1U << 11U), 
  k_drw_c2_bdi           = (1U << 12U), 
  k_drw_c2_wfmt_lo_pos   = 20U,         
  k_drw_c2_wfmt_lo_mask  = 0x3U,        
  k_drw_c2_walpha_pos    = 22U,         
  k_drw_c2_walpha_mask   = 0x3U,        
  k_drw_c2_bsia          = (1U << 28U), 
  k_drw_c2_bdia          = (1U << 29U), 
} drw_c2_t;

typedef enum : uint32_t {
  k_drw_cachectl_cenablefx = (1U << 0U), 
} drw_cachectl_t;

typedef enum : uint32_t {
  k_drw_walpha_color2    = 0U, 
  k_drw_walpha_pixel_cov = 1U, 
  k_drw_walpha_zero      = 2U, 
  k_drw_walpha_fb        = 3U, 
} drw_walpha_t;

typedef enum : uint32_t {
  k_drw_wfmt_a8       = 0U, 
  k_drw_wfmt_rgb565   = 1U, 
  k_drw_wfmt_argb8888 = 2U, 
  k_drw_wfmt_argb4444 = 3U, 
} drw_wfmt_t;

typedef enum : uint32_t {
  k_drw_byte_mask      = 0xFFU,   
  k_drw_a_shift        = 24U,     
  k_drw_r_shift        = 16U,     
  k_drw_g_shift        = 8U,      
  k_drw_alpha_full     = 255U,    
  k_drw_alpha_round    = 127U,    
  k_drw_size_w_mask    = 0xFFFFU, 
  k_drw_size_h_pos     = 16U,     
  k_drw_rgb565_r_pos   = 11U,     
  k_drw_rgb565_g_pos   = 5U,      
  k_drw_argb4444_a_pos = 12U,     
  k_drw_nibble_shift   = 4U,      
  k_drw_r565_shift     = 3U,      
  k_drw_g565_shift     = 2U,      
} drw_layout_t;

typedef enum : uint32_t {
  k_drw_bpp_8  = 1U, 
  k_drw_bpp_16 = 2U, 
  k_drw_bpp_32 = 4U, 
} drw_bpp_t;

typedef enum : uint32_t {
  k_drw_hwrevision_value = 0x0FBE0107U, 
} drw_hwrev_t;

typedef enum : uint32_t {
  k_drw_block_order = 160U, 
} drw_order_t;

typedef struct {
  uint32_t control;  
  uint32_t control2; 
  uint32_t color1;   
  uint32_t color2;   
  uint32_t size;     
  uint32_t pitch;    
  uint32_t origin;   
  uint32_t cachectl; 
  uint32_t renders;  
  uint32_t skipped;  
  uint32_t last_w;   
  uint32_t last_h;   
} drw_state_t;

static drw_state_t s_drw;

RA8_INTERNAL static uint32_t internal_drw_chan(uint32_t argb, uint32_t shift)
{
  return (argb >> shift) & (uint32_t)k_drw_byte_mask;
}

RA8_INTERNAL static uint32_t internal_drw_bpp(void)
{
  const uint32_t lo =
    (s_drw.control2 >> (uint32_t)k_drw_c2_wfmt_lo_pos) & (uint32_t)k_drw_c2_wfmt_lo_mask;
  const uint32_t hi = ((s_drw.control2 & (uint32_t)k_drw_c2_wfmt_hi_bit) != 0U) ? 0x4U : 0x0U;
  switch (lo | hi) {
    case (uint32_t)k_drw_wfmt_a8:
      return (uint32_t)k_drw_bpp_8;
    case (uint32_t)k_drw_wfmt_rgb565:
    case (uint32_t)k_drw_wfmt_argb4444:
      return (uint32_t)k_drw_bpp_16;
    default:
      /* ARGB8888 and the prohibited codes both take the 32-bit width. */
      return (uint32_t)k_drw_bpp_32;
  }
}

RA8_INTERNAL static uint32_t internal_drw_factor(bool is_alpha, bool invert, uint32_t alpha)
{
  if (is_alpha) {
    return invert ? ((uint32_t)k_drw_alpha_full - alpha) : alpha;
  }
  return invert ? 0U : (uint32_t)k_drw_alpha_full;
}

RA8_INTERNAL static uint32_t internal_drw_mix(uint32_t src, uint32_t dst, uint32_t fs, uint32_t fd)
{
  const uint32_t num = (src * fs) + (dst * fd) + (uint32_t)k_drw_alpha_round;
  const uint32_t out = num / (uint32_t)k_drw_alpha_full;
  return (out > (uint32_t)k_drw_byte_mask) ? (uint32_t)k_drw_byte_mask : out;
}

RA8_INTERNAL static uint32_t internal_drw_out_alpha(uint32_t src_a, uint32_t dst_a)
{
  if ((s_drw.control2 & (uint32_t)k_drw_c2_useacb) != 0U) {
    /* HUM Ch 62.6.5.2 "Alpha Channel Blending" p 3734 */
    const uint32_t fsa = internal_drw_factor((s_drw.control2 & (uint32_t)k_drw_c2_bsfa) != 0U,
                                             (s_drw.control2 & (uint32_t)k_drw_c2_bsia) != 0U,
                                             src_a);
    const uint32_t fda = internal_drw_factor((s_drw.control2 & (uint32_t)k_drw_c2_bdfa) != 0U,
                                             (s_drw.control2 & (uint32_t)k_drw_c2_bdia) != 0U,
                                             src_a);
    return internal_drw_mix(src_a, dst_a, fsa, fda);
  }
  /* HUM Ch 62.2.2 "WRITEALPHA[1:0]" p 3694 -- Figure 62.23 p 3734 */
  const uint32_t code =
    (s_drw.control2 >> (uint32_t)k_drw_c2_walpha_pos) & (uint32_t)k_drw_c2_walpha_mask;
  switch (code) {
    case (uint32_t)k_drw_walpha_color2:
      return internal_drw_chan(s_drw.color2, (uint32_t)k_drw_a_shift);
    case (uint32_t)k_drw_walpha_pixel_cov:
      return src_a;
    case (uint32_t)k_drw_walpha_zero:
      return 0U;
    default:
      return dst_a;
  }
}

RA8_INTERNAL static uint32_t internal_drw_shade(uint32_t dst)
{
  const uint32_t src_a = internal_drw_chan(s_drw.color1, (uint32_t)k_drw_a_shift);
  const uint32_t fs    = internal_drw_factor((s_drw.control2 & (uint32_t)k_drw_c2_bsf) != 0U,
                                             (s_drw.control2 & (uint32_t)k_drw_c2_bsi) != 0U,
                                             src_a);
  const uint32_t fd    = internal_drw_factor((s_drw.control2 & (uint32_t)k_drw_c2_bdf) != 0U,
                                             (s_drw.control2 & (uint32_t)k_drw_c2_bdi) != 0U,
                                             src_a);
 
  const uint32_t r = internal_drw_mix(internal_drw_chan(s_drw.color1, (uint32_t)k_drw_r_shift),
                                      internal_drw_chan(dst, (uint32_t)k_drw_r_shift),
                                      fs,
                                      fd);
  const uint32_t g = internal_drw_mix(internal_drw_chan(s_drw.color1, (uint32_t)k_drw_g_shift),
                                      internal_drw_chan(dst, (uint32_t)k_drw_g_shift),
                                      fs,
                                      fd);
  const uint32_t b =
    internal_drw_mix(internal_drw_chan(s_drw.color1, 0U), internal_drw_chan(dst, 0U), fs, fd);
  const uint32_t a = internal_drw_out_alpha(src_a, internal_drw_chan(dst, (uint32_t)k_drw_a_shift));
 
  return (a << (uint32_t)k_drw_a_shift) | (r << (uint32_t)k_drw_r_shift) |
         (g << (uint32_t)k_drw_g_shift) | b;
}

RA8_INTERNAL static uint32_t internal_drw_pack(uint32_t argb, uint32_t bpp)
{
  if (bpp == (uint32_t)k_drw_bpp_32) {
    return argb;
  }
  const uint32_t a = internal_drw_chan(argb, (uint32_t)k_drw_a_shift);
  if (bpp == (uint32_t)k_drw_bpp_8) {
    return a;
  }
  const uint32_t r = internal_drw_chan(argb, (uint32_t)k_drw_r_shift);
  const uint32_t g = internal_drw_chan(argb, (uint32_t)k_drw_g_shift);
  const uint32_t b = internal_drw_chan(argb, 0U);
  const uint32_t lo =
    (s_drw.control2 >> (uint32_t)k_drw_c2_wfmt_lo_pos) & (uint32_t)k_drw_c2_wfmt_lo_mask;
  if (lo == (uint32_t)k_drw_wfmt_argb4444) {
    return ((a >> (uint32_t)k_drw_nibble_shift) << (uint32_t)k_drw_argb4444_a_pos) |
           ((r >> (uint32_t)k_drw_nibble_shift) << (uint32_t)k_drw_g_shift) |
           ((g >> (uint32_t)k_drw_nibble_shift) << (uint32_t)k_drw_nibble_shift) |
           (b >> (uint32_t)k_drw_nibble_shift);
  }
  return ((r >> (uint32_t)k_drw_r565_shift) << (uint32_t)k_drw_rgb565_r_pos) |
         ((g >> (uint32_t)k_drw_g565_shift) << (uint32_t)k_drw_rgb565_g_pos) |
         (b >> (uint32_t)k_drw_r565_shift);
}

RA8_INTERNAL static bool internal_drw_render_modelled(uint32_t w, uint32_t h)
{
  if (!priv_board_pdctr_graphics_powered()) {
    return false; /* Dark domain: writes are lost on silicon. */
  }
  if ((w == 0U) || (h == 0U) || (s_drw.pitch == 0U) || (s_drw.origin == 0U)) {
    return false; /* Nothing programmed yet -- e.g. the init ORIGIN write. */
  }
  if ((s_drw.control & (uint32_t)k_drw_control_limiter_mask) != 0U) {
    return false; /* Limiter semantics uncharacterised -- see file header. */
  }
  if ((s_drw.cachectl & (uint32_t)k_drw_cachectl_cenablefx) != 0U) {
    return false; /* FB cache holds the pixels -- see file header. */
  }
  const uint32_t sources = (uint32_t)k_drw_c2_patternenable | (uint32_t)k_drw_c2_textureenable;
  return (s_drw.control2 & sources) == 0U;
}

RA8_INTERNAL static void internal_drw_render(uc_engine* uc)
{
  const uint32_t w = s_drw.size & (uint32_t)k_drw_size_w_mask;
  const uint32_t h = (s_drw.size >> (uint32_t)k_drw_size_h_pos) & (uint32_t)k_drw_size_w_mask;
 
  if (!internal_drw_render_modelled(w, h)) {
    if ((w != 0U) && (h != 0U) && (s_drw.origin != 0U)) {
      s_drw.skipped++;
    }
    return;
  }
 
  const uint32_t bpp = internal_drw_bpp();
  for (uint32_t row = 0U; row < h; ++row) {
    const uint64_t line =
      (uint64_t)s_drw.origin + ((uint64_t)row * (uint64_t)s_drw.pitch * (uint64_t)bpp);
    for (uint32_t col = 0U; col < w; ++col) {
      const uint64_t addr = line + ((uint64_t)col * (uint64_t)bpp);
      uint32_t       dst  = 0U;
      (void)emu_mem_read(uc, addr, &dst, (size_t)bpp);
      const uint32_t out = internal_drw_pack(internal_drw_shade(dst), bpp);
      (void)emu_mem_write(uc, addr, &out, (size_t)bpp);
    }
  }
  s_drw.renders++;
  s_drw.last_w = w;
  s_drw.last_h = h;
}

RA8_INTERNAL static uint64_t internal_drw_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint64_t off = addr - (uint64_t)k_drw_base;
  switch (off) {
    case (uint64_t)k_drw_off_control:
      /* HUM Ch 62.2.5 "STATUS: Status Control Register" p 3695. The model
       * rasterizes synchronously on the ORIGIN write, so the engine is never
       * observably busy and latches no IRQ or bus error: STATUS reads
       * all-zero and ra8_drw_wait_idle succeeds on its first poll.
       *
       * This MUST return explicitly rather than fall through to HWREVISION:
       * the two registers are read aliases at different offsets carrying
       * different values, and sharing an arm made ra8_drw_wait_idle poll
       * STATUS, see the revision stamp, never observe idle, and time out. */
      return 0U;
    case (uint64_t)k_drw_off_control2:
      /* HUM Ch 62.2.6 "HWREVISION: Hardware Revision Register" p 3696.
       * Reads 0 while the graphics power domain is gated (HUM Ch 11.2.14
       * p 452) and 0x0FBE0107 once it is powered -- both bench-captured, so
       * firmware that skips the power-domain bring-up sees the dead register
       * here exactly as it does on the bench. */
      if (!priv_board_pdctr_graphics_powered()) {
        return 0U;
      }
      return (uint64_t)k_drw_hwrevision_value;
    default:
      /* Every other DRW register is write-only on silicon (HUM Ch 62.2) and
       * the driver shadows what it needs, so a deterministic zero is both
       * harmless and faithful. */
      return 0U;
  }
}

RA8_INTERNAL static bool internal_drw_latch(uint64_t off, uint32_t val)
{
  switch (off) {
    case (uint64_t)k_drw_off_control:
      s_drw.control = val;
      return true;
    case (uint64_t)k_drw_off_control2:
      s_drw.control2 = val;
      return true;
    case (uint64_t)k_drw_off_color1:
      s_drw.color1 = val;
      return true;
    case (uint64_t)k_drw_off_color2:
      s_drw.color2 = val;
      return true;
    case (uint64_t)k_drw_off_size:
      s_drw.size = val;
      return true;
    case (uint64_t)k_drw_off_pitch:
      s_drw.pitch = val;
      return true;
    case (uint64_t)k_drw_off_cachectl:
      s_drw.cachectl = val;
      return true;
    default:
      /* Limiter, texture, CLUT and IRQ registers are accepted and discarded:
       * the modelled render path does not consume them. */
      return false;
  }
}

RA8_INTERNAL static void internal_drw_dlr_exec_reg(uc_engine* uc, uint32_t index, uint32_t val)
{
  const uint64_t off = (uint64_t)index * (uint64_t)k_drw_dlr_bytes_per_word;
  if (off == (uint64_t)k_drw_off_origin) {
    /* Same trigger as a CPU ORIGIN write: anchor the box and rasterize. */
    s_drw.origin = val;
    internal_drw_render(uc);
    return;
  }
  (void)internal_drw_latch(off, val);
}

RA8_INTERNAL static void internal_drw_run_dlist(uc_engine* uc, uint32_t dlist_addr)
{
  uint32_t addr = dlist_addr;
  for (uint32_t fetched = 0U; fetched < (uint32_t)k_drw_dlr_max_words; ++fetched) {
    uint32_t tag = 0U;
    (void)emu_mem_read(uc, (uint64_t)addr, &tag, sizeof(tag));
    addr += (uint32_t)k_drw_dlr_bytes_per_word;
 
    if ((tag & (uint32_t)k_drw_dlr_b1_boundary) != 0U) {
      /* One-index entry: byte 0 is a register, one value word follows. */
      const uint32_t index = tag & (uint32_t)k_drw_dlr_index_mask;
      if (index == (uint32_t)k_drw_dlr_idx_dliststart) {
        return; /* display-list jump / stop */
      }
      uint32_t val = 0U;
      (void)emu_mem_read(uc, (uint64_t)addr, &val, sizeof(val));
      addr += (uint32_t)k_drw_dlr_bytes_per_word;
      internal_drw_dlr_exec_reg(uc, index, val);
      continue;
    }
    if ((tag & (uint32_t)k_drw_dlr_index_mask) == (uint32_t)k_drw_dlr_eol_low) {
      /* End-of-list word: byte 1 is the argument. The builder emits only the
       * pipeline+cache wait (2, a synchronous no-op here); every other value
       * terminates. */
      const uint32_t arg =
        (tag >> (uint32_t)k_drw_dlr_eol_arg_pos) & (uint32_t)k_drw_dlr_index_mask;
      if (arg == (uint32_t)k_drw_dlr_arg_wait) {
        continue;
      }
      return; /* terminate */
    }
    return; /* unmodelled multi-index packing: stop, do not guess */
  }
}

RA8_INTERNAL static void
internal_drw_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)size;
  const uint64_t off = addr - (uint64_t)k_drw_base;
  const uint32_t val = (uint32_t)value;
 
  /* While the graphics power domain is gated the block is unpowered and every
   * write is LOST on silicon (HUM Ch 11.2.14 p 452), so the shadow must not
   * latch it either -- otherwise firmware that skips the bring-up would
   * render here and not on the bench. */
  if (!priv_board_pdctr_graphics_powered()) {
    return;
  }
 
  if (off == (uint64_t)k_drw_off_origin) {
    /* HUM Ch 62.2.31 p 3705: writing ORIGIN both anchors the bounding box and
     * TRIGGERS the render. */
    s_drw.origin = val;
    internal_drw_render(uc);
    return;
  }
  if (off == (uint64_t)k_drw_off_dliststart) {
    /* HUM Ch 62.2.32 p 3705: writing DLISTSTART kicks the display-list reader,
     * which executes the list from RAM (issue #247 loop-stable clear+fill). */
    internal_drw_run_dlist(uc, val);
    return;
  }
  (void)internal_drw_latch(off, val);
}

RA8_INTERNAL static void internal_drw_reset(void)
{
  s_drw = (drw_state_t){};
}

RA8_INTERNAL static void internal_drw_report(void)
{
  if ((s_drw.renders == 0U) && (s_drw.skipped == 0U)) {
    return;
  }
  if (s_drw.skipped != 0U) {
    /* Loud: an app reached a DRW configuration this model declines to
     * reproduce, so the emulated framebuffer is NOT what the bench shows. */
    (void)priv_emu_io_errf("  DRW           : %u boxes rasterized (last %ux%u), "
                           "%u DECLINED (limiter / FB-cache / textured path unmodelled)\n",
                           s_drw.renders,
                           s_drw.last_w,
                           s_drw.last_h,
                           s_drw.skipped);
    return;
  }
  (void)priv_emu_io_errf("  DRW           : %u boxes rasterized (last %ux%u)\n",
                         s_drw.renders,
                         s_drw.last_w,
                         s_drw.last_h);
}

static const board_periph_block_t s_k_drw_block = {
  .base   = (uint64_t)k_drw_base,
  .span   = (uint64_t)k_drw_span,
  .order  = (uint32_t)k_drw_block_order,
  .read   = internal_drw_read,
  .write  = internal_drw_write,
  .tick   = nullptr,
  .reset  = internal_drw_reset,
  .report = internal_drw_report,
  .name   = "DRW",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_drw_block_register(void)
{
  board_periph_register_block(&s_k_drw_block);
}