ra8_drw_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_drw_base_addr    = 0x40444000UL, 
  k_ra8_drw_ns_base_addr = 0x50444000UL, 
} ra8_drw_addr_t;

typedef enum : uint16_t {
  k_ra8_drw_off_control     = 0x000U, 
  k_ra8_drw_off_status      = 0x000U, 
  k_ra8_drw_off_control2    = 0x004U, 
  k_ra8_drw_off_hwrevision  = 0x004U, 
  k_ra8_drw_off_l1start     = 0x010U, 
  k_ra8_drw_off_l2start     = 0x014U, 
  k_ra8_drw_off_l3start     = 0x018U, 
  k_ra8_drw_off_l4start     = 0x01CU, 
  k_ra8_drw_off_l5start     = 0x020U, 
  k_ra8_drw_off_l6start     = 0x024U, 
  k_ra8_drw_off_l1xadd      = 0x028U, 
  k_ra8_drw_off_l2xadd      = 0x02CU, 
  k_ra8_drw_off_l3xadd      = 0x030U, 
  k_ra8_drw_off_l4xadd      = 0x034U, 
  k_ra8_drw_off_l5xadd      = 0x038U, 
  k_ra8_drw_off_l6xadd      = 0x03CU, 
  k_ra8_drw_off_l1yadd      = 0x040U, 
  k_ra8_drw_off_l2yadd      = 0x044U, 
  k_ra8_drw_off_l3yadd      = 0x048U, 
  k_ra8_drw_off_l4yadd      = 0x04CU, 
  k_ra8_drw_off_l5yadd      = 0x050U, 
  k_ra8_drw_off_l6yadd      = 0x054U, 
  k_ra8_drw_off_l1band      = 0x058U, 
  k_ra8_drw_off_l2band      = 0x05CU, 
  k_ra8_drw_off_color1      = 0x064U, 
  k_ra8_drw_off_color2      = 0x068U, 
  k_ra8_drw_off_pattern     = 0x074U, 
  k_ra8_drw_off_size        = 0x078U, 
  k_ra8_drw_off_pitch       = 0x07CU, 
  k_ra8_drw_off_origin      = 0x080U, 
  k_ra8_drw_off_lustart     = 0x090U, 
  k_ra8_drw_off_luxadd      = 0x094U, 
  k_ra8_drw_off_luyadd      = 0x098U, 
  k_ra8_drw_off_lvstarti    = 0x09CU, 
  k_ra8_drw_off_lvstartf    = 0x0A0U, 
  k_ra8_drw_off_lvxaddi     = 0x0A4U, 
  k_ra8_drw_off_lvyaddi     = 0x0A8U, 
  k_ra8_drw_off_lvyxaddf    = 0x0ACU, 
  k_ra8_drw_off_texpitch    = 0x0B4U, 
  k_ra8_drw_off_texmask     = 0x0B8U, 
  k_ra8_drw_off_texorigin   = 0x0BCU, 
  k_ra8_drw_off_irqctl      = 0x0C0U, 
  k_ra8_drw_off_cachectl    = 0x0C4U, 
  k_ra8_drw_off_dliststart  = 0x0C8U, 
  k_ra8_drw_off_perfcount1  = 0x0CCU, 
  k_ra8_drw_off_perfcount2  = 0x0D0U, 
  k_ra8_drw_off_perftrigger = 0x0D4U, 
  k_ra8_drw_off_texcladdr   = 0x0DCU, 
  k_ra8_drw_off_texcldata   = 0x0E0U, 
  k_ra8_drw_off_texcloffset = 0x0E4U, 
  k_ra8_drw_off_colkey      = 0x0E8U, 
  k_ra8_drw_off_dbwer       = 0x100U, 
} ra8_drw_off_t;

typedef enum : uint16_t {
  k_ra8_drw_block_bytes = 0x104U, 
} ra8_drw_blocksize_t;
 
/* =============================================================================
 * STATUS register (R only, alias of CONTROL @ +0x00)
 *
 * HUM Ch 62.2.5 "STATUS : Status Control Register" p 3695.
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_drw_status_busyenum     = (1UL << 0U),  
  k_ra8_drw_status_busywrite    = (1UL << 1U),  
  k_ra8_drw_status_cachedirty   = (1UL << 2U),  
  k_ra8_drw_status_dlistactive  = (1UL << 3U),  
  k_ra8_drw_status_enumirq      = (1UL << 4U),  
  k_ra8_drw_status_dlistirq     = (1UL << 5U),  
  k_ra8_drw_status_busirq       = (1UL << 6U),  
  k_ra8_drw_status_buserrmfb    = (1UL << 8U),  
  k_ra8_drw_status_buserrmtxmrl = (1UL << 9U),  
  k_ra8_drw_status_buserrmdl    = (1UL << 10U), 
  k_ra8_drw_status_busy_mask    = (k_ra8_drw_status_busyenum | k_ra8_drw_status_busywrite |
                                   k_ra8_drw_status_dlistactive), 
  k_ra8_drw_status_irq_mask     = (k_ra8_drw_status_enumirq | k_ra8_drw_status_dlistirq |
                                   k_ra8_drw_status_busirq), 
  k_ra8_drw_status_buserr_mask  = (k_ra8_drw_status_buserrmfb | k_ra8_drw_status_buserrmtxmrl |
                                   k_ra8_drw_status_buserrmdl), 
} ra8_drw_status_mask_t;
 
/* =============================================================================
 * IRQCTL register (W only)
 *
 * HUM Ch 62.2.3 "IRQCTL : Interrupt Control Register" p 3693.
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_drw_irqctl_enumirqen   = (1UL << 0U), 
  k_ra8_drw_irqctl_dlistirqen  = (1UL << 1U), 
  k_ra8_drw_irqctl_enumirqclr  = (1UL << 2U), 
  k_ra8_drw_irqctl_dlistirqclr = (1UL << 3U), 
  k_ra8_drw_irqctl_busirqen    = (1UL << 4U), 
  k_ra8_drw_irqctl_busirqclr   = (1UL << 5U), 
  k_ra8_drw_irqctl_all_clr     = (k_ra8_drw_irqctl_enumirqclr | k_ra8_drw_irqctl_dlistirqclr |
                                  k_ra8_drw_irqctl_busirqclr), 
  k_ra8_drw_irqctl_all_en      = (k_ra8_drw_irqctl_enumirqen | k_ra8_drw_irqctl_dlistirqen |
                                  k_ra8_drw_irqctl_busirqen), 
} ra8_drw_irqctl_mask_t;
 
/* =============================================================================
 * CACHECTL register (W only)
 *
 * HUM Ch 62.2.4 "CACHECTL : Cache Control Register" p 3694.
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_drw_cachectl_cenablefx = (1UL << 0U), 
  k_ra8_drw_cachectl_cflushfx  = (1UL << 1U), 
  k_ra8_drw_cachectl_cenabletx = (1UL << 2U), 
  k_ra8_drw_cachectl_cflushtx  = (1UL << 3U), 
  k_ra8_drw_cachectl_all_en =
    (k_ra8_drw_cachectl_cenablefx | k_ra8_drw_cachectl_cenabletx), 
  k_ra8_drw_cachectl_all_flush =
    (k_ra8_drw_cachectl_cflushfx | k_ra8_drw_cachectl_cflushtx), 
} ra8_drw_cachectl_mask_t;
 
/* =============================================================================
 * CONTROL2 (Surface Control) register
 *
 * HUM Ch 62.2.2 p 3690-3693.
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_drw_control2_patternenable    = (1UL << 0U),  
  k_ra8_drw_control2_textureenable    = (1UL << 1U),  
  k_ra8_drw_control2_patternsourcel5  = (1UL << 2U),  
  k_ra8_drw_control2_useacb           = (1UL << 3U),  
  k_ra8_drw_control2_readformath_pos  = 4U,           
  k_ra8_drw_control2_readformath_mask = (3UL << 4U),  
  k_ra8_drw_control2_bsfa             = (1UL << 6U),  
  k_ra8_drw_control2_bdfa             = (1UL << 7U),  
  k_ra8_drw_control2_writeformat2_bit = (1UL << 8U),  
  k_ra8_drw_control2_bsf              = (1UL << 9U),  
  k_ra8_drw_control2_bdf              = (1UL << 10U), 
  k_ra8_drw_control2_bsi              = (1UL << 11U), 
  k_ra8_drw_control2_bdi              = (1UL << 12U), 
  k_ra8_drw_control2_bc2              = (1UL << 13U), 
  k_ra8_drw_control2_textureclampx    = (1UL << 14U), 
  k_ra8_drw_control2_textureclampy    = (1UL << 15U), 
  k_ra8_drw_control2_texturefilterx   = (1UL << 16U), 
  k_ra8_drw_control2_texturefiltery   = (1UL << 17U), 
  k_ra8_drw_control2_readformatl_pos  = 18U,          
  k_ra8_drw_control2_readformatl_mask = (3UL << 18U), 
  k_ra8_drw_control2_writeformat_pos  = 20U,          
  k_ra8_drw_control2_writeformat_mask = (3UL << 20U), 
  k_ra8_drw_control2_writealpha_pos   = 22U,          
  k_ra8_drw_control2_writealpha_mask  = (3UL << 22U), 
  k_ra8_drw_control2_rleenable        = (1UL << 24U), 
  k_ra8_drw_control2_clutenable       = (1UL << 25U), 
  k_ra8_drw_control2_colkeyenable     = (1UL << 26U), 
  k_ra8_drw_control2_clutformat_565   = (1UL << 27U), 
  k_ra8_drw_control2_bsia             = (1UL << 28U), 
  k_ra8_drw_control2_bdia             = (1UL << 29U), 
  k_ra8_drw_control2_rlepixel_pos     = 30U,          
  k_ra8_drw_control2_rlepixel_mask    = (3UL << 30U), 
} ra8_drw_control2_mask_t;
 
/* =============================================================================
 * CONTROL (Geometry Control) register
 *
 * HUM Ch 62.2.1 p 3689-3690.
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_drw_control_lim1en        = (1UL << 0U),  
  k_ra8_drw_control_lim2en        = (1UL << 1U),  
  k_ra8_drw_control_lim3en        = (1UL << 2U),  
  k_ra8_drw_control_lim4en        = (1UL << 3U),  
  k_ra8_drw_control_lim5en        = (1UL << 4U),  
  k_ra8_drw_control_lim6en        = (1UL << 5U),  
  k_ra8_drw_control_quad1en       = (1UL << 6U),  
  k_ra8_drw_control_quad2en       = (1UL << 7U),  
  k_ra8_drw_control_quad3en       = (1UL << 8U),  
  k_ra8_drw_control_lim1threshold = (1UL << 9U),  
  k_ra8_drw_control_lim2threshold = (1UL << 10U), 
  k_ra8_drw_control_lim3threshold = (1UL << 11U), 
  k_ra8_drw_control_lim4threshold = (1UL << 12U), 
  k_ra8_drw_control_lim5threshold = (1UL << 13U), 
  k_ra8_drw_control_lim6threshold = (1UL << 14U), 
  k_ra8_drw_control_band1en       = (1UL << 15U), 
  k_ra8_drw_control_band2en       = (1UL << 16U), 
  k_ra8_drw_control_union12       = (1UL << 17U), 
  k_ra8_drw_control_union34       = (1UL << 18U), 
  k_ra8_drw_control_union56       = (1UL << 19U), 
  k_ra8_drw_control_unionab       = (1UL << 20U), 
  k_ra8_drw_control_unioncd       = (1UL << 21U), 
  k_ra8_drw_control_spanabort     = (1UL << 22U), 
  k_ra8_drw_control_spanstore     = (1UL << 23U), 
  k_ra8_drw_control_quad_box =
    (k_ra8_drw_control_lim1en | k_ra8_drw_control_lim2en | k_ra8_drw_control_lim3en |
     k_ra8_drw_control_lim4en), 
  k_ra8_drw_control_triangle = (k_ra8_drw_control_lim1en | k_ra8_drw_control_lim2en |
                                k_ra8_drw_control_lim3en), 
  k_ra8_drw_control_line_quad =
    (k_ra8_drw_control_lim1en | k_ra8_drw_control_lim2en | k_ra8_drw_control_lim3en |
     k_ra8_drw_control_lim4en | k_ra8_drw_control_union12), 
} ra8_drw_control_mask_t;
 
/* =============================================================================
 * HWREVISION (R only, alias of CONTROL2)
 *
 * HUM Ch 62.2.6 p 3696.
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_drw_hwrev_rev_mask    = 0x00000FFFUL, 
  k_ra8_drw_hwrev_dlr         = (1UL << 17U), 
  k_ra8_drw_hwrev_fbcache     = (1UL << 18U), 
  k_ra8_drw_hwrev_txcache     = (1UL << 19U), 
  k_ra8_drw_hwrev_perfcount   = (1UL << 20U), 
  k_ra8_drw_hwrev_texclut     = (1UL << 21U), 
  k_ra8_drw_hwrev_rleunit     = (1UL << 23U), 
  k_ra8_drw_hwrev_texclut256  = (1UL << 24U), 
  k_ra8_drw_hwrev_colorkey    = (1UL << 25U), 
  k_ra8_drw_hwrev_acblend     = (1UL << 27U), 
  k_ra8_drw_hwrev_reset_value = 0x1FBE0017UL, 
} ra8_drw_hwrev_mask_t;
 
/* =============================================================================
 * Pixel formats
 *
 * HUM Ch 62.2.2 p 3692 (WRITEFORMAT[2:0] table) and Ch 62.3.1.1 p 3707.
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_drw_writefmt_a8       = 0U, 
  k_ra8_drw_writefmt_rgb565   = 1U, 
  k_ra8_drw_writefmt_argb8888 = 2U, 
  k_ra8_drw_writefmt_argb4444 = 3U, 
} ra8_drw_writeformat_t;

typedef enum : uint8_t {
  k_ra8_drw_readfmt_a8       = 0x0U, 
  k_ra8_drw_readfmt_rgb565   = 0x1U, 
  k_ra8_drw_readfmt_argb8888 = 0x2U, 
  k_ra8_drw_readfmt_argb4444 = 0x3U, 
  k_ra8_drw_readfmt_argb1555 = 0x4U, 
  k_ra8_drw_readfmt_aclut44  = 0x5U, 
  k_ra8_drw_readfmt_clut8    = 0x9U, 
  k_ra8_drw_readfmt_clut4    = 0xAU, 
  k_ra8_drw_readfmt_clut2    = 0xBU, 
  k_ra8_drw_readfmt_clut1    = 0xCU, 
} ra8_drw_readformat_t;

typedef enum : uint8_t {
  k_ra8_drw_writealpha_color2    = 0U, 
  k_ra8_drw_writealpha_pixel_cov = 1U, 
  k_ra8_drw_writealpha_zero      = 2U, 
  k_ra8_drw_writealpha_fb        = 3U, 
} ra8_drw_writealpha_t;

typedef enum : uint8_t {
  k_ra8_drw_rle_1byte = 0U, 
  k_ra8_drw_rle_2byte = 1U, 
  k_ra8_drw_rle_3byte = 2U, 
  k_ra8_drw_rle_4byte = 3U, 
} ra8_drw_rlepixel_t;
 
/* =============================================================================
 * Performance counters
 *
 * HUM Ch 62.2.33 p 3706.
 * =============================================================================
 */

typedef enum : uint16_t {
  k_ra8_drw_perfev_disabled       = 0x0000U, 
  k_ra8_drw_perfev_active_cycles  = 0x0001U, 
  k_ra8_drw_perfev_fb_read        = 0x0002U, 
  k_ra8_drw_perfev_fb_write       = 0x0003U, 
  k_ra8_drw_perfev_tex_read       = 0x0004U, 
  k_ra8_drw_perfev_invisible      = 0x0005U, 
  k_ra8_drw_perfev_invisible_idle = 0x0006U, 
  k_ra8_drw_perfev_dlist_active   = 0x0007U, 
  k_ra8_drw_perfev_fb_read_hit    = 0x0008U, 
  k_ra8_drw_perfev_fb_read_miss   = 0x0009U, 
  k_ra8_drw_perfev_fb_write_hit   = 0x000AU, 
  k_ra8_drw_perfev_fb_write_miss  = 0x000BU, 
  k_ra8_drw_perfev_tex_read_hit   = 0x000CU, 
  k_ra8_drw_perfev_tex_read_miss  = 0x000DU, 
  k_ra8_drw_perfev_every_cycle    = 0x001FU, 
} ra8_drw_perftrigger_t;

typedef enum : uint8_t {
  k_ra8_drw_perfctr_1 = 0U, 
  k_ra8_drw_perfctr_2 = 1U, 
} ra8_drw_perfcounter_id_t;
 
/* =============================================================================
 * Display list encoding
 *
 * A display list is a stream of 32-bit words the DRW's display-list reader
 * (DLR) fetches from RAM after DLISTSTART is written (HUM Ch 62.6 "Display
 * List Mode" p 3724). The HUM documents the concept but not the word layout;
 * the layout below is the one the DLR consumes, decoded from the vendored TES
 * D/AVE 2D reference (its software DLR model d2_executedlist_intern and
 * register map: register index == byte offset / 4) and bench-verified on an
 * EK-RA8D2 (issue #247).
 *
 * Each entry is a TAG word followed by one value word per register it writes.
 * The tag packs up to four register indices, one per byte. The first byte
 * position >= 1 whose bit 7 is set marks the entry's boundary: byte 1 -> one
 * register, byte 2 -> two, byte 3 -> three, none set -> four. A word whose low
 * byte is 0xFF is an end-of-list marker with an argument in byte 1 (2 = wait
 * for the pipeline and cache then continue; 3 = terminate).
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_drw_dlr_idx_control  = 0U,  
  k_ra8_drw_dlr_idx_control2 = 1U,  
  k_ra8_drw_dlr_idx_color1   = 25U, 
  k_ra8_drw_dlr_idx_color2   = 26U, 
  k_ra8_drw_dlr_idx_size     = 30U, 
  k_ra8_drw_dlr_idx_pitch    = 31U, 
  k_ra8_drw_dlr_idx_origin   = 32U, 
  k_ra8_drw_dlr_idx_cachectl = 49U, 
} ra8_drw_dlr_index_t;

typedef enum : uint32_t {
  k_ra8_drw_dlr_tag_one_index = 0x80808000UL, 
  k_ra8_drw_dlr_eol_byte      = 0x000000FFUL, 
  k_ra8_drw_dlr_eol_arg_pos   = 8UL,          
  k_ra8_drw_dlr_arg_wait      = 2UL,          
  k_ra8_drw_dlr_arg_terminate = 3UL,          
} ra8_drw_dlr_word_t;
 
/* =============================================================================
 * SIZE / PITCH / DBWER misc bit fields
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_drw_size_height_pos      = 16U, 
  k_ra8_drw_pitch_ssd_pos        = 16U, 
  k_ra8_drw_perftrigger2_pos     = 16U, 
  k_ra8_drw_color_b_pos          = 0U,  
  k_ra8_drw_color_g_pos          = 8U,  
  k_ra8_drw_color_r_pos          = 16U, 
  k_ra8_drw_color_a_pos          = 24U, 
  k_ra8_drw_lvyxaddf_lvyaddf_pos = 16U, 
} ra8_drw_geom_layout_t;

typedef enum : uint16_t {
  k_ra8_drw_max_width_px     = 1024U, 
  k_ra8_drw_max_height_px    = 1024U, 
  k_ra8_drw_max_texpitch_tx  = 2048U, 
  k_ra8_drw_max_texumask     = 2048U, 
  k_ra8_drw_max_texvmask     = 1024U, 
  k_ra8_drw_clut_entries_max = 256U,  
  k_ra8_drw_min_dim_px       = 1U,    
} ra8_drw_dim_limits_t;

typedef enum : uint8_t {
  k_ra8_drw_bytes_px_8bpp  = 1U, 
  k_ra8_drw_bytes_px_16bpp = 2U, 
  k_ra8_drw_bytes_px_32bpp = 4U, 
} ra8_drw_pixel_stride_t;

typedef enum : uint32_t {
  k_ra8_drw_dbwer_bwe = (1UL << 2U), 
} ra8_drw_dbwer_mask_t;

typedef enum : uint8_t {
  k_ra8_drw_subpixel_shift = 4U,  
  k_ra8_drw_subpixel_unit  = 16U, 
} ra8_drw_subpixel_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_drw_reg32(ra8_drw_off_t off)
{
  return (volatile uint32_t*)(k_ra8_drw_base_addr + (uintptr_t)(uint16_t)off);
}
 
#ifdef __cplusplus
}
#endif