ra8_drw_draw.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_drw.h"
#include "ra8_drw_dlist.h"
#include "ra8_drw_internal.h"
#include "ra8_drw_regs.h"
#include "ra8_err.h"
 
/* =============================================================================
 * Driver-private state
 * =============================================================================
 */

static const char* s_tag = "DRW";
 
/* =============================================================================
 * Drawing primitives
 * =============================================================================
 */
 
[[nodiscard]] ra8_err_t ra8_drw_fill_rect(const ra8_drw_rect_t* rect)
{
  RA8_CHECK_NULL_PTR(rect, s_tag, "rect must not be nullptr");
  if ((uint16_t)rect->width_px < k_ra8_drw_min_dim_px ||
      (uint16_t)rect->height_px < k_ra8_drw_min_dim_px) {
    return k_ra8_err_invalid_arg;
  }
  if ((uint16_t)rect->width_px > k_ra8_drw_max_width_px ||
      (uint16_t)rect->height_px > k_ra8_drw_max_height_px) {
    return k_ra8_err_invalid_arg;
  }
  if (priv_ra8_drw_internal_rect_off_surface(rect)) {
    return k_ra8_err_invalid_arg;
  }
 
  /* COLOR1 goes through the shadowed writer (write-only register). */
  priv_ra8_drw_internal_color1_write(rect->color_argb8888);
 
  priv_program_rect_bbox(rect);
 
  /* HUM Ch 62.2.1 "CONTROL: Geometry Control Register", p 3689 */
  /* No spatial limiter: the bounding box scan (HUM Ch 62.6.2 p 3716) already
   * covers exactly the rectangle, so every enable bit stays clear. Driving
   * the quad-box limiters here is what produced the half-sized rect on
   * silicon -- the limiters were fed absolute pixel coordinates while the
   * hardware wants the decision value at the bounding box's top-left corner,
   * and their coverage output then landed as alpha 0x01 rather than 0xFF. */
  *ra8_drw_reg32(k_ra8_drw_off_control) = 0UL;
 
  /* HUM Ch 62.2.31 "ORIGIN: Framebuffer Base Address Register", p 3705 */
  /* ORIGIN both POSITIONS the bounding box and TRIGGERS the render, so it is
   * written last and points at the rectangle's own top-left pixel rather
   * than the framebuffer base. Without the trigger the engine never
   * rasterizes (silicon-verified: the demo framebuffer stayed zero-filled). */
  *ra8_drw_reg32(k_ra8_drw_off_origin) = priv_ra8_drw_internal_rect_origin(rect);
 
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_drw_blit_textured_rect(const ra8_drw_rect_t* rect)
{
  RA8_CHECK_NULL_PTR(rect, s_tag, "rect must not be nullptr");
  if (priv_ra8_drw_internal_rect_below_min((uint16_t)k_ra8_drw_min_dim_px,
                                           (uint16_t)rect->width_px,
                                           (uint16_t)rect->height_px)) {
    return k_ra8_err_invalid_arg;
  }
  if (priv_ra8_drw_internal_rect_above_max((uint16_t)k_ra8_drw_max_width_px,
                                           (uint16_t)k_ra8_drw_max_height_px,
                                           (uint16_t)rect->width_px,
                                           (uint16_t)rect->height_px)) {
    return k_ra8_err_invalid_arg;
  }
  if (priv_ra8_drw_internal_rect_off_surface(rect)) {
    return k_ra8_err_invalid_arg;
  }
 
  priv_program_rect_bbox(rect);
 
  /* HUM Ch 62.2.18 "LUSTART: U Limiter Start Value Register" p 3701 */
  *ra8_drw_reg32(k_ra8_drw_off_lustart) = 0UL;
  /* HUM Ch 62.2.18 "LUSTART: U Limiter Start Value Register" p 3701 */
  *ra8_drw_reg32(k_ra8_drw_off_luxadd) = (uint32_t)k_ra8_drw_subpixel_unit;
  /* HUM Ch 62.2.18 "LUSTART: U Limiter Start Value Register" p 3701 */
  *ra8_drw_reg32(k_ra8_drw_off_luyadd) = 0UL;
 
  /* HUM Ch 62.2.20 "LVSTARTI: V Limiter Start Integer Part", p 3702 */
  *ra8_drw_reg32(k_ra8_drw_off_lvstarti) = 0UL;
  /* HUM Ch 62.2.21 "LVSTARTF: V Limiter Start Fractional Part", p 3702 */
  *ra8_drw_reg32(k_ra8_drw_off_lvstartf) = 0UL;
  /* HUM Ch 62.2.22 "LVXADDI: V Limiter X-Axis Increment Integer", p 3702 */
  *ra8_drw_reg32(k_ra8_drw_off_lvxaddi) = 0UL;
  /* HUM Ch 62.2.23 "LVYADDI: V Limiter Y-Axis Increment Integer", p 3702 */
  *ra8_drw_reg32(k_ra8_drw_off_lvyaddi) = (uint32_t)k_ra8_drw_subpixel_unit;
  /* HUM Ch 62.2.24 "LVYXADDF: V Limiter Increment Fractional", p 3703 */
  *ra8_drw_reg32(k_ra8_drw_off_lvyxaddf) = 0UL;
 
  /* HUM Ch 62.2.4 "CACHECTL: Cache Control Register", p 3694 */
  /* Pulse the texture cache flush so this blit cannot consume texels a
 * previous primitive left cached. The framebuffer cache is left exactly as
 * ::ra8_drw_init configured it -- a primitive must not silently switch on a
 * cache the caller asked to keep off, because the rendered pixels then sit
 * in the DRW cache instead of memory until something flushes them. */
  *ra8_drw_reg32(k_ra8_drw_off_cachectl) = k_ra8_drw_cachectl_cflushtx;
 
  /* HUM Ch 62.2.1 "CONTROL: Geometry Control Register", p 3689 */
  /* No spatial limiter -- the bounding box scan is the rectangle. */
  *ra8_drw_reg32(k_ra8_drw_off_control) = 0UL;
 
  /* HUM Ch 62.2.31 "ORIGIN: Framebuffer Base Address Register", p 3705 */
  /* ORIGIN positions the bounding box AND triggers the render. */
  *ra8_drw_reg32(k_ra8_drw_off_origin) = priv_ra8_drw_internal_rect_origin(rect);
  return k_ra8_ok;
}

RA8_INTERNAL
static void internal_program_line_limiters(const ra8_drw_line_t* line)
{
  const int32_t dx  = line->x1 - line->x0;
  const int32_t dy  = line->y1 - line->y0;
  const int32_t adx = internal_iabs(dx);
  const int32_t ady = internal_iabs(dy);
 
  /* HUM Ch 62.2.10 "LnSTART: Limiter n Start Value Register", p 3698 */
  *ra8_drw_reg32(k_ra8_drw_off_l1start) = internal_to_subpixel(line->x0);
  *ra8_drw_reg32(k_ra8_drw_off_l2start) = internal_to_subpixel(line->x0);
  *ra8_drw_reg32(k_ra8_drw_off_l3start) = internal_to_subpixel(line->y0);
  *ra8_drw_reg32(k_ra8_drw_off_l4start) = internal_to_subpixel(line->y0);
 
  /* HUM Ch 62.2.11 "LnXADD: Limiter n X-Axis Increment Register", p 3698 */
  *ra8_drw_reg32(k_ra8_drw_off_l1xadd) = internal_to_subpixel(adx);
  *ra8_drw_reg32(k_ra8_drw_off_l2xadd) = internal_to_subpixel(-adx);
  *ra8_drw_reg32(k_ra8_drw_off_l3xadd) = internal_to_subpixel(ady);
  *ra8_drw_reg32(k_ra8_drw_off_l4xadd) = internal_to_subpixel(-ady);
 
  /* HUM Ch 62.2.12 "LnYADD: Limiter n Y-Axis Increment Register", p 3699 */
  *ra8_drw_reg32(k_ra8_drw_off_l1yadd) = internal_to_subpixel(ady);
  *ra8_drw_reg32(k_ra8_drw_off_l2yadd) = internal_to_subpixel(-ady);
  *ra8_drw_reg32(k_ra8_drw_off_l3yadd) = internal_to_subpixel(adx);
  *ra8_drw_reg32(k_ra8_drw_off_l4yadd) = internal_to_subpixel(-adx);
 
  /* HUM Ch 62.2.13 "L1BAND/L2BAND: Limiter Band Width Register", p 3699.
   * Band width = stroke width in sub-pixels for L1 and L2. */
  const uint32_t band = (uint32_t)line->width_px * (uint32_t)k_ra8_drw_subpixel_unit;
  *ra8_drw_reg32(k_ra8_drw_off_l1band) = band;
  *ra8_drw_reg32(k_ra8_drw_off_l2band) = band;
}
 
[[nodiscard]] ra8_err_t ra8_drw_draw_line(const ra8_drw_line_t* line)
{
  RA8_CHECK_NULL_PTR(line, s_tag, "line must not be nullptr");
  if (line->width_px == 0U || (uint16_t)line->width_px > k_ra8_drw_max_width_px) {
    return k_ra8_err_invalid_arg;
  }
 
  /* COLOR1 goes through the shadowed writer (write-only register). */
  priv_ra8_drw_internal_color1_write(line->color_argb8888);
 
  /* Compute the bounding box of the stroke for SIZE: a simple
   * over-estimate using axis-aligned span + width. The DRW only uses
   * SIZE as an enumeration upper bound, not for clipping the stroke
   * itself. HUM Ch 62.2.29 p 3704. */
  const int32_t  min_x  = (line->x0 < line->x1) ? line->x0 : line->x1;
  const int32_t  max_x  = (line->x0 > line->x1) ? line->x0 : line->x1;
  const int32_t  min_y  = (line->y0 < line->y1) ? line->y0 : line->y1;
  const int32_t  max_y  = (line->y0 > line->y1) ? line->y0 : line->y1;
  const uint32_t span_x = (uint32_t)(max_x - min_x) + (uint32_t)line->width_px;
  const uint32_t span_y = (uint32_t)(max_y - min_y) + (uint32_t)line->width_px;
 
  /* HUM Ch 62.2.29 "SIZE: Bounding Box Dimension Register", p 3704 */
  *ra8_drw_reg32(k_ra8_drw_off_size) = (span_y << k_ra8_drw_size_height_pos) | span_x;
 
  internal_program_line_limiters(line);
 
  /* HUM Ch 62.2.4 "CACHECTL: Cache Control Register", p 3694 */
  *ra8_drw_reg32(k_ra8_drw_off_cachectl) =
    (k_ra8_drw_cachectl_all_en | k_ra8_drw_cachectl_cflushfx);
 
  /* HUM Ch 62.2.1 "CONTROL: Geometry Control Register", p 3689 */
  *ra8_drw_reg32(k_ra8_drw_off_control) = k_ra8_drw_control_line_quad;
 
  /* HUM Ch 62.2.31 "ORIGIN: Framebuffer Base Address Register", p 3705 */
  /* ORIGIN write = render trigger (see ra8_drw_fill_rect). */
  *ra8_drw_reg32(k_ra8_drw_off_origin) = priv_ra8_drw_internal_origin();
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_drw_draw_triangle(const ra8_drw_triangle_t* tri)
{
  RA8_CHECK_NULL_PTR(tri, s_tag, "tri must not be nullptr");
 
  /* COLOR1 goes through the shadowed writer (write-only register). */
  priv_ra8_drw_internal_color1_write(tri->color_argb8888);
 
  /* Bounding box for SIZE -- HUM Ch 62.2.29 p 3704. */
  int32_t min_x = (tri->x0 < tri->x1) ? tri->x0 : tri->x1;
  if (tri->x2 < (int16_t)min_x) {
    min_x = tri->x2;
  }
  int32_t max_x = (tri->x0 > tri->x1) ? tri->x0 : tri->x1;
  if (tri->x2 > (int16_t)max_x) {
    max_x = tri->x2;
  }
  int32_t min_y = (tri->y0 < tri->y1) ? tri->y0 : tri->y1;
  if (tri->y2 < (int16_t)min_y) {
    min_y = tri->y2;
  }
  int32_t max_y = (tri->y0 > tri->y1) ? tri->y0 : tri->y1;
  if (tri->y2 > (int16_t)max_y) {
    max_y = tri->y2;
  }
  const uint32_t span_x = (uint32_t)(max_x - min_x);
  const uint32_t span_y = (uint32_t)(max_y - min_y);
 
  *ra8_drw_reg32(k_ra8_drw_off_size) = (span_y << k_ra8_drw_size_height_pos) | span_x;
 
  /* HUM Ch 62.4.5 "Triangles" p 3726: three half-plane limiters,
 * one per edge. The HAL programmes the simplest "axis-aligned
 * triangle" encoding -- the application can override LnSTART /
 * LnXADD / LnYADD via display lists for arbitrary geometry. */
 
  /* HUM Ch 62.2.10 "LnSTART: Limiter n Start Value Register", p 3698 */
  *ra8_drw_reg32(k_ra8_drw_off_l1start) = internal_to_subpixel(tri->x0);
  *ra8_drw_reg32(k_ra8_drw_off_l2start) = internal_to_subpixel(tri->x1);
  *ra8_drw_reg32(k_ra8_drw_off_l3start) = internal_to_subpixel(tri->x2);
 
  /* HUM Ch 62.2.11 "LnXADD: Limiter n X-Axis Increment", p 3698 */
  *ra8_drw_reg32(k_ra8_drw_off_l1xadd) = internal_to_subpixel((int32_t)tri->y1 - (int32_t)tri->y0);
  *ra8_drw_reg32(k_ra8_drw_off_l2xadd) = internal_to_subpixel((int32_t)tri->y2 - (int32_t)tri->y1);
  *ra8_drw_reg32(k_ra8_drw_off_l3xadd) = internal_to_subpixel((int32_t)tri->y0 - (int32_t)tri->y2);
 
  /* HUM Ch 62.2.12 "LnYADD: Limiter n Y-Axis Increment", p 3699 */
  *ra8_drw_reg32(k_ra8_drw_off_l1yadd) = internal_to_subpixel((int32_t)tri->x0 - (int32_t)tri->x1);
  *ra8_drw_reg32(k_ra8_drw_off_l2yadd) = internal_to_subpixel((int32_t)tri->x1 - (int32_t)tri->x2);
  *ra8_drw_reg32(k_ra8_drw_off_l3yadd) = internal_to_subpixel((int32_t)tri->x2 - (int32_t)tri->x0);
 
  /* HUM Ch 62.2.4 "CACHECTL: Cache Control Register", p 3694 */
  *ra8_drw_reg32(k_ra8_drw_off_cachectl) =
    (k_ra8_drw_cachectl_all_en | k_ra8_drw_cachectl_cflushfx);
 
  /* HUM Ch 62.2.1 "CONTROL: Geometry Control Register", p 3689 */
  *ra8_drw_reg32(k_ra8_drw_off_control) = k_ra8_drw_control_triangle;
 
  /* HUM Ch 62.2.31 "ORIGIN: Framebuffer Base Address Register", p 3705 */
  /* ORIGIN write = render trigger (see ra8_drw_fill_rect). */
  *ra8_drw_reg32(k_ra8_drw_off_origin) = priv_ra8_drw_internal_origin();
  return k_ra8_ok;
}
 
/* =============================================================================
 * Display list mode
 * =============================================================================
 */
 
[[nodiscard]] ra8_err_t ra8_drw_run_dlist(const uint32_t* dlist_addr)
{
  if (dlist_addr == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (((uintptr_t)dlist_addr & (uintptr_t)k_ra8_drw_internal_align_mask) != 0U) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 62.2.4 "CACHECTL: Cache Control Register", p 3694 */
  /* Flush both caches so the dlist words written by the CPU are
 * visible to the DRW bus initiator. */
  const uint32_t cur_cc                  = *ra8_drw_reg32(k_ra8_drw_off_cachectl);
  *ra8_drw_reg32(k_ra8_drw_off_cachectl) = cur_cc | k_ra8_drw_cachectl_all_flush;
 
  /* HUM Ch 62.2.32 "DLISTSTART: Display List Start Address Register",
 * p 3705. Writing a new value triggers execution. */
  *ra8_drw_reg32(k_ra8_drw_off_dliststart) = (uint32_t)(uintptr_t)dlist_addr;
  return k_ra8_ok;
}

typedef enum : uint8_t {
  k_ra8_drw_dlist_entry_words   = 2U, 
  k_ra8_drw_dlist_special_words = 1U, 
  k_ra8_drw_dlist_fill_regs     = 4U, 
  k_ra8_drw_dlist_fill_words    = 9U, 
} ra8_drw_dlist_span_t;

RA8_INTERNAL
static void internal_dlist_put_reg(ra8_drw_dlist_t* dl, ra8_drw_dlr_index_t idx, uint32_t val)
{
  dl->buf[dl->count]      = (uint32_t)k_ra8_drw_dlr_tag_one_index | (uint32_t)idx;
  dl->buf[dl->count + 1U] = val;
  dl->count += (uint32_t)k_ra8_drw_dlist_entry_words;
}

RA8_INTERNAL
static void internal_dlist_put_special(ra8_drw_dlist_t* dl, uint32_t arg)
{
  dl->buf[dl->count] =
    (uint32_t)k_ra8_drw_dlr_eol_byte | (arg << (uint32_t)k_ra8_drw_dlr_eol_arg_pos);
  dl->count += (uint32_t)k_ra8_drw_dlist_special_words;
}
 
[[nodiscard]] ra8_err_t ra8_drw_dlist_begin(ra8_drw_dlist_t* dl, uint32_t* buf, uint32_t cap_words)
{
  RA8_CHECK_NULL_PTR(dl, s_tag, "dl must not be nullptr");
  RA8_CHECK_NULL_PTR(buf, s_tag, "buf must not be nullptr");
  if (((uintptr_t)buf & (uintptr_t)k_ra8_drw_internal_align_mask) != 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (cap_words == 0U) {
    return k_ra8_err_invalid_arg;
  }
  dl->buf        = buf;
  dl->cap_words  = cap_words;
  dl->count      = 0U;
  dl->overflow   = false;
  dl->terminated = false;
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_drw_dlist_add_fill(ra8_drw_dlist_t* dl, const ra8_drw_rect_t* rect)
{
  RA8_CHECK_NULL_PTR(dl, s_tag, "dl must not be nullptr");
  RA8_CHECK_NULL_PTR(rect, s_tag, "rect must not be nullptr");
  if (priv_ra8_drw_internal_rect_below_min((uint16_t)k_ra8_drw_min_dim_px,
                                           (uint16_t)rect->width_px,
                                           (uint16_t)rect->height_px)) {
    return k_ra8_err_invalid_arg;
  }
  if (priv_ra8_drw_internal_rect_above_max((uint16_t)k_ra8_drw_max_width_px,
                                           (uint16_t)k_ra8_drw_max_height_px,
                                           (uint16_t)rect->width_px,
                                           (uint16_t)rect->height_px)) {
    return k_ra8_err_invalid_arg;
  }
  if (priv_ra8_drw_internal_rect_off_surface(rect)) {
    return k_ra8_err_invalid_arg;
  }
  /* Reject up front so no partial primitive is left in the buffer. */
  if ((dl->count + (uint32_t)k_ra8_drw_dlist_fill_words) > dl->cap_words) {
    dl->overflow = true;
    return k_ra8_err_no_mem;
  }
 
  /* Same geometry as the register-mode ra8_drw_fill_rect: COLOR1 carries the
   * ARGB, SIZE the bounding box, CONTROL clears the spatial limiters so the
   * box scan is the rectangle, and ORIGIN (the render trigger) anchors it at
   * the rectangle's top-left pixel. CONTROL2 / PITCH / cache stay as
   * ra8_drw_init programmed them. */
  internal_dlist_put_reg(dl, k_ra8_drw_dlr_idx_color1, rect->color_argb8888);
  internal_dlist_put_reg(dl,
                         k_ra8_drw_dlr_idx_size,
                         ((uint32_t)rect->height_px << k_ra8_drw_size_height_pos) |
                           (uint32_t)rect->width_px);
  internal_dlist_put_reg(dl, k_ra8_drw_dlr_idx_control, 0UL);
  internal_dlist_put_reg(dl, k_ra8_drw_dlr_idx_origin, priv_ra8_drw_internal_rect_origin(rect));
  /* Wait for the pipeline and framebuffer cache to drain so this primitive
   * fully lands before the next one (or the CPU read) begins. */
  internal_dlist_put_special(dl, (uint32_t)k_ra8_drw_dlr_arg_wait);
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_drw_dlist_end(ra8_drw_dlist_t* dl)
{
  RA8_CHECK_NULL_PTR(dl, s_tag, "dl must not be nullptr");
  if (dl->overflow) {
    return k_ra8_err_invalid_arg;
  }
  if ((dl->count + (uint32_t)k_ra8_drw_dlist_special_words) > dl->cap_words) {
    dl->overflow = true;
    return k_ra8_err_no_mem;
  }
  internal_dlist_put_special(dl, (uint32_t)k_ra8_drw_dlr_arg_terminate);
  dl->terminated = true;
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_drw_dlist_run(const ra8_drw_dlist_t* dl)
{
  RA8_CHECK_NULL_PTR(dl, s_tag, "dl must not be nullptr");
  if (dl->overflow || !dl->terminated || (dl->count == 0U)) {
    return k_ra8_err_invalid_arg;
  }
  return ra8_drw_run_dlist(dl->buf);
}
 
/* =============================================================================
 * Performance counters
 * =============================================================================
 */
 
[[nodiscard]] ra8_err_t ra8_drw_perf_arm(ra8_drw_perftrigger_t event_ctr1,
                                         ra8_drw_perftrigger_t event_ctr2)
{
  if ((uint16_t)event_ctr1 > k_ra8_drw_internal_perfev_max ||
      (uint16_t)event_ctr2 > k_ra8_drw_internal_perfev_max) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 62.2.33 "PERFTRIGGER: Performance Counters Control Register",
 * p 3706. PERFTRIGGER1 in [15:0], PERFTRIGGER2 in [31:16]. */
  *ra8_drw_reg32(k_ra8_drw_off_perftrigger) =
    ((uint32_t)event_ctr2 << k_ra8_drw_perftrigger2_pos) | (uint32_t)event_ctr1;
 
  /* HUM Ch 62.2.34 "PERFCOUNTk: Performance Counter k", p 3706 */
  *ra8_drw_reg32(k_ra8_drw_off_perfcount1) = 0UL;
  *ra8_drw_reg32(k_ra8_drw_off_perfcount2) = 0UL;
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_drw_perf_read(ra8_drw_perfcounter_id_t id, uint32_t* out)
{
  RA8_CHECK_NULL_PTR(out, s_tag, "out must not be nullptr");
  ra8_err_t result = k_ra8_err_invalid_arg;
  /* HUM Ch 62.2.34 "PERFCOUNTk: Performance Counter k", p 3706 */
  if (id == k_ra8_drw_perfctr_1) {
    *out   = *ra8_drw_reg32(k_ra8_drw_off_perfcount1);
    result = k_ra8_ok;
  } else if (id == k_ra8_drw_perfctr_2) {
    *out   = *ra8_drw_reg32(k_ra8_drw_off_perfcount2);
    result = k_ra8_ok;
  } else {
    result = k_ra8_err_invalid_arg;
  }
  return result;
}
 
[[nodiscard]] ra8_err_t ra8_drw_perf_reset(ra8_drw_perfcounter_id_t id)
{
  ra8_err_t result = k_ra8_err_invalid_arg;
  /* HUM Ch 62.2.34 "PERFCOUNTk: Performance Counter k", p 3706 */
  if (id == k_ra8_drw_perfctr_1) {
    *ra8_drw_reg32(k_ra8_drw_off_perfcount1) = 0UL;
    result                                   = k_ra8_ok;
  } else if (id == k_ra8_drw_perfctr_2) {
    *ra8_drw_reg32(k_ra8_drw_off_perfcount2) = 0UL;
    result                                   = k_ra8_ok;
  } else {
    result = k_ra8_err_invalid_arg;
  }
  return result;
}