main.c

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#include <stddef.h>
#include <stdint.h>
#include <string.h>
 
#include "book.h"
#include "compile_on_m33.h"
#include "parity_fixture.h"
#include "ra8_attributes.h"
#include "ra8_boot_entry.h"
#include "ra8_dual_core.h"
#include "ra8_err.h"
#include "ra8_ipc.h"
#include "ra8_isr.h"
#include "ra8_log.h"

extern uint32_t g_ra8_ls_cpu1_mram_start;
extern uint32_t g_ra8_ls_cpu1_stack_top;

typedef enum : uint32_t {
  k_m85_sig_poll_budget  = 10000000UL, 
  k_m85_done_poll_budget = 50000000UL, 
} m85_poll_t;
 
static_assert((uint32_t)k_m33_parity_epub_len <= (uint32_t)k_com33_epub_cap,
              "staged parity .epub must fit the shared input buffer");

typedef enum : uint8_t {
  k_ipc_wake_channel = 0U, 
} m85_ipc_t;

static volatile bool s_m33_woke;

static void ipc_wake_handler(void* ctx, uint8_t channel, ra8_ipc_irq_event_id_t event_id)
{
  (void)ctx;
  (void)channel;
  (void)event_id;
  s_m33_woke = true;
}

static void ipc0_receive_isr(void* ctx)
{
  (void)ctx;
  ra8_ipc_dispatch((uint8_t)k_ipc_wake_channel);
}

static bool arm_ipc_wake(void)
{
  if (ra8_isr_init() != k_ra8_ok) {
    return false;
  }
  const ra8_ipc_config_t cfg = {
    .channel      = (uint8_t)k_ipc_wake_channel,
    .reset_fifo   = true,
    .clear_status = true,
    .event_mask   = (uint32_t)k_ra8_ipc_event_irq0,
  };
  if (ra8_ipc_init(&cfg) != k_ra8_ok) {
    return false;
  }
  if (ra8_ipc_attach_event_handler((uint8_t)k_ipc_wake_channel,
                                   k_ra8_ipc_irq_event_0,
                                   ipc_wake_handler,
                                   nullptr) != k_ra8_ok) {
    return false;
  }
  if (ra8_isr_register((ra8_elc_event_t)k_ra8_ipc_elc_event_irq0,
                       ipc0_receive_isr,
                       nullptr,
                       (uint8_t)k_ra8_isr_prio_default,
                       nullptr) != k_ra8_ok) {
    return false;
  }
  ra8_isr_globals_enable();
  return true;
}

static void prep_mailbox(volatile com33_mailbox_t* mb)
{
  mb->magic         = 0U;
  mb->req_magic     = 0U;
  mb->m33_sig       = 0U;
  mb->status        = (uint32_t)k_com33_status_running;
  mb->blob_base     = 0U;
  mb->blob_len      = 0U;
  mb->blob_crc      = 0U;
  mb->chapter_count = 0U;
  mb->done          = 0U;
  __asm volatile("dsb" ::: "memory");
  mb->magic = (uint32_t)k_com33_magic;
 
  /* Stage the source .epub into shared SRAM and POST the job: the M33 compiles
   * the staged bytes (not a baked-in array), so the same M33 image serves any
   * book the M85 dispatches -- this is the seam stage c reuses to offload a real
   * dropped book. req_magic is stamped LAST, behind a dsb, so the M33 sees the
   * job only once the staged bytes + request fields are settled in memory. */
  memcpy(com33_epub(), s_m33_parity_epub, (size_t)k_m33_parity_epub_len);
  mb->epub_base = (uint32_t)(uintptr_t)k_com33_epub_addr;
  mb->epub_len  = (uint32_t)k_m33_parity_epub_len;
  mb->out_base  = (uint32_t)(uintptr_t)k_com33_blob_addr;
  mb->out_cap   = (uint32_t)k_com33_blob_cap;
  __asm volatile("dsb" ::: "memory");
  mb->req_magic = (uint32_t)k_com33_req_magic;
  __asm volatile("dsb" ::: "memory");
}

static bool wait_for_m33_sig(const volatile com33_mailbox_t* mb)
{
  RA8_LOOP_BOUND(k_m85_sig_poll_budget);
  for (uint32_t i = 0U; i < (uint32_t)k_m85_sig_poll_budget; i++) {
    if (mb->m33_sig == (uint32_t)k_com33_m33_sig) {
      return true;
    }
  }
  return false;
}

static bool wait_for_done(const volatile com33_mailbox_t* mb)
{
  RA8_LOOP_BOUND(k_m85_done_poll_budget);
  for (uint32_t i = 0U; i < (uint32_t)k_m85_done_poll_budget; i++) {
    if (mb->done == 1U) {
      return true;
    }
    /* IPC-interrupt idle: sleep until the M33 finishes the compile and pokes
     * IPC0ISET0, which raises the armed IPC0 receive IRQ and wakes the core.
     * The M33 orders `done` before that poke (a `dsb`), so the next iteration
     * observes a settled `done` and returns. The bounded count is the NASA
     * Rule 2 backstop: if the wake is ever missed the loop still terminates and
     * the caller reports a timeout instead of hanging. WFI here also means a
     * real import keeps the M85 off the bus while the slow core grinds. */
    __asm volatile("wfi" ::: "memory");
  }
  return false;
}

static bool verify_blob(volatile com33_mailbox_t* mb)
{
  if (mb == nullptr) {
    return false;
  }
  if (mb->status != (uint32_t)k_com33_status_ok) {
    return false;
  }
  if (mb->blob_base != (uint32_t)k_com33_blob_addr) {
    return false;
  }
  const uint32_t len = mb->blob_len;
  if (len == 0U) {
    return false;
  }
  if (len > (uint32_t)k_com33_blob_cap) {
    return false;
  }
  const void* base = (const void*)(uintptr_t)mb->blob_base;
  if (book_validate(base, (size_t)len) != k_ra8_ok) {
    return false;
  }
  const book_header_t* hdr = book_header(base);
  if (hdr->crc32_val != mb->blob_crc) {
    return false;
  }
  if (hdr->chapter_count != mb->chapter_count) {
    return false;
  }
  /* #149 a1: byte-identity on the secondary core. The M33-produced blob must
   * equal the desktop/M85 golden (s_m33_parity_golden) byte for byte -- the same
   * acceptance the M85 parity gate proves, now on the slow core. */
  if (len != (uint32_t)k_m33_parity_golden_len) {
    return false;
  }
  if (memcmp(base, s_m33_parity_golden, (size_t)len) != 0) {
    return false;
  }
  return true;
}

[[noreturn]] static void park_forever(void)
{
  while (1) {
    __asm volatile("nop");
  }
}

void main(void)
{
  ra8_log_init();
  ra8_log_info("M85", "==== RA8D2 compile_on_m33 demo (#149b emitter offload) ====");
  ra8_log_info("M85", "Cortex-M85 primary core online");
  ra8_log_info("M85", "shared mailbox + output blob in SRAM at 0x22100000");
 
  volatile com33_mailbox_t* mb = com33_mailbox();
  prep_mailbox(mb);
 
  /* Arm the IPC0 receive IRQ before releasing the M33 so the M85 can WFI-idle
   * until the M33's compile-done poke wakes it. A setup failure is non-fatal:
   * wait_for_done still bounds-polls the mailbox `done` flag (its WFI then just
   * sleeps until the next interrupt, harmless with the flag re-checked). */
  if (!arm_ipc_wake()) {
    ra8_log_info("M85", "IPC wake arm failed -- falling back to bounded poll");
  } else {
    ra8_log_info("M85", "IPC0 receive IRQ armed -- M85 will WFI-idle for the M33");
  }
 
  ra8_log_info("M85", "releasing Cortex-M33 to run the RABOOK1 emitter ...");
  const ra8_err_t err = ra8_cpu1_release(&g_ra8_ls_cpu1_mram_start, &g_ra8_ls_cpu1_stack_top);
  ra8_log_info_val("M85", "ra8_cpu1_release rc (0 = ok)", (uint32_t)err);
  if (err != k_ra8_ok) {
    ra8_log_info("M85", "release FAILED -- halting");
    park_forever();
  }
 
  if (wait_for_m33_sig(mb)) {
    ra8_log_info("M85", "M33 emitter is alive");
  } else {
    ra8_log_info("M85", "M33 signature not seen -- did it boot?");
  }
 
  ra8_log_info("M85", "M85 yielding -- M33 is compiling the book ...");
  if (!wait_for_done(mb)) {
    ra8_log_info("M85", "M33 done flag not seen -- timed out");
    park_forever();
  }
 
  /* Consumer-side barrier: order the blob/field loads AFTER observing `done`,
   * pairing with the M33's pre-`done` `dsb` so the M85 reads a settled blob. */
  __asm volatile("dmb" ::: "memory");
  ra8_log_info_val("M85", "M33 reported blob length (bytes)", mb->blob_len);
 
  if (verify_blob(mb)) {
    ra8_log_info_val("M85", "book_validate OK; chapters in blob", mb->chapter_count);
    ra8_log_info("M85", "compile_on_m33 PASS");
    park_forever();
  }
 
  /* The M33-produced blob did NOT equal the desktop/M85 golden byte for byte (or
   * failed validation). Trap so the byte-identity is GATED: ra8_emulator's smoke
   * detects the BKPT and fails the run. A silent park here would read as a clean
   * boot and hide a compile regression (e.g. a future ra8_emulator long-shift seam
   * miss on a DEFLATE'd fixture). On real silicon with no debugger the BKPT
   * escalates to a HardFault -- a loud, visible failure for the demo. */
  ra8_log_info_val("M85", "compile_on_m33 FAIL -- status", mb->status);
  __asm volatile("bkpt #0");
  park_forever();
}