42typedef enum : uint32_t {
63typedef enum : uint8_t {
84typedef enum : uint16_t {
Error Code Definitions for ra8-firmware.
Inter-Processor Communication (IPC) register layout for the RA8D2.
ra8_ipc_retry_limits_t
Retry-loop bounds used by the bounded-wait helpers.
@ k_ra8_ipc_retry_max
Hard cap accepted by the API.
@ k_ra8_ipc_sem_take_max
Hard cap on semaphore-take spins.
@ k_ra8_ipc_retry_default
Default poll bound for FIFO retry.
void(* ra8_ipc_event_fn_t)(void *ctx, uint8_t channel, uint32_t event_mask, uint32_t message)
IPC event callback signature.
ra8_ipc_irq_event_id_t
Index of an IRQ event line within a channel (0..7).
@ k_ra8_ipc_irq_event_4
RA8 ipc IRQ event 4.
@ k_ra8_ipc_irq_event_1
RA8 ipc IRQ event 1.
@ k_ra8_ipc_irq_event_2
RA8 ipc IRQ event 2.
@ k_ra8_ipc_irq_event_5
RA8 ipc IRQ event 5.
@ k_ra8_ipc_irq_event_6
RA8 ipc IRQ event 6.
@ k_ra8_ipc_irq_event_0
RA8 ipc IRQ event 0.
@ k_ra8_ipc_irq_event_7
RA8 ipc IRQ event 7.
@ k_ra8_ipc_irq_event_3
RA8 ipc IRQ event 3.
ra8_ipc_event_t
Bitmask reported to the user callback during dispatch.
@ k_ra8_ipc_event_irq3
Maskable IRQ event line 3.
@ k_ra8_ipc_event_irq4
Maskable IRQ event line 4.
@ k_ra8_ipc_event_irq0
Maskable IRQ event line 0.
@ k_ra8_ipc_event_msg_ready
RDY: receive FIFO non-empty.
@ k_ra8_ipc_event_irq5
Maskable IRQ event line 5.
@ k_ra8_ipc_event_fifo_full
FULL: send FIFO is full.
@ k_ra8_ipc_event_irq2
Maskable IRQ event line 2.
@ k_ra8_ipc_event_irq6
Maskable IRQ event line 6.
@ k_ra8_ipc_event_none
No event pending.
@ k_ra8_ipc_event_err_full
FERR: write-while-full.
@ k_ra8_ipc_event_irq1
Maskable IRQ event line 1.
@ k_ra8_ipc_event_err_empty
RERR: read-while-empty.
@ k_ra8_ipc_event_irq_all
IRQ7..IRQ0 union mask.
@ k_ra8_ipc_event_irq7
Maskable IRQ event line 7.
void(* ra8_ipc_nmi_fn_t)(void *ctx, uint8_t unit)
NMI dispatch callback signature.
void(* ra8_ipc_irq_fn_t)(void *ctx, uint8_t channel, ra8_ipc_irq_event_id_t event_id)
Per-IRQ-event-line callback signature.
Snapshot of the security / privilege attribution for one IPC channel, decoded from IPCSAR / IPCPAR.
bool privileged
true -> unprivileged, false -> privileged (IPCPAR.PAIPCIRn).
bool secure
true -> non-secure, false -> secure (IPCSAR.SAIPCIRn).
Per-channel configuration descriptor passed to ra8_ipc_init.
bool reset_fifo
true -> issue CLR.RST during init.
uint8_t channel
Channel id 0..3.
uint32_t event_mask
Bitmask of events the user cares about.
bool clear_status
true -> clear all IRQ + error bits.
Shared-memory ring-buffer descriptor used by the producer / consumer protocol primitives.
uint8_t channel
IPC channel used for notification.
uint8_t sem_id
IPCSEM index used for exclusion.
volatile uint32_t * head
Producer write index (shared).
volatile uint32_t * tail
Consumer read index (shared).
volatile uint32_t * slots
Backing SRAM array (caller-owned).
uint32_t capacity
Number of 32-bit slots in slots.
ra8_ipc_irq_event_id_t notify_id
IRQ event line used for notify.