Cortex-M85 / RA8D2/RA8P1 core bring-up (called from Reset_Handler). More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_boot_entry.h"
#include "ra8_boot_intrinsics.h"
#include "ra8_cache.h"
#include "trustzone_init.h"

Include dependency graph for system_init.c:

Enumerations
enum	ra8_core_addr_t : uintptr_t { k_ra8_scb_vtor_addr = 0xE000ED08UL , k_ra8_scb_ccr_addr = 0xE000ED14UL , k_ra8_scb_shcsr_addr = 0xE000ED24UL , k_ra8_scb_cpacr_addr = 0xE000ED88UL , k_ra8_scb_nsacr_addr = 0xE000ED8CUL , k_ra8_scb_iciallu = 0xE000EF50UL , k_ra8_scb_dciallu = 0xE000EF58UL , k_ra8_scb_csselr = 0xE000ED84UL , k_ra8_scb_ccsidr = 0xE000ED80UL , k_ra8_scb_dcisw = 0xE000EF60UL , k_ra8_fpu_fpccr_addr = 0xE000EF34UL , k_ra8_nvic_aircr = 0xE000ED0CUL , k_ra8_mpu_type_addr = 0xE000ED90UL , k_ra8_mpu_ctrl_addr = 0xE000ED94UL , k_ra8_mpu_rnr_addr = 0xE000ED98UL , k_ra8_mpu_rbar_addr = 0xE000ED9CUL , k_ra8_mpu_rlar_addr = 0xE000EDA0UL , k_ra8_mpu_mair0_addr = 0xE000EDC0UL , k_ra8_mpu_mair1_addr = 0xE000EDC4UL }
enum	: uint32_t { k_ra8_rbar_attr_ro_x = 0x06U , k_ra8_rbar_attr_rw_xn = 0x03U , k_ra8_mpu_rlar_enable = 1UL << 0 }
	Programme and enable the Cortex-M85 core MPU. More...
enum	: uint32_t { k_ra8_mpu_rlar_attridx_shift = 1U , k_ra8_mpu_attridx_normal_wbwa = 0U , k_ra8_mpu_attridx_noncacheable = 1U , k_ra8_mpu_attridx_device = 2U }
enum	: uint32_t { k_ra8_mpu_mram_base = 0x02000000UL , k_ra8_mpu_mram_limit = 0x020FFFE0UL , k_ra8_mpu_sram_base = 0x22000000UL , k_ra8_mpu_sram_limit = 0x220FFFE0UL , k_ra8_mpu_shram_base = 0x22100000UL , k_ra8_mpu_shram_limit = 0x2219FFE0UL , k_ra8_mpu_sdram_base = 0x68000000UL , k_ra8_mpu_sdram_limit = 0x6BFFFFE0UL , k_ra8_mpu_peri_base = 0x40000000UL , k_ra8_mpu_peri_limit = 0x47FFFFE0UL }

Functions
static void	internal_set_vtor (void)
	Point VTOR at the physical vector table base.
static void	internal_enable_fpu (void)
	Grant full access to CP10 / CP11 (the FPU coprocessors).
static void	internal_enable_fpu_lazy_stack (void)
	Turn on FPU lazy stacking (FPCCR.LSPEN = 1, ASPEN = 1).
static void	internal_enable_icache (void)
	Invalidate and enable the Cortex-M85 I-cache.
static void	internal_enable_dcache (void)
	Invalidate and enable the Cortex-M85 D-cache.
static void	internal_enable_branch_predictor (void)
	Enable branch-target prediction (CCR.BP on Cortex-M85).
static void	internal_enable_fault_handlers (void)
	Enable the configurable-fault handlers so faults decode by class.
static void	internal_enable_div0_trap (void)
	Make integer divide-by-zero trap as a decoded UsageFault.
static void	internal_set_priority_grouping (void)
	Set NVIC priority grouping to 4 preempt bits / 0 sub-priority.
static void	internal_mpu_set_region (uint32_t region, uint32_t base_attr, uint32_t limit_enable, uint32_t attr_idx)
	Program a single MPU region via RNR/RBAR/RLAR.
static void	internal_mpu_init (void)
	Programme and enable the Cortex-M85 core MPU.
void	SystemInit (void)
	Earliest C code the image runs: bring the core up before RAM init.

Variables
const uint32_t	g_ra8_vector_table_start []
uint32_t	g_ra8_ls_stack_top

Detailed Description

Cortex-M85 / RA8D2/RA8P1 core bring-up (called from Reset_Handler).

Note: RA8P1 board layer (issue #226): this chip-boot TU is byte-identical to the EK-RA8D2 copy. The RA8P1 (R7KA8P1KFLCAC) shares the RA8D2 Cortex-M85 core, cache/MPU, and CGC-reset state (see libs/ra8_core/inc/ra8_device.h), so the core bring-up is common; HUM citations reference the RA8D2 manual (R01UH1065EJ), which documents the byte-identical registers.

SystemInit() follows the CMSIS naming convention and runs as the first C function out of reset, before Reset_Handler copies .data or zeroes .bss. Its responsibilities are strictly CPU-core level – anything peripheral-bus-side belongs in ra8_infrastructure_init() called from main() after the C runtime is live.

Bring-up sequence

Set VTOR to the physical address of the vector table (so that linker relocations and later TrustZone / bootloader hand-offs work).
Enable CP10 / CP11 so the FPU is usable before any floating-point instruction runs.
Enable FPU lazy stacking (FPCCR.LSPEN) so ISRs do not pay the full FP-state save cost unless they touch the FPU.
Enable the configurable-fault handlers (SHCSR MEM/BUS/USG/ SECUREFAULTENA) and the divide-by-zero trap (CCR.DIV_0_TRP) so every fault decodes with its true class instead of an anonymous HardFault.
Enable the I-cache and D-cache (Cortex-M85 has both). Without this the core runs at a small fraction of its rated speed.
Enable the branch-target predictor (CCR.BP).
Programme NVIC priority grouping to 4 bits preempt / 0 bits sub (the standard embedded pattern).
Disable interrupts until the application is ready – this mirrors CMSIS convention. main() re-enables via __enable_irq() once all drivers are up.

The function is C, not naked asm, so stack and BSS must already be usable. Reset_Handler loads SP from the vector table before calling SystemInit(), so the stack is fine; BSS is zeroed only after SystemInit() returns but SystemInit() writes to no BSS or data-section variables, so the ordering is safe.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file system_init.c.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum : uint32_t

Programme and enable the Cortex-M85 core MPU.

Installs five regions and enables the MPU with PRIVDEFENA so privileged mode still sees the default memory map for anything not explicitly covered. Activated (with the caches) behind the RA8_BOOT_ENABLE_CACHE_MPU build flag; default OFF leaves the MPU disabled and the boot unchanged.

Region 0: MRAM code (0x02000000, 1 MiB) – RO + execute, cacheable.
Region 1: M85 private SRAM0+1 (0x22000000, 1 MiB) – RW/NX, cacheable.
Region 2: SDRAM (0x68000000, 64 MiB) – RW/NX, cacheable.
Region 3: Peripherals (0x40000000, 128 MiB) – RW/NX, Device-nGnRE.
Region 4: M85<->M33 shared SRAM2+3 (0x22100000, 576 KiB) – RW/NX, Normal NON-cacheable (mailbox + CPU1 RAM stay coherent across cores).

Attribute indirection table:

MAIR0[0] = 0xFF (Normal inner + outer write-back / write-alloc).
MAIR0[1] = 0x44 (Normal non-cacheable).
MAIR0[2] = 0x04 (Device-nGnRE).

Per ARMv8-M PMSAv8: RBAR[4:0] = SH[4:3] | AP[2:1] | XN[0] (permissions); RLAR = LIMIT[31:5] | AttrIndx[3:1] | EN[0], where AttrIndx selects the MAIR byte that sets the region's memory TYPE (cacheable vs Device).

Note: The shared SRAM bank (region 4) is non-cacheable, so cross-core hand-offs need no software cache maintenance (the M33 is cacheless). The private SRAM limit is now tight (ends at 0x220FFFFF). SDRAM (region 2) stays cacheable – DMA buffers there still need a non-cacheable placement or an explicit clean/invalidate at the DMA boundary (T4-02).

Enumerator
k_ra8_rbar_attr_ro_x	AP=RO any-priv, SH=none, XN=0 (executable).
k_ra8_rbar_attr_rw_xn	AP=RW any-priv, SH=none, XN=1 (no execute).
k_ra8_mpu_rlar_enable	RA8 MPU rlar enable.

Definition at line 393 of file system_init.c.

◆ anonymous enum

anonymous enum : uint32_t

Enumerator
k_ra8_mpu_rlar_attridx_shift	RA8 MPU rlar attridx shift.
k_ra8_mpu_attridx_normal_wbwa	MAIR0[0] 0xFF: Normal inner/outer WB/WA.
k_ra8_mpu_attridx_noncacheable	MAIR0[1] 0x44: Normal non-cacheable.
k_ra8_mpu_attridx_device	MAIR0[2] 0x04: Device-nGnRE (MMIO).

Definition at line 404 of file system_init.c.

◆ anonymous enum

anonymous enum : uint32_t

Enumerator
k_ra8_mpu_mram_base	1 MiB MRAM code region.
k_ra8_mpu_mram_limit	RA8 MPU MRAM limit.
k_ra8_mpu_sram_base	M85 private SRAM0+1, 1 MiB, cacheable.
k_ra8_mpu_sram_limit	RA8 MPU SRAM limit.
k_ra8_mpu_shram_base	Shared SRAM2+3: M33 mailbox + CPU1 RAM.
k_ra8_mpu_shram_limit	Non-cacheable -> M85<->M33 stays coherent.
k_ra8_mpu_sdram_base	64 MiB external SDRAM.
k_ra8_mpu_sdram_limit	RA8 MPU SDRAM limit.
k_ra8_mpu_peri_base	Peripheral bus window base.
k_ra8_mpu_peri_limit	RA8 MPU peri limit.

Definition at line 413 of file system_init.c.

◆ ra8_core_addr_t

enum ra8_core_addr_t : uintptr_t

Enumerator
k_ra8_scb_vtor_addr	Vector Table Offset Register.
k_ra8_scb_ccr_addr	Configuration and Control Register.
k_ra8_scb_shcsr_addr	System Handler Control and State.
k_ra8_scb_cpacr_addr	Coprocessor Access Control.
k_ra8_scb_nsacr_addr	Non-secure Access Control.
k_ra8_scb_iciallu	ICIALLU – invalidate I-cache.
k_ra8_scb_dciallu	DCIALLU – invalidate D-cache (sets only).
k_ra8_scb_csselr	Cache Size Selection Register.
k_ra8_scb_ccsidr	Cache Size ID Register.
k_ra8_scb_dcisw	D-cache Invalidate by Set/Way.
k_ra8_fpu_fpccr_addr	FPU Context Control Register.
k_ra8_nvic_aircr	Application Interrupt and Reset Ctrl.
k_ra8_mpu_type_addr	MPU Type Register.
k_ra8_mpu_ctrl_addr	MPU Control Register.
k_ra8_mpu_rnr_addr	MPU Region Number.
k_ra8_mpu_rbar_addr	MPU Region Base Address.
k_ra8_mpu_rlar_addr	MPU Region Limit Address.
k_ra8_mpu_mair0_addr	MPU Attribute Indirection 0.
k_ra8_mpu_mair1_addr	MPU Attribute Indirection 1.

Definition at line 66 of file system_init.c.

Function Documentation

◆ internal_enable_branch_predictor()

void internal_enable_branch_predictor ( void )

static

Enable branch-target prediction (CCR.BP on Cortex-M85).

Sets the architectural branch-prediction enable bit and retires the control-register update with data and instruction barriers.

Precondition: Execution is privileged during the single-threaded reset path.; No concurrent code modifies the System Control Block CCR.

Postcondition: CCR.BP is set and branch prediction is enabled.; The control-register write is globally observed.

Note: Call once during reset before interrupts or secondary-core launch.

Since: 0.1.0

< RA8 ccr bp.

Definition at line 229 of file system_init.c.

References k_ra8_scb_ccr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

◆ internal_enable_dcache()

void internal_enable_dcache ( void )

static

Invalidate and enable the Cortex-M85 D-cache.

Runs the full CCSIDR-driven invalidate-by-set/way pass (ra8_cache_dcache_invalidate_all()) BEFORE setting CCR.DC, so no random power-on line content is ever treated as valid once the cache is enabled. This replaces the earlier "bulk CCR.DC = 1" shortcut, which relied on an unverified boot-ROM guarantee that the lines came up invalid. The function stays gated off (only address-taken in SystemInit) until the coherency substrate – clean-before-DMA and the non-cacheable region – lands; the actual enable is T4-06.

Precondition: Execution is privileged during the single-threaded reset path.; No DMA or secondary-core transaction can observe cacheable data yet.

Postcondition: The data cache is invalidated and enabled through CCR.DC.; The cache and control-register changes are globally observed.

Note: The board coherency policy must be installed before this is called.

Since: 0.1.0

< RA8 ccr dc.

Definition at line 205 of file system_init.c.

References k_ra8_scb_ccr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), ra8_boot_write32(), and ra8_cache_dcache_invalidate_all().

◆ internal_enable_div0_trap()

void internal_enable_div0_trap ( void )

static

Make integer divide-by-zero trap as a decoded UsageFault.

Out of reset CCR.DIV_0_TRP is 0 and an SDIV/UDIV by zero silently returns 0 – the strongest possible "garbage in, garbage onward" failure mode for control code. Setting the trap makes a zero divisor raise UsageFault with CFSR.DIVBYZERO, which internal_enable_fault_handlers() has already routed to the decoding UsageFault_Handler trampoline, so the faulting PC and the cause land in g_ra8_exception_last instead of propagating a bogus quotient.

CCR.UNALIGN_TRP (bit 3) is deliberately NOT set. Evidence: this tree compiles with arm-none-eabi-gcc's default -munaligned-access (confirmed [enabled] for -mcpu=cortex-m85 via -Q --help=target), under which the compiler is entitled to emit hardware-supported unaligned word accesses – and does, e.g. when expanding the small fixed-size memcpy() idiom the vendored SOUP decoders (miniz via MINIZ_UNALIGNED_USE_MEMCPY, stb) use for byte-buffer reads, and for packed-struct field access. The prebuilt newlib libc is compiled the same way. Trapping unaligned accesses would therefore fault legitimate generated code; it can only ever be enabled together with a whole-tree (and libc) rebuild under -mno-unaligned-access.

Precondition: Running privileged out of reset with the vector table installed.; internal_enable_fault_handlers() has set SHCSR.USGFAULTENA.

Postcondition: CCR.DIV_0_TRP is set; a zero divisor now raises UsageFault.; A dsb/isb pair retires the change before any divide executes.

Note: Not thread-safe; single-threaded boot only.

Since: 0.1.0

< RA8 ccr div 0 trp.

Definition at line 324 of file system_init.c.

References k_ra8_scb_ccr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), ra8_boot_write32(), and RA8_INTERNAL.

◆ internal_enable_fault_handlers()

void internal_enable_fault_handlers ( void )

static

Enable the configurable-fault handlers so faults decode by class.

Out of reset SHCSR.{MEM,BUS,USG,SECURE}FAULTENA are 0, so MemManage, BusFault, UsageFault and SecureFault all escalate to HardFault and the per-class exception trampolines (exc 4/5/6/7, which forward into ra8_exception_report) never fire – the real fault class is lost. Set the four enables so each configurable fault is taken by its own handler and reported with its true class. Always-on diagnostics, independent of the cache / MPU build flag.

SECUREFAULTENA (bit 19) scoping decision: the bit is banked and exists only in the Secure view of SHCSR (from the Non-secure state it is RES0, so a misplaced write is architecturally ignored). This shared SystemInit runs out of reset, and the RA8D2 core always resets into the Secure state – flat (non-TrustZone) apps simply never leave it – so the write always lands in the Secure bank. It is enabled unconditionally (no build flag) because every image in this repository carries a decoded SecureFault handler: the shared boot secure_exception.c trampoline, or a per-app secure_exception.c override (all of which decode SFSR). With the bit off, a TrustZone security violation (SG check, attribution mismatch, INVTRAN) halts as an anonymous HardFault; with it on, the same violation reaches SecureFault_Handler and is recorded with its true class + SFSR/SFAR. No non-fault code path changes, so HW-validated apps see identical behaviour until something actually faults.

Precondition: Running privileged out of reset with the vector table installed.; The per-app vector table forwards exc 4/5/6/7 into ra8_exception_report.

Postcondition: SHCSR.MEMFAULTENA, BUSFAULTENA, USGFAULTENA and SECUREFAULTENA are set.; A dsb/isb pair retires the change before the first fault can be taken.

Note: Not thread-safe; single-threaded boot only.

Since: 0.1.0

< RA8 shcsr memfaultena.

< RA8 shcsr busfaultena.

< RA8 shcsr usgfaultena.

< RA8 shcsr securefaultena.

Definition at line 273 of file system_init.c.

References k_ra8_scb_shcsr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), ra8_boot_write32(), and RA8_INTERNAL.

◆ internal_enable_fpu()

void internal_enable_fpu ( void )

static

Grant full access to CP10 / CP11 (the FPU coprocessors).

Sets the CPACR access bits then barriers so the FPU is usable before any floating-point instruction executes.

Precondition: Running privileged out of reset.; No floating-point instruction has executed yet.

Postcondition: CP10/CP11 have full access; the FPU is usable.; A dsb/isb pair has retired the change.

Note: Not thread-safe; single-threaded boot only.

Since: 0.1.0

< RA8 cpacr cp10 cp11 full access.

Definition at line 125 of file system_init.c.

References k_ra8_scb_cpacr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

◆ internal_enable_fpu_lazy_stack()

void internal_enable_fpu_lazy_stack ( void )

static

Turn on FPU lazy stacking (FPCCR.LSPEN = 1, ASPEN = 1).

Lets ISRs skip the full FP-state save unless they touch the FPU, reducing worst-case interrupt latency.

Precondition: Running privileged out of reset.; internal_enable_fpu() has granted CP10/CP11 access.

Postcondition: FPCCR.LSPEN and FPCCR.ASPEN are set.; No other core state is changed.

Note: Not thread-safe; single-threaded boot only.

Since: 0.1.0

< RA8 fpccr lspen.

< RA8 fpccr aspen.

Definition at line 148 of file system_init.c.

References k_ra8_fpu_fpccr_addr, ra8_boot_read32(), and ra8_boot_write32().

◆ internal_enable_icache()

void internal_enable_icache ( void )

static

Invalidate and enable the Cortex-M85 I-cache.

Invalidates all instruction-cache lines before setting CCR.IC and retires the state transition with data and instruction barriers.

Precondition: Execution is privileged during the single-threaded reset path.; No application code depends on cached instructions yet.

Postcondition: CCR.IC is set and the instruction cache is enabled.; The invalidate and control-register write are globally observed.

Note: Call once during reset before interrupts or secondary-core launch.

Since: 0.1.0

< RA8 ccr ic.

Definition at line 170 of file system_init.c.

References k_ra8_scb_ccr_addr, k_ra8_scb_iciallu, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

◆ internal_mpu_init()

void internal_mpu_init ( void )

static

Programme and enable the Cortex-M85 core MPU.

Installs code, private SRAM, SDRAM, peripheral, and shared-memory regions with explicit MAIR types before enabling the privileged map.

Precondition: Execution is privileged during the single-threaded reset path.; No application or interrupt accesses memory under an earlier MPU map.

Postcondition: The five board regions and their MAIR attributes are installed.; The MPU is enabled with PRIVDEFENA and barriers have retired the map.

Note: Call once during reset before caches, interrupts, or secondary-core launch.

Since: 0.1.0

< RA8 MPU control enable.

< RA8 MPU control privdefena.

< RA8 mair0 default.

Definition at line 464 of file system_init.c.

References internal_mpu_set_region(), k_ra8_mpu_attridx_device, k_ra8_mpu_attridx_noncacheable, k_ra8_mpu_attridx_normal_wbwa, k_ra8_mpu_ctrl_addr, k_ra8_mpu_ctrl_enable, k_ra8_mpu_ctrl_privdefena, k_ra8_mpu_mair0_addr, k_ra8_mpu_mair1_addr, k_ra8_mpu_mram_base, k_ra8_mpu_mram_limit, k_ra8_mpu_peri_base, k_ra8_mpu_peri_limit, k_ra8_mpu_rlar_enable, k_ra8_mpu_sdram_base, k_ra8_mpu_sdram_limit, k_ra8_mpu_shram_base, k_ra8_mpu_shram_limit, k_ra8_mpu_sram_base, k_ra8_mpu_sram_limit, k_ra8_rbar_attr_ro_x, k_ra8_rbar_attr_rw_xn, ra8_boot_dsb(), ra8_boot_isb(), and ra8_boot_write32().

◆ internal_mpu_set_region()

void internal_mpu_set_region	(	uint32_t	region,
		uint32_t	base_attr,
		uint32_t	limit_enable,
		uint32_t	attr_idx )

static

Program a single MPU region via RNR/RBAR/RLAR.

attr_idx (written into RLAR AttrIndx, bits[3:1]) selects the region's MAIR byte and therefore its memory type – this is what makes the peripheral region Device-nGnRE rather than Normal cacheable.

Parameters

[in]	region	MPU region number to select.
[in]	base_attr	Aligned base address combined with RBAR attributes.
[in]	limit_enable	Aligned limit combined with RLAR enable.
[in]	attr_idx	MAIR attribute index for the region's memory type.

Precondition: Execution is privileged and the MPU is disabled.; All address and attribute fields satisfy the ARMv8-M MPU encoding.

Postcondition: The selected region contains the supplied RBAR and RLAR values.; No other MPU region is modified.

Note: This helper does not validate caller-prepared register encodings.

Since: 0.1.0

Definition at line 443 of file system_init.c.

References k_ra8_mpu_rbar_addr, k_ra8_mpu_rlar_addr, k_ra8_mpu_rlar_attridx_shift, k_ra8_mpu_rnr_addr, and ra8_boot_write32().

◆ internal_set_priority_grouping()

void internal_set_priority_grouping ( void )

static

Set NVIC priority grouping to 4 preempt bits / 0 sub-priority.

Writes AIRCR with the VECTKEY and PRIGROUP=3, the standard embedded split (all priority bits are preempt, none sub-priority).

Precondition: Running privileged out of reset.; Interrupts are still masked.

Postcondition: AIRCR.PRIGROUP = 3 (4 preempt bits, 0 sub-priority bits).; No reset was triggered (correct VECTKEY used).

Note: Not thread-safe; single-threaded boot only.

Since: 0.1.0

< Required write key.

< PRIGROUP = 3 -> 4 bits.

Definition at line 350 of file system_init.c.

References k_ra8_nvic_aircr, and ra8_boot_write32().

◆ internal_set_vtor()

void internal_set_vtor ( void )

static

Point VTOR at the physical vector table base.

Writes the absolute vector-table address into SCB->VTOR so exceptions dispatch through the linker-pinned table in MRAM.

Precondition: Running privileged out of reset.; g_ra8_vector_table_start resolves to the .vectors base.

Postcondition: SCB->VTOR holds the vector-table base address.; No other core state is changed.

Note: Not thread-safe; single-threaded boot only.

Since: 0.1.0

Definition at line 106 of file system_init.c.

References g_ra8_vector_table_start, k_ra8_scb_vtor_addr, and ra8_boot_write32().

◆ SystemInit()

void SystemInit ( void )

Earliest C code the image runs: bring the core up before RAM init.

Called by Reset_Handler before .data is copied and .bss is zeroed, so it must not touch initialised or zero-initialised statics. Each image supplies its own definition – the shared board one under the board boot directories, or an application-local system_init.c where the clock tree or memory map diverges.

The name is the CMSIS convention; the startup code reaches it by that name, which is why it has external linkage.

Precondition: The CPU is at the reset vector with interrupts masked.; .data has not been copied and .bss has not been zeroed.

Postcondition: The clock tree, cache and memory controller are configured.; It is safe for Reset_Handler to initialise RAM and call main.

Note: Not thread-safe; single-threaded reset context only.

Warning: Must not read or write any static that startup has yet to initialise – at this point they hold whatever SRAM held.

See also: Default_Handler()

Since: 0.1.0

Definition at line 518 of file system_init.c.

References internal_enable_branch_predictor(), internal_enable_dcache(), internal_enable_div0_trap(), internal_enable_fault_handlers(), internal_enable_fpu(), internal_enable_fpu_lazy_stack(), internal_enable_icache(), internal_mpu_init(), internal_set_priority_grouping(), internal_set_vtor(), ra8_boot_disable_irq(), and ra8_trustzone_init().

Variable Documentation

◆ g_ra8_ls_stack_top

uint32_t g_ra8_ls_stack_top

extern

◆ g_ra8_vector_table_start

const uint32_t g_ra8_vector_table_start[]

extern

Definition at line 294 of file vector_table.c.

Enumerations

Functions

Variables

Detailed Description

Bring-up sequence

Enumeration Type Documentation

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ ra8_core_addr_t

Function Documentation

◆ internal_enable_branch_predictor()

◆ internal_enable_dcache()

◆ internal_enable_div0_trap()

◆ internal_enable_fault_handlers()

◆ internal_enable_fpu()

◆ internal_enable_fpu_lazy_stack()

◆ internal_enable_icache()

◆ internal_mpu_init()

◆ internal_mpu_set_region()

◆ internal_set_priority_grouping()

◆ internal_set_vtor()

◆ SystemInit()

Variable Documentation

◆ g_ra8_ls_stack_top

◆ g_ra8_vector_table_start