system_init.c File Reference

Cortex-M85 / RA8D2 core bring-up – MPU map via the ra8_mpu HAL (#576). More...

#include <stdint.h>
#include "ra8_boot_entry.h"
#include "ra8_boot_intrinsics.h"
#include "ra8_cache.h"
#include "ra8_err.h"
#include "ra8_mpu.h"
#include "trustzone_init.h"

Include dependency graph for system_init.c:

Go to the source code of this file.

Enumerations

enum

ra8_core_addr_t : uintptr_t {   k_ra8_scb_vtor_addr = 0xE000ED08UL ,   k_ra8_scb_ccr_addr = 0xE000ED14UL ,   k_ra8_scb_shcsr_addr = 0xE000ED24UL ,   k_ra8_scb_cpacr_addr = 0xE000ED88UL ,   k_ra8_scb_nsacr_addr = 0xE000ED8CUL ,   k_ra8_scb_iciallu = 0xE000EF50UL ,   k_ra8_scb_dciallu = 0xE000EF58UL ,   k_ra8_scb_csselr = 0xE000ED84UL ,   k_ra8_scb_ccsidr = 0xE000ED80UL ,   k_ra8_scb_dcisw = 0xE000EF60UL ,   k_ra8_fpu_fpccr_addr = 0xE000EF34UL ,   k_ra8_nvic_aircr = 0xE000ED0CUL }

Functions
static void	internal_set_vtor (void)
	Point VTOR at the physical vector table base.
static void	internal_enable_fpu (void)
	Grant full access to CP10 / CP11 (the FPU coprocessors).
static void	internal_enable_fpu_lazy_stack (void)
	Turn on FPU lazy stacking (FPCCR.LSPEN = 1, ASPEN = 1).
static void	internal_enable_icache (void)
	Invalidate and enable the Cortex-M85 I-cache.
static void	internal_enable_dcache (void)
	Invalidate and enable the Cortex-M85 D-cache.
static void	internal_enable_branch_predictor (void)
	Enable branch-target prediction (CCR.BP on Cortex-M85).
static void	internal_enable_fault_handlers (void)
	Enable the configurable-fault handlers so faults decode by class.
static void	internal_enable_div0_trap (void)
	Make integer divide-by-zero trap as a decoded UsageFault.
static void	internal_set_priority_grouping (void)
	Set NVIC priority grouping to 4 preempt bits / 0 sub-priority.
void	SystemInit (void)
	Earliest C code the image runs: bring the core up before RAM init.

Variables
const uint32_t	g_ra8_vector_table_start []
uint32_t	g_ra8_ls_stack_top

Detailed Description

Cortex-M85 / RA8D2 core bring-up – MPU map via the ra8_mpu HAL (#576).

Per-app override of the shared board SystemInit() that installs the boot MPU memory-attribute map through the ra8_mpu HAL (ra8_mpu_apply_boot_map()) instead of hand-rolling the MAIR / RBAR / RLAR / CTRL register pokes. It is kept ALONGSIDE the raw-poke reference (libs/ra8_board_ek_ra8d2/src/boot/system_init.c, used by e.g. cache_mpu_hil): every other bring-up step here is byte-identical, so a diff of the two files shows exactly the raw-pokes-vs-HAL boot difference, and the two apps can be compared on HIL.

SystemInit() follows the CMSIS naming convention and runs as the first C function out of reset, before Reset_Handler copies .data or zeroes .bss. ra8_mpu_apply_boot_map() is safe in that window: it reads only the driver-owned const region table (in .rodata) and MMIO, writes no .data/.bss, and never logs – exactly as this same function already calls ra8_cache_dcache_invalidate_all() from boot.

Bring-up sequence

1. Set VTOR to the physical address of the vector table.
2. Enable CP10 / CP11 so the FPU is usable before any FP instruction runs.
3. Enable FPU lazy stacking (FPCCR.LSPEN).
4. Enable the configurable-fault handlers and the divide-by-zero trap.
5. (cache+MPU build) Install the boot MPU map via the HAL, then enable the I-cache / D-cache / branch predictor.
6. Programme NVIC priority grouping to 4 bits preempt / 0 bits sub.
7. Disable interrupts until the application is ready.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file system_init.c.

Enumeration Type Documentation

ra8_core_addr_t

enum ra8_core_addr_t : uintptr_t

Enumerator
k_ra8_scb_vtor_addr	Vector Table Offset Register.
k_ra8_scb_ccr_addr	Configuration and Control Register.
k_ra8_scb_shcsr_addr	System Handler Control and State.
k_ra8_scb_cpacr_addr	Coprocessor Access Control.
k_ra8_scb_nsacr_addr	Non-secure Access Control.
k_ra8_scb_iciallu	ICIALLU – invalidate I-cache.
k_ra8_scb_dciallu	DCIALLU – invalidate D-cache (sets only).
k_ra8_scb_csselr	Cache Size Selection Register.
k_ra8_scb_ccsidr	Cache Size ID Register.
k_ra8_scb_dcisw	D-cache Invalidate by Set/Way.
k_ra8_fpu_fpccr_addr	FPU Context Control Register.
k_ra8_nvic_aircr	Application Interrupt and Reset Ctrl.

Definition at line 57 of file system_init.c.

Function Documentation

internal_enable_branch_predictor()

void internal_enable_branch_predictor ( void )

static

Enable branch-target prediction (CCR.BP on Cortex-M85).

Sets CCR.BP so the branch predictor is active with the caches.

Precondition

Running privileged out of reset.

The I-cache is already enabled.

Postcondition

CCR.BP is set.

A dsb/isb pair retires the change.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< RA8 ccr bp.

Definition at line 211 of file system_init.c.

References k_ra8_scb_ccr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

internal_enable_dcache()

void internal_enable_dcache ( void )

static

Invalidate and enable the Cortex-M85 D-cache.

Runs the full CCSIDR-driven invalidate-by-set/way pass (ra8_cache_dcache_invalidate_all()) BEFORE setting CCR.DC, so no random power-on line content is ever treated as valid once the cache is enabled.

Precondition

The MPU attribute map is installed (non-cacheable shared SRAM + Device-nGnRE MMIO) so the D-cache never caches what must stay coherent.

Running privileged out of reset.

Postcondition

CCR.DC is set and the D-cache is enabled.

A dsb/isb pair retires the change.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< RA8 ccr dc.

Definition at line 188 of file system_init.c.

References k_ra8_scb_ccr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), ra8_boot_write32(), and ra8_cache_dcache_invalidate_all().

internal_enable_div0_trap()

void internal_enable_div0_trap ( void )

static

Make integer divide-by-zero trap as a decoded UsageFault.

Out of reset CCR.DIV_0_TRP is 0 and an SDIV/UDIV by zero silently returns

1. Setting the trap makes a zero divisor raise UsageFault with CFSR.DIVBYZERO, which internal_enable_fault_handlers() has already routed to the decoding UsageFault_Handler trampoline. CCR.UNALIGN_TRP stays 0 – the toolchain emits hardware-supported unaligned accesses by default.

Precondition

Running privileged out of reset with the vector table installed.

internal_enable_fault_handlers() has set SHCSR.USGFAULTENA.

Postcondition

CCR.DIV_0_TRP is set; a zero divisor now raises UsageFault.

A dsb/isb pair retires the change before any divide executes.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< RA8 ccr div 0 trp.

Definition at line 276 of file system_init.c.

References k_ra8_scb_ccr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

Referenced by SystemInit().

internal_enable_fault_handlers()

void internal_enable_fault_handlers ( void )

static

Enable the configurable-fault handlers so faults decode by class.

Out of reset SHCSR.{MEM,BUS,USG,SECURE}FAULTENA are 0, so MemManage, BusFault, UsageFault and SecureFault all escalate to HardFault and the per-class exception trampolines never fire. Set the four enables so each configurable fault is taken by its own handler and reported with its true class. Always-on diagnostics, independent of the cache / MPU build flag.

Precondition

Running privileged out of reset with the vector table installed.

The per-app vector table forwards exc 4/5/6/7 into ra8_exception_report.

Postcondition

SHCSR.MEMFAULTENA, BUSFAULTENA, USGFAULTENA and SECUREFAULTENA are set.

A dsb/isb pair retires the change before the first fault can be taken.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< RA8 shcsr memfaultena.

< RA8 shcsr busfaultena.

< RA8 shcsr usgfaultena.

< RA8 shcsr securefaultena.

Definition at line 238 of file system_init.c.

References k_ra8_scb_shcsr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

Referenced by SystemInit().

internal_enable_fpu()

void internal_enable_fpu ( void )

static

Grant full access to CP10 / CP11 (the FPU coprocessors).

Sets the CPACR access bits then barriers so the FPU is usable before any floating-point instruction executes.

Precondition

Running privileged out of reset.

No floating-point instruction has executed yet.

Postcondition

CP10/CP11 have full access; the FPU is usable.

A dsb/isb pair has retired the change.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< RA8 cpacr cp10 cp11 full access.

Definition at line 109 of file system_init.c.

References k_ra8_scb_cpacr_addr, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

internal_enable_fpu_lazy_stack()

void internal_enable_fpu_lazy_stack ( void )

static

Turn on FPU lazy stacking (FPCCR.LSPEN = 1, ASPEN = 1).

Lets ISRs skip the full FP-state save unless they touch the FPU, reducing worst-case interrupt latency.

Precondition

Running privileged out of reset.

internal_enable_fpu() has granted CP10/CP11 access.

Postcondition

FPCCR.LSPEN and FPCCR.ASPEN are set.

No other core state is changed.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< RA8 fpccr lspen.

< RA8 fpccr aspen.

Definition at line 132 of file system_init.c.

References k_ra8_fpu_fpccr_addr, ra8_boot_read32(), and ra8_boot_write32().

internal_enable_icache()

void internal_enable_icache ( void )

static

Invalidate and enable the Cortex-M85 I-cache.

Invalidates the whole I-cache (ICIALLU) with the surrounding barriers, then sets CCR.IC. Gated with the D-cache and MPU behind the cache+MPU build flag.

Precondition

Running privileged out of reset with the vector table installed.

The MPU attribute map is installed so instruction fetches see the correct memory type.

Postcondition

CCR.IC is set and the I-cache is enabled.

A dsb/isb pair retires the change.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< RA8 ccr ic.

Definition at line 156 of file system_init.c.

References k_ra8_scb_ccr_addr, k_ra8_scb_iciallu, ra8_boot_dsb(), ra8_boot_isb(), ra8_boot_read32(), and ra8_boot_write32().

internal_set_priority_grouping()

void internal_set_priority_grouping ( void )

static

Set NVIC priority grouping to 4 preempt bits / 0 sub-priority.

Writes AIRCR with the VECTKEY and PRIGROUP=3, the standard embedded split (all priority bits are preempt, none sub-priority).

Precondition

Running privileged out of reset.

Interrupts are still masked.

Postcondition

AIRCR.PRIGROUP = 3 (4 preempt bits, 0 sub-priority bits).

No reset was triggered (correct VECTKEY used).

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

< Required write key.

< PRIGROUP = 3 -> 4 bits.

Definition at line 301 of file system_init.c.

References k_ra8_nvic_aircr, and ra8_boot_write32().

internal_set_vtor()

void internal_set_vtor ( void )

static

Point VTOR at the physical vector table base.

Writes the absolute vector-table address into SCB->VTOR so exceptions dispatch through the linker-pinned table in MRAM.

Precondition

Running privileged out of reset.

g_ra8_vector_table_start resolves to the .vectors base.

Postcondition

SCB->VTOR holds the vector-table base address.

No other core state is changed.

Note

Not thread-safe; single-threaded boot only.

Since

0.1.0

Definition at line 90 of file system_init.c.

References g_ra8_vector_table_start, k_ra8_scb_vtor_addr, and ra8_boot_write32().

SystemInit()

void SystemInit

(

void

)

Earliest C code the image runs: bring the core up before RAM init.

Called by Reset_Handler before .data is copied and .bss is zeroed, so it must not touch initialised or zero-initialised statics. Each image supplies its own definition – the shared board one under the board boot directories, or an application-local system_init.c where the clock tree or memory map diverges.

The name is the CMSIS convention; the startup code reaches it by that name, which is why it has external linkage.

Precondition

The CPU is at the reset vector with interrupts masked.

.data has not been copied and .bss has not been zeroed.

Postcondition

The clock tree, cache and memory controller are configured.

It is safe for Reset_Handler to initialise RAM and call main.

Note

Not thread-safe; single-threaded reset context only.

Warning

Must not read or write any static that startup has yet to initialise – at this point they hold whatever SRAM held.

See also

Default_Handler()

Since

0.1.0

Definition at line 320 of file system_init.c.

References internal_enable_branch_predictor(), internal_enable_dcache(), internal_enable_div0_trap(), internal_enable_fault_handlers(), internal_enable_fpu(), internal_enable_fpu_lazy_stack(), internal_enable_icache(), internal_set_priority_grouping(), internal_set_vtor(), k_ra8_ok, ra8_boot_disable_irq(), ra8_mpu_apply_boot_map(), and ra8_trustzone_init().

Variable Documentation

g_ra8_ls_stack_top

uint32_t g_ra8_ls_stack_top

extern

g_ra8_vector_table_start

const uint32_t g_ra8_vector_table_start[]

extern

Definition at line 294 of file vector_table.c.