system_init.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_boot_entry.h"
#include "ra8_boot_intrinsics.h"
#include "ra8_cache.h"
#include "trustzone_init.h"
 
extern const uint32_t g_ra8_vector_table_start[];
 
/* =============================================================================
 * Core / SCB / NVIC register addresses (direct, no CMSIS dep)
 * =============================================================================
 */
 
typedef enum : uintptr_t {
  k_ra8_scb_vtor_addr  = 0xE000ED08UL, 
  k_ra8_scb_ccr_addr   = 0xE000ED14UL, 
  k_ra8_scb_shcsr_addr = 0xE000ED24UL, 
  k_ra8_scb_cpacr_addr = 0xE000ED88UL, 
  k_ra8_scb_nsacr_addr = 0xE000ED8CUL, 
  k_ra8_scb_iciallu    = 0xE000EF50UL, 
  k_ra8_scb_dciallu    = 0xE000EF58UL, 
  k_ra8_scb_csselr     = 0xE000ED84UL, 
  k_ra8_scb_ccsidr     = 0xE000ED80UL, 
  k_ra8_scb_dcisw      = 0xE000EF60UL, 
  k_ra8_fpu_fpccr_addr = 0xE000EF34UL, 
  k_ra8_nvic_aircr     = 0xE000ED0CUL, 
  k_ra8_mpu_type_addr  = 0xE000ED90UL, 
  k_ra8_mpu_ctrl_addr  = 0xE000ED94UL, 
  k_ra8_mpu_rnr_addr   = 0xE000ED98UL, 
  k_ra8_mpu_rbar_addr  = 0xE000ED9CUL, 
  k_ra8_mpu_rlar_addr  = 0xE000EDA0UL, 
  k_ra8_mpu_mair0_addr = 0xE000EDC0UL, 
  k_ra8_mpu_mair1_addr = 0xE000EDC4UL, 
} ra8_core_addr_t;
 
extern uint32_t g_ra8_ls_stack_top; /* from vector_table.c / linker. */
 
/* =============================================================================
 * Core init steps
 * =============================================================================
 */

static void internal_set_vtor(void)
{
  /* Vector table sits at the start of the .vectors section, which
   * the linker pins to the start of MRAM (`0x02000000`). The SCB
   * VTOR register stores the absolute address. */
  ra8_boot_write32(k_ra8_scb_vtor_addr, (uint32_t)(uintptr_t)g_ra8_vector_table_start);
}

static void internal_enable_fpu(void)
{
  enum : uint32_t {
    k_ra8_cpacr_cp10_cp11_full_access = 0x00F00000UL, 
  };
  uint32_t cpacr = ra8_boot_read32(k_ra8_scb_cpacr_addr);
  cpacr |= k_ra8_cpacr_cp10_cp11_full_access;
  ra8_boot_write32(k_ra8_scb_cpacr_addr, cpacr);
  ra8_boot_dsb();
  ra8_boot_isb();
}

static void internal_enable_fpu_lazy_stack(void)
{
  enum : uint32_t {
    k_ra8_fpccr_lspen = 1UL << 30, 
    k_ra8_fpccr_aspen = 1UL << 31, 
  };
  uint32_t fpccr = ra8_boot_read32(k_ra8_fpu_fpccr_addr);
  fpccr |= k_ra8_fpccr_lspen | k_ra8_fpccr_aspen;
  ra8_boot_write32(k_ra8_fpu_fpccr_addr, fpccr);
}

static void internal_enable_icache(void)
{
  /* Invalidate, then set CCR.IC. */
  ra8_boot_dsb();
  ra8_boot_write32(k_ra8_scb_iciallu, 0U);
  ra8_boot_dsb();
  ra8_boot_isb();
 
  enum : uint32_t { k_ra8_ccr_ic = 1UL << 17  };
  uint32_t ccr = ra8_boot_read32(k_ra8_scb_ccr_addr);
  ccr |= k_ra8_ccr_ic;
  ra8_boot_write32(k_ra8_scb_ccr_addr, ccr);
  ra8_boot_dsb();
  ra8_boot_isb();
}

static void internal_enable_dcache(void)
{
  /* Architectural ARMv8-M set/way invalidate of the whole D-cache,
   * driven by CCSIDR (implemented in libs/ra8_hal ra8_cache). */
  ra8_cache_dcache_invalidate_all();
  enum : uint32_t { k_ra8_ccr_dc = 1UL << 16  };
  uint32_t ccr = ra8_boot_read32(k_ra8_scb_ccr_addr);
  ccr |= k_ra8_ccr_dc;
  ra8_boot_write32(k_ra8_scb_ccr_addr, ccr);
  ra8_boot_dsb();
  ra8_boot_isb();
}

static void internal_enable_branch_predictor(void)
{
  enum : uint32_t { k_ra8_ccr_bp = 1UL << 18  };
  uint32_t ccr = ra8_boot_read32(k_ra8_scb_ccr_addr);
  ccr |= k_ra8_ccr_bp;
  ra8_boot_write32(k_ra8_scb_ccr_addr, ccr);
  ra8_boot_dsb();
  ra8_boot_isb();
}

RA8_INTERNAL static void internal_enable_fault_handlers(void)
{
  /* ARMv8-M SCB->SHCSR: MEMFAULTENA[16], BUSFAULTENA[17], USGFAULTENA[18],
   * SECUREFAULTENA[19] take MemManage/BusFault/UsageFault/SecureFault to
   * their own handlers instead of escalating to HardFault, so
   * ra8_exception_report sees the real class. SECUREFAULTENA is a
   * Secure-bank bit (RES0 from NS); this boot executes in the Secure
   * state, see the function contract for the scoping rationale. */
  enum : uint32_t {
    k_ra8_shcsr_memfaultena    = 1UL << 16, 
    k_ra8_shcsr_busfaultena    = 1UL << 17, 
    k_ra8_shcsr_usgfaultena    = 1UL << 18, 
    k_ra8_shcsr_securefaultena = 1UL << 19, 
  };
  uint32_t shcsr = ra8_boot_read32(k_ra8_scb_shcsr_addr);
  shcsr |= k_ra8_shcsr_memfaultena | k_ra8_shcsr_busfaultena | k_ra8_shcsr_usgfaultena |
           k_ra8_shcsr_securefaultena;
  ra8_boot_write32(k_ra8_scb_shcsr_addr, shcsr);
  ra8_boot_dsb();
  ra8_boot_isb();
}

RA8_INTERNAL static void internal_enable_div0_trap(void)
{
  /* ARMv8-M SCB->CCR: DIV_0_TRP[4] promotes SDIV/UDIV-by-zero from
   * "quotient reads as 0" to a UsageFault with CFSR.DIVBYZERO set.
   * UNALIGN_TRP[3] stays 0 -- see the function contract for evidence. */
  enum : uint32_t {
    k_ra8_ccr_div_0_trp = 1UL << 4, 
  };
  uint32_t ccr = ra8_boot_read32(k_ra8_scb_ccr_addr);
  ccr |= k_ra8_ccr_div_0_trp;
  ra8_boot_write32(k_ra8_scb_ccr_addr, ccr);
  ra8_boot_dsb();
  ra8_boot_isb();
}

static void internal_set_priority_grouping(void)
{
  enum : uint32_t {
    k_ra8_aircr_vectkey    = 0x05FA0000UL, 
    k_ra8_aircr_prigroup_4 = 0x00000300UL, 
  };
  ra8_boot_write32(k_ra8_nvic_aircr, k_ra8_aircr_vectkey | k_ra8_aircr_prigroup_4);
}

/* RBAR attribute bits[4:0] = { SH[4:3], AP[2:1], XN[0] }. AP: 0b01<<1 = RW
 * any-privilege, 0b11<<1 = RO any-privilege. The memory TYPE is NOT here --
 * it is the RLAR AttrIndx (see internal_mpu_set_region). */
enum : uint32_t {
  k_ra8_rbar_attr_ro_x  = 0x06U,    
  k_ra8_rbar_attr_rw_xn = 0x03U,    
  k_ra8_mpu_rlar_enable = 1UL << 0, 
};
 
/* RLAR AttrIndx (bits[3:1]) selects which MAIR byte sets the region's memory
 * type. The old code tried to encode "device" in RBAR (k_ra8_rbar_attr_device_rw
 * = 0x23), which both spilled bit5 into the base address and left every RLAR at
 * AttrIndx 0 = MAIR0[0] = Normal cacheable -- so peripheral MMIO was mapped
 * cacheable. The type must be selected here instead. */
enum : uint32_t {
  k_ra8_mpu_rlar_attridx_shift   = 1U, 
  k_ra8_mpu_attridx_normal_wbwa  = 0U, 
  k_ra8_mpu_attridx_noncacheable = 1U, 
  k_ra8_mpu_attridx_device       = 2U, 
};
 
/* Region base and limit addresses. RLAR limits are <region-end> minus
 * the ARMv8-M 32-byte region quantum, OR-ed with the enable bit at write time. */
enum : uint32_t {
  k_ra8_mpu_mram_base   = 0x02000000UL, 
  k_ra8_mpu_mram_limit  = 0x020FFFE0UL, 
  k_ra8_mpu_sram_base   = 0x22000000UL, 
  k_ra8_mpu_sram_limit  = 0x220FFFE0UL, 
  k_ra8_mpu_shram_base  = 0x22100000UL, 
  k_ra8_mpu_shram_limit = 0x2219FFE0UL, 
  k_ra8_mpu_sdram_base  = 0x68000000UL, 
  k_ra8_mpu_sdram_limit = 0x6BFFFFE0UL, 
  k_ra8_mpu_peri_base   = 0x40000000UL, 
  k_ra8_mpu_peri_limit  = 0x47FFFFE0UL, 
};

static void internal_mpu_set_region(uint32_t region,
                                    uint32_t base_attr,
                                    uint32_t limit_enable,
                                    uint32_t attr_idx)
{
  ra8_boot_write32(k_ra8_mpu_rnr_addr, region);
  ra8_boot_write32(k_ra8_mpu_rbar_addr, base_attr);
  ra8_boot_write32(k_ra8_mpu_rlar_addr, limit_enable | (attr_idx << k_ra8_mpu_rlar_attridx_shift));
}

static void internal_mpu_init(void)
{
  enum : uint32_t {
    k_ra8_mpu_ctrl_enable     = 1UL << 0,     
    k_ra8_mpu_ctrl_privdefena = 1UL << 2,     
    k_ra8_mair0_default       = 0x000444FFUL, 
  };
 
  /* MAIR0: idx0 = Normal WB/WA, idx1 = Normal non-cacheable, idx2 = Device-nGnRE. */
  ra8_boot_write32(k_ra8_mpu_mair0_addr, k_ra8_mair0_default);
  ra8_boot_write32(k_ra8_mpu_mair1_addr, 0U);
 
  /* Code = RO + executable cacheable; RAM = RW/NX cacheable; peripherals =
   * Device-nGnRE (NOT cacheable -- the AttrIndx selects the type). */
  internal_mpu_set_region(0U,
                          (k_ra8_mpu_mram_base | k_ra8_rbar_attr_ro_x),
                          (k_ra8_mpu_mram_limit | k_ra8_mpu_rlar_enable),
                          k_ra8_mpu_attridx_normal_wbwa);
  internal_mpu_set_region(1U,
                          (k_ra8_mpu_sram_base | k_ra8_rbar_attr_rw_xn),
                          (k_ra8_mpu_sram_limit | k_ra8_mpu_rlar_enable),
                          k_ra8_mpu_attridx_normal_wbwa);
  internal_mpu_set_region(2U,
                          (k_ra8_mpu_sdram_base | k_ra8_rbar_attr_rw_xn),
                          (k_ra8_mpu_sdram_limit | k_ra8_mpu_rlar_enable),
                          k_ra8_mpu_attridx_normal_wbwa);
  internal_mpu_set_region(3U,
                          (k_ra8_mpu_peri_base | k_ra8_rbar_attr_rw_xn),
                          (k_ra8_mpu_peri_limit | k_ra8_mpu_rlar_enable),
                          k_ra8_mpu_attridx_device);
  /* Shared M85<->M33 SRAM bank: Normal NON-cacheable so cross-core hand-offs
   * (mailbox at 0x22100000, CPU1 RAM) stay coherent with the M85 D-cache on. */
  internal_mpu_set_region(4U,
                          (k_ra8_mpu_shram_base | k_ra8_rbar_attr_rw_xn),
                          (k_ra8_mpu_shram_limit | k_ra8_mpu_rlar_enable),
                          k_ra8_mpu_attridx_noncacheable);
 
  /* Enable MPU with PRIVDEFENA so unclassified privileged accesses
   * still succeed through the default system memory map. */
  ra8_boot_dsb();
  ra8_boot_write32(k_ra8_mpu_ctrl_addr, k_ra8_mpu_ctrl_enable | k_ra8_mpu_ctrl_privdefena);
  ra8_boot_dsb();
  ra8_boot_isb();
}
 
/* =============================================================================
 * Public entry point
 * =============================================================================
 *
 * Called from `Reset_Handler` before the .data copy and .bss zero.
 * Must therefore not touch any global variables -- everything here
 * runs on the stack and writes to CPU / SCB memory only.
 */
 
void SystemInit(void)
{
  /* Mask global IRQs so the application gets a deterministic init
   * window. main() must call ``ra8_isr_globals_enable`` once every
   * driver / handler is wired up before any IRQ source can fire. */
  ra8_boot_disable_irq();
 
  internal_set_vtor();
  internal_enable_fpu();
  internal_enable_fpu_lazy_stack();
  /* Always-on fault diagnostics: take MemManage/BusFault/UsageFault/
   * SecureFault to their own decoded handlers and trap divide-by-zero
   * as a UsageFault (independent of the cache / MPU build flag). */
  internal_enable_fault_handlers();
  internal_enable_div0_trap();
#ifdef RA8_BOOT_ENABLE_CACHE_MPU
  /* T4-06: MPU memory-attribute map FIRST (so the D-cache sees Device-nGnRE
   * MMIO and the non-cacheable shared SRAM, not Normal cacheable), then the
   * caches. Each *_enable does its own architectural invalidate before setting
   * CCR. Region 4 (non-cacheable shared SRAM) keeps M85<->M33 hand-offs
   * coherent with no software maintenance. */
  internal_mpu_init();
  internal_enable_icache();
  internal_enable_dcache();
  internal_enable_branch_predictor();
#else
  /* Default OFF: caches + MPU stay disabled -- no behaviour change. */
  (void)internal_enable_icache;
  (void)internal_enable_dcache;
  (void)internal_enable_branch_predictor;
  (void)internal_mpu_init;
#endif
  (void)ra8_trustzone_init; /* TrustZone has its own gate (RA8_TRUSTZONE_ENABLE). */
  internal_set_priority_grouping();
}