21typedef enum : uintptr_t {
34 volatile uint32_t
RNR;
48typedef enum : uint32_t {
53 "r_mpu_regs_t size must match k_ra8_mpu_regs_block_size");
55typedef enum : uint32_t {
61typedef enum : uint32_t {
66typedef enum : uint32_t {
75typedef enum : uint32_t {
@ k_ra8_mpu_rlar_attridx_shift
RA8 MPU rlar attridx shift.
@ k_ra8_mpu_regs_block_size
RA8 MPU registers block size.
@ k_ra8_mpu_rbar_ap_mask
RA8 MPU rbar ap mask.
@ k_ra8_mpu_rbar_base_mask
RA8 MPU rbar base mask.
@ k_ra8_mpu_rbar_sh_mask
RA8 MPU rbar sh mask.
@ k_ra8_mpu_rbar_xn_mask
RA8 MPU rbar xn mask.
@ k_ra8_mpu_rbar_sh_shift
RA8 MPU rbar sh shift.
@ k_ra8_mpu_rbar_ap_shift
RA8 MPU rbar ap shift.
@ k_ra8_mpu_ctrl_enable
RA8 MPU control enable.
@ k_ra8_mpu_ctrl_hfnmiena
RA8 MPU control hfnmiena.
@ k_ra8_mpu_ctrl_privdefena
RA8 MPU control privdefena.
static volatile r_mpu_regs_t * ra8_mpu_regs(void)
Accessor for the architectural Cortex-M85 MPU register block.
@ k_ra8_mpu_rlar_limit_mask
RA8 MPU rlar limit mask.
@ k_ra8_mpu_rlar_en_mask
RA8 MPU rlar en mask.
@ k_ra8_mpu_rlar_attridx_mask
RA8 MPU rlar attridx mask.
@ k_ra8_mpu_type_dregion_shift
RA8 MPU type dregion shift.
@ k_ra8_mpu_type_dregion_mask
RA8 MPU type dregion mask.
@ k_ra8_mpu_core_base_addr
RA8 MPU core base address.
@ k_ra8_mpu_spmon_base_addr
RA8 MPU spmon base address.
@ k_ra8_mpu_mmpu_base_addr
RA8 MPU mmpu base address.
Architectural Cortex-M85 MPU register block.
volatile uint32_t RBAR_A1
RBAR_A1 register.
volatile uint32_t RBAR_A3
RBAR_A3 register.
volatile uint32_t RLAR_A2
RLAR_A2 register.
volatile uint32_t reserved0
Reserved.
volatile uint32_t RBAR
RBAR register.
volatile uint32_t RBAR_A2
RBAR_A2 register.
volatile uint32_t MAIR0
MAIR0 register.
volatile uint32_t RNR
RNR register.
volatile uint32_t RLAR_A1
RLAR_A1 register.
volatile uint32_t MAIR1
MAIR1 register.
volatile uint32_t RLAR
RLAR register.
volatile uint32_t TYPE
TYPE register.
volatile uint32_t RLAR_A3
RLAR_A3 register.
volatile uint32_t CTRL
CTRL register.