ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_mpu_regs.h
Go to the documentation of this file.
1
11
12#pragma once
13
14#ifdef __cplusplus
15extern "C" {
16#endif
17
18#include <stddef.h>
19#include <stdint.h>
20
21typedef enum : uintptr_t {
22 k_ra8_mpu_core_base_addr = 0xE000ED90UL,
23 k_ra8_mpu_mmpu_base_addr = 0x40000000UL,
26
31typedef struct {
32 volatile uint32_t TYPE;
33 volatile uint32_t CTRL;
34 volatile uint32_t RNR;
35 volatile uint32_t RBAR;
36 volatile uint32_t RLAR;
37 volatile uint32_t RBAR_A1;
38 volatile uint32_t RLAR_A1;
39 volatile uint32_t RBAR_A2;
40 volatile uint32_t RLAR_A2;
41 volatile uint32_t RBAR_A3;
42 volatile uint32_t RLAR_A3;
43 volatile uint32_t reserved0;
44 volatile uint32_t MAIR0;
45 volatile uint32_t MAIR1;
47
48typedef enum : uint32_t {
51
52static_assert(sizeof(r_mpu_regs_t) == (size_t)k_ra8_mpu_regs_block_size,
53 "r_mpu_regs_t size must match k_ra8_mpu_regs_block_size");
54
55typedef enum : uint32_t {
56 k_ra8_mpu_ctrl_enable = (1UL << 0U),
60
61typedef enum : uint32_t {
65
74
75typedef enum : uint32_t {
76 k_ra8_mpu_rlar_en_mask = 0x00000001UL,
81
90static inline volatile r_mpu_regs_t* ra8_mpu_regs(void)
91{
92 return (volatile r_mpu_regs_t*)k_ra8_mpu_core_base_addr;
93}
94
95#ifdef __cplusplus
96}
97#endif
@ k_ra8_mpu_rlar_attridx_shift
RA8 MPU rlar attridx shift.
ra8_mpu_layout_t
@ k_ra8_mpu_regs_block_size
RA8 MPU registers block size.
ra8_mpu_rbar_bits_t
@ k_ra8_mpu_rbar_ap_mask
RA8 MPU rbar ap mask.
@ k_ra8_mpu_rbar_base_mask
RA8 MPU rbar base mask.
@ k_ra8_mpu_rbar_sh_mask
RA8 MPU rbar sh mask.
@ k_ra8_mpu_rbar_xn_mask
RA8 MPU rbar xn mask.
@ k_ra8_mpu_rbar_sh_shift
RA8 MPU rbar sh shift.
@ k_ra8_mpu_rbar_ap_shift
RA8 MPU rbar ap shift.
ra8_mpu_ctrl_bits_t
@ k_ra8_mpu_ctrl_enable
RA8 MPU control enable.
@ k_ra8_mpu_ctrl_hfnmiena
RA8 MPU control hfnmiena.
@ k_ra8_mpu_ctrl_privdefena
RA8 MPU control privdefena.
static volatile r_mpu_regs_t * ra8_mpu_regs(void)
Accessor for the architectural Cortex-M85 MPU register block.
ra8_mpu_rlar_bits_t
@ k_ra8_mpu_rlar_limit_mask
RA8 MPU rlar limit mask.
@ k_ra8_mpu_rlar_en_mask
RA8 MPU rlar en mask.
@ k_ra8_mpu_rlar_attridx_mask
RA8 MPU rlar attridx mask.
ra8_mpu_type_bits_t
@ k_ra8_mpu_type_dregion_shift
RA8 MPU type dregion shift.
@ k_ra8_mpu_type_dregion_mask
RA8 MPU type dregion mask.
ra8_mpu_addr_t
@ k_ra8_mpu_core_base_addr
RA8 MPU core base address.
@ k_ra8_mpu_spmon_base_addr
RA8 MPU spmon base address.
@ k_ra8_mpu_mmpu_base_addr
RA8 MPU mmpu base address.
Architectural Cortex-M85 MPU register block.
volatile uint32_t RBAR_A1
RBAR_A1 register.
volatile uint32_t RBAR_A3
RBAR_A3 register.
volatile uint32_t RLAR_A2
RLAR_A2 register.
volatile uint32_t reserved0
Reserved.
volatile uint32_t RBAR
RBAR register.
volatile uint32_t RBAR_A2
RBAR_A2 register.
volatile uint32_t MAIR0
MAIR0 register.
volatile uint32_t RNR
RNR register.
volatile uint32_t RLAR_A1
RLAR_A1 register.
volatile uint32_t MAIR1
MAIR1 register.
volatile uint32_t RLAR
RLAR register.
volatile uint32_t TYPE
TYPE register.
volatile uint32_t RLAR_A3
RLAR_A3 register.
volatile uint32_t CTRL
CTRL register.