cpu1_main.c File Reference

CPU1 (Cortex-M33 secondary core) autonomous counter image. More...

#include <stdint.h>
#include "dualcore_background.h"
#include "ra8_attributes.h"

Include dependency graph for cpu1_main.c:

Go to the source code of this file.

Functions
void	cpu1_reset_handler (void)
	CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.
static void	cpu1_main (void)
	CPU1 application: stamp signature, count autonomously, signal done.
static void	cpu1_fault_handler (void)
	CPU1 default fault handler: park the core.

Variables
uint32_t	g_ra8_ls_cpu1_stack_top
	CPU1 stack top (slot 0 of the M33 vector table).
uint32_t	g_ra8_ls_cpu1_data_start
	CPU1 .data run-region start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_data_end
	CPU1 .data run-region end.
uint32_t	g_ra8_ls_cpu1_data_load
	CPU1 .data load image (in MRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_start
	CPU1 .bss start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_end
	CPU1 .bss end.
const uintptr_t	g_cpu1_vector_table []

Detailed Description

CPU1 (Cortex-M33 secondary core) autonomous counter image.

Tag

[Ring 6 / APP] {World: NS}

This is the firmware that runs on the RA8D2's secondary core, the Cortex-M33. It is compiled as a wholly separate ELF (-mcpu=cortex-m33) and embedded into the M85 ELF as a .cpu1_image blob; the M85 releases this core at runtime via ra8_cpu1_release (HUM Ch 2.9.1 "CPU control registers").

Its job is intentionally tiny so the autonomous co-processor pattern is what stands out:

1. Stamp k_bg_m33_signature into the shared block so the M85 can prove the M33 came out of reset and is executing user code.
2. Increment counter in the shared block k_bg_target_count times. The M85 does nothing during this phase – it merely polls done.
3. Set done = 1 to signal completion.
4. Spin forever.

Note

The M33 deliberately does NOT call ra8_log. The ra8_emulator only echoes the primary core's ITM stream, so an M33 ra8_log line would be invisible in the fake. The M33's proof-of-life is the signature it writes and the counter it increments; the M85 reads and logs both on the M33's behalf, which is honest in both the emulator and on silicon.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file cpu1_main.c.

Function Documentation

cpu1_fault_handler()

void cpu1_fault_handler ( void )

static

CPU1 default fault handler: park the core.

Every M33 exception slot routes here. The core stops making forward progress; on hardware a watchdog (if enabled) eventually resets.

Returns

This function never returns.

Note

The core spins in place.

Precondition

A hardware fault or unhandled exception occurred.

Entered via the M33 exception entry path.

Postcondition

The M33 makes no further forward progress.

done stays 0 (or at whatever value it held at fault time).

Note

Shared default for all CPU1 exception vectors.

Since

0.1.0

Definition at line 161 of file cpu1_main.c.

cpu1_main()

void cpu1_main ( void )

static

CPU1 application: stamp signature, count autonomously, signal done.

Writes the boot signature so the M85 can confirm the M33 left reset, then increments the shared counter k_bg_target_count times independently of the M85. Once counting is complete it sets done = 1 and spins. The M85 does nothing during the count except poll done – the key teaching point of this example.

Returns

This function never returns.

Note

Control stays in the final spin loop.

Precondition

cpu1_reset_handler has initialised .data and .bss.

The shared block at k_bg_sram_base has been zeroed by the M85.

Postcondition

m33_sig holds k_bg_m33_signature.

counter equals k_bg_target_count and done equals 1.

Note

Single-threaded; runs in M33 thread mode with no RTOS.

Since

0.1.0

Definition at line 77 of file cpu1_main.c.

References dualcore_bg_t::counter, dualcore_bg_t::done, dualcore_bg(), k_bg_m33_signature, k_bg_target_count, dualcore_bg_t::m33_sig, and RA8_LOOP_BOUND.

cpu1_reset_handler()

void cpu1_reset_handler

(

void

)

CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.

The M33 boots with uninitialised RAM. Before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Definition at line 123 of file cpu1_main.c.

References cpu1_main(), g_ra8_ls_cpu1_bss_end, g_ra8_ls_cpu1_bss_start, g_ra8_ls_cpu1_data_end, g_ra8_ls_cpu1_data_load, g_ra8_ls_cpu1_data_start, and RA8_LOOP_BOUND_RUNTIME.

Variable Documentation

g_cpu1_vector_table

const uintptr_t g_cpu1_vector_table[]

Initial value:

                                     = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
}

Definition at line 182 of file cpu1_main.c.

g_ra8_ls_cpu1_bss_end

uint32_t g_ra8_ls_cpu1_bss_end

extern

CPU1 .bss end.

g_ra8_ls_cpu1_bss_start

uint32_t g_ra8_ls_cpu1_bss_start

extern

CPU1 .bss start (in SRAM_CPU1).

g_ra8_ls_cpu1_data_end

uint32_t g_ra8_ls_cpu1_data_end

extern

CPU1 .data run-region end.

g_ra8_ls_cpu1_data_load

uint32_t g_ra8_ls_cpu1_data_load

extern

CPU1 .data load image (in MRAM_CPU1).

g_ra8_ls_cpu1_data_start

uint32_t g_ra8_ls_cpu1_data_start

extern

CPU1 .data run-region start (in SRAM_CPU1).

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern

CPU1 stack top (slot 0 of the M33 vector table).