Prove CCR.DIV_0_TRP: a zero divisor must raise a decoded UsageFault. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_log.h"
#include "ra8_mstp.h"

Include dependency graph for main.c:

Enumerations
enum	fd_consts_t : uint32_t { k_fd_uart_baud = 115200U , k_fd_dividend = 100U , k_fd_divisor = 0U }
	Console + divide-test knobs (no magic numbers). More...
enum	fd_scb_addr_t : uintptr_t { k_fd_scb_ccr_addr = 0xE000ED14UL }
	ARMv8-M SCB register addresses this app reads. More...
enum	fd_ccr_bits_t : uint32_t { k_fd_ccr_div_0_trp = 1UL << 4 }
	CCR bits checked by the arming probe. More...

Functions
static void	internal_print (const uint8_t *msg, uint32_t len)
	Emit a byte run on the SCI8 console.
static void	internal_log_sink (void *ctx, uint8_t byte)
	ra8_log byte sink: forward every log byte to the SCI8 console.
static void	internal_panic_halt (const uint8_t *msg, uint32_t len)
	Print the fail banner and trap (ra8_emulator halts on the BKPT).
static void	internal_print_uint (uint32_t value)
	Print a small unsigned integer in decimal (quotient display).
static void	internal_setup_or_halt (void)
	Bring up clocks / MSTP + the SCI8 console; halt on failure.
void	main (void)
	The application entry point Reset_Handler hands control to.

Variables
static const uint8_t	s_msg_boot [] = "fault-div0: boot\r\n"
static const uint8_t	s_msg_fail [] = "fault-div0: FAIL init\r\n"
static const uint8_t	s_msg_armed [] = "fault-div0: trap armed\r\n"
static const uint8_t	s_msg_unarmed [] = "fault-div0: FAIL trap not armed\r\n"
static const uint8_t	s_msg_survived [] = "fault-div0: survived divide quotient="
static const uint8_t	s_msg_emu_tail [] = " (trap not modelled -- ra8_emulator)\r\n"
static volatile uint32_t	s_fd_dividend = (uint32_t)k_fd_dividend
	Volatile numerator so the divide executes at run time.
static volatile uint32_t	s_fd_divisor = (uint32_t)k_fd_divisor
	Volatile zero divisor – the UDIV of this value must trap.
volatile uint32_t	g_fd_quotient = 0U
	Quotient observed when the trap did NOT fire (emulator survival path).
volatile uint32_t	g_fd_heartbeat = 0U
	Bumps forever in the survival idle loop – liveness for probes.

Detailed Description

Prove CCR.DIV_0_TRP: a zero divisor must raise a decoded UsageFault.

Tag: [Ring 6 / APP] {World: S}

The shared boot (libs/ra8_board_ek_ra8d2/src/boot/system_init.c) sets SHCSR.USGFAULTENA and CCR.DIV_0_TRP, so an integer SDIV/UDIV by zero must no longer silently return 0 – it must raise a UsageFault that the per-app vector table's trampoline forwards into ra8_exception_report(). This app closes the loop on real silicon:

Bring up clocks + the SCI8 J-Link VCOM console, and register the console as the ra8_log byte sink so the fault handler's dump is visible on the bench (the default ITM path drops every byte in fault context; a registered sink does not).
Read back CCR and confirm DIV_0_TRP is set (proves the boot write landed) – fault-div0: trap armed.
Perform a guarded volatile u32 / 0.

On silicon the divide never completes: the CPU takes UsageFault, the decoded dump prints (exception=6, cfsr =33554432 – that is 0x02000000 = CFSR.DIVBYZERO – plus pc/lr/xpsr), and the handler parks at ra8_exception_halt_loop. The hil.conf gate scrapes that dump.

Note: Headless-emulator status. tools/ra8_emulator models this trap: a DIV_0_TRP-gated UDIV/SDIV seam takes the decoded UsageFault when (and only when) the firmware has armed CCR.DIV_0_TRP and the divisor is zero, so the emulator run reproduces the silicon dump headlessly (exception=6, cfsr =33554432). The survived divide branch below is therefore the on-silicon negative fallback – reached only if the trap ever fails to fire – not the fake's normal path. The bench has captured the real fault dump on silicon (tracker issue #191), so the app lives in hw_validated/hil/.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file main.c.

Enumeration Type Documentation

◆ fd_ccr_bits_t

enum fd_ccr_bits_t : uint32_t

CCR bits checked by the arming probe.

Enumerator
k_fd_ccr_div_0_trp	ARMv8-M CCR.DIV_0_TRP – divide-by-zero traps.

Definition at line 69 of file main.c.

◆ fd_consts_t

enum fd_consts_t : uint32_t

Console + divide-test knobs (no magic numbers).

Enumerator
k_fd_uart_baud	SCI8 J-Link VCOM console baud.
k_fd_dividend	Numerator for the guarded zero-divide.
k_fd_divisor	The zero divisor that must trap on silicon.

Definition at line 57 of file main.c.

◆ fd_scb_addr_t

enum fd_scb_addr_t : uintptr_t

ARMv8-M SCB register addresses this app reads.

Enumerator
k_fd_scb_ccr_addr	Configuration and Control Register.

Definition at line 64 of file main.c.

Function Documentation

◆ internal_log_sink()

void internal_log_sink	(	void *	ctx,
		uint8_t	byte )

static

ra8_log byte sink: forward every log byte to the SCI8 console.

The fault path (ra8_exception_report) logs through ra8_log, whose default ITM backend deliberately drops every byte in fault context (IPSR != 0). A registered byte sink bypasses that gate, so routing it at the console makes the decoded dump visible on the bench UART. The console write is polled (no IRQs needed), so it is safe from the fault handler.

Parameters

[in]	ctx	Unused opaque cookie (sink ABI).
[in]	byte	Log byte to emit.

Precondition: ra8_board_uart_console_init succeeded.; Registered via ra8_log_set_byte_sink.

Postcondition: The byte was pushed to the console (or dropped on error).; No other state modified.

Note: Callable from fault context (polled console write).

Since: 0.1.0

Definition at line 160 of file main.c.

References ra8_board_uart_console_write(), and RA8_INTERNAL.

Referenced by main(), and main().

◆ internal_panic_halt()

void internal_panic_halt	(	const uint8_t *	msg,
		uint32_t	len )

static

Print the fail banner and trap (ra8_emulator halts on the BKPT).

Mirrors the sibling apps' panic idiom: one negative banner the HIL gate can match, then a debugger-visible stop.

Parameters

[in]	msg	Banner bytes.
[in]	len	Banner length.

Precondition: The console is up (best effort – the write may be dropped).; Called only on an unrecoverable bring-up failure.

Postcondition: Never returns; CPU parks in a BKPT + WFI loop.; The negative banner was pushed to the console.

Note: Not thread-safe (terminal path).

Since: 0.1.0

Definition at line 180 of file main.c.

References internal_print(), and RA8_INTERNAL.

◆ internal_print()

void internal_print	(	const uint8_t *	msg,
		uint32_t	len )

static

Emit a byte run on the SCI8 console.

Thin wrapper discarding the write status: console loss is acceptable for a print helper, the HIL gate re-checks output.

Parameters

[in]	msg	Bytes to send (not NUL-inspected).
[in]	len	Number of bytes.

Precondition: msg points at len readable bytes.; ra8_board_uart_console_init succeeded.

Postcondition: len bytes were pushed to the console (or dropped on error).; No other state modified.

Note: Not thread-safe (single-threaded app).

Since: 0.1.0

Definition at line 134 of file main.c.

References ra8_board_uart_console_write(), and RA8_INTERNAL.

Referenced by internal_panic_halt(), internal_print_uint(), and main().

◆ internal_print_uint()

void internal_print_uint ( uint32_t value )

static

Print a small unsigned integer in decimal (quotient display).

Emits at most 10 digits; 0 prints as "0". Digits are pushed LSB-first into a local buffer, then emitted MSB-first.

Parameters

[in] value Value to print.

Precondition: The console is up.; value is any uint32 (full range supported).

Postcondition: The decimal text was pushed to the console.; No other state modified.

Note: Not thread-safe (single-threaded app).

Since: 0.1.0

< Decimal base.

< Max digits in a uint32 (4G).

Definition at line 202 of file main.c.

References internal_print(), and RA8_INTERNAL.

Referenced by main().

◆ internal_setup_or_halt()

void internal_setup_or_halt ( void )

static

Bring up clocks / MSTP + the SCI8 console; halt on failure.

Minimal bring-up: CGC, MSTP, console. No timers – the app needs no delays, only one divide.

Precondition: Running after Reset_Handler with .data/.bss initialised.; The J-Link OB VCOM bridge is on SCI8 PD02/PD03 (stock EK-RA8D2).

Postcondition: The console accepts writes at k_fd_uart_baud.; On any init failure the CPU is parked via internal_panic_halt.

Note: Not thread-safe; boot context only.

Since: 0.1.0

Definition at line 236 of file main.c.

References internal_panic_halt(), k_fd_uart_baud, k_ra8_ok, ra8_board_uart_console_init(), ra8_cgc_init(), RA8_INTERNAL, ra8_mstp_init(), and s_msg_fail.

◆ main()

void main ( void )

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has configured the clock tree and VTOR.

Postcondition: Control does not return; the image runs until reset or halt.; Any value the application wanted to report has been logged, not returned.

Note: Not thread-safe; single-threaded startup context only.

Warning: Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also: SystemInit()

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the playback loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the sweep loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.

Postcondition: On clean entry the kernel runs the worker thread once.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the kernel runs the worker thread forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition: Reset_Handler has copied .data + zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: CPUCLK0 is raised to the PLL1 target before the kernel starts.; On clean entry the SD card thread runs forever.; On any HAL init failure the function halts in __WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the iso-IN feed loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition: Boot init has completed.; The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition: Diagnostic counter latched, CPU parked in a halt loop.; Function never returns.

Note: Single-threaded entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.; On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.; On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition: The shelf scans on the panel; taps open books, browse, and read.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the cache globals are latched and g_pc_heartbeat advances.; On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the profile + blink loop.; On any HAL hard error LED2 latches ON.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; The shared board boot files installed the vector table.

Postcondition: The demo has run once and its verdict banner is streaming steadily.; The CPU idles re-emitting the banner (or halts after a fatal init error).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The page-count + render-hash banner is emitted; the CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The cal=OK / cal=SKIP result and the finger-free touchcal: ready sentinel are emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The open=OK touch banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Both USB controllers' clocks and pins come up before the kernel so the workers only deal with stack bring-up.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging and the clock tree, releases the Cortex-M33 (which then blinks LED1 via ra8_pcntr_set_output()), and idles. See the file header.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and is blinking LED1.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: The application links ra8_c6link and ESP-hosted generated codecs.; No hardware validation is inferred from this function.

Postcondition: No c6link operation is attempted.; No network or storage state is modified.

Note: Single-threaded compile fixture.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the cacheable-SRAM round-trip with the D-cache that SystemInit() enabled through ra8_cache_dcache_enable(), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU + RA8_BOOT_CACHE_VIA_HAL).

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + I-cache + D-cache via the ra8_cache HAL.

Postcondition: Exactly one banner (PASS or FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, releases the Cortex-M33 into the emitter, yields until it signals done, validates the blob the M33 built, then logs the PASS/FAIL verdict and the chapter count read back from the blob. See the file header for the offload narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 has built a RABOOK1 blob and the M85 has validated it.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the CPU heartbeats after epaper: PASS.; On any HAL error the console prints epaper: FAIL and the red LED latches on.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/toc/cover banner is emitted; CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The reader loop runs forever, redrawing on each tap.; A page-1 banner is emitted once after the first render.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The cover-size / framebuffer-CRC banner is emitted; CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The panel shows the reader screen and the input loop runs forever.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, arms the IPC0 wake and configures the LPM block, releases the Cortex-M33 into the reader, waits for the first held page, logs the page-0 verdict, then runs the #150 mode-switch cycle – parking in low-power WFI and waking on the M33's page-turn pokes – before logging the handoff verdict and parking for good. See the file header for the narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 has rendered + re-rendered the held page and the M85 is parked.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The boot banner is emitted; the reader loop services taps forever.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the timebase then measures forever.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the measure + blink loop forever.; On any HAL init failure the function halts in WFI.

Note: Never returns.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Arms the RIIC1 target and polls the dispatcher.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: The CPU stays in the dispatch poll loop forever.; On any fatal init error the CPU parks in riic_target_panic_halt.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the PASS banner is printed and the CPU loops in WFI.; On any failure the function prints a FAIL line and halts.

Note: Not thread-safe; single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the read + print loop forever.; On any HAL hard error LED2 latches ON and the loop exits.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the LIN commander then drives frames.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the LIN-frame + blink loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, "renders" page 0 into the shared mailbox, releases the Cortex-M33 into its hold loop, and parks the M85 in low-power WFI sleep. See the file header for the power-saving narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 owns the held page and the M85 is parked.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

The USB clock, pins, console, and the SD card all come up before the kernel so the worker only deals with USB stack bring-up.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit configured VTOR / FPU.

Postcondition: On clean bring-up the CPU stays in the poll loop.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler initialized static storage.; SystemInit configured VTOR, FPU, and priority grouping.

Postcondition: The startup banner is printed once.; Control enters ThreadX and never returns normally.

Note: The #707 freestanding contract is declared by ra8_boot_entry.h.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the PASS banner is printed and the CPU heartbeats forever.; On any failure LED2 latches ON and the CPU parks.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (MPU enabled, canonical boot map, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit installed the boot map via ra8_mpu_apply_boot_map().

Postcondition: Exactly one banner (PASS or a step-specific FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler initialised the C runtime; SystemInit ran.; The EK-RA8D2 J-Link OB VCOM console is attached for the banner.

Postcondition: The commit + rollback attempts have executed against extra-MRAM.; The verdict banner is emitted once per report cycle.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the wear-levelling + power-cycle-survival flow, and prints a single PASS/FAIL verdict.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the program/erase round-trip, and prints a single PASS/FAIL verdict.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then runs the full ra8_io VFS round-trip over the native-SDHI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the console and both stdio sinks, retargets the engine's stdio to the in-RAM capture sink, runs the two-backend swap, replays the RAM capture out of the UART, and prints a single PASS/FAIL verdict per abstraction before parking in an infinite loop.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition: A PASS or FAIL verdict line has been queued on SCI8 for each abstraction.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then writes + reads + compares one raw 512-byte block straight against ra8_sdcard. On success it prints the exact PASS banner; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The whoami PASS banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII + RSIP, then ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.

Postcondition: On clean entry the kernel runs the worker thread once.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition: The banner was printed exactly once.; Control passed to ThreadX and never came back.

Note: Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition: The banner and the resolved pin map were printed exactly once.; Control passed to ThreadX and never came back.

Note: Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and priority grouping.

Postcondition: The probe ran exactly once and printed its verdict.; The CPU stays in a slow heartbeat loop afterwards.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, the FPU and the priority grouping.

Postcondition: The banner was printed exactly once.; Control passed to ThreadX and never came back.

Note: Everything after tx_kernel_enter runs on ThreadX; the panic-halt below is reached only if the kernel refuses to start.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initializes and arms ADC_B, formats each successful channel sample without variadic I/O, emits the verdict, toggles LED1, and delays.

Precondition: Reset startup and SystemInit completed successfully.; The selected ADC channel matches the board analog connection.

Postcondition: Every PASS verdict follows a successful channel read.; Any read or LED failure leads to the terminal panic helper.

Note: Does not return during normal operation.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the PASS banner is emitted; otherwise a FAIL line is.; The CPU parks in WFI (observable on ra8_emulator until its budget).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33 (which then blinks LED1), and idles. See the file header for the teaching narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and is blinking LED1.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The IDCODE/checks PASS banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

See the file header for the full behaviour summary.

Precondition: SystemInit has enabled the caches + MPU (this build defines RA8_BOOT_ENABLE_CACHE_MPU).; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and the round-trip loop is running.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (cacheable SRAM, RO MRAM const, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches and MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU).

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + I-cache + D-cache (cache+MPU build).

Postcondition: Exactly one banner (PASS or a step-specific FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU and priority grouping.

Postcondition: The verdict banner is on SCI8 and the CPU parks.; The result globals hold the outcome for SWD probing.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Lights HOCO + PLL, then runs a 1 Hz blink.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the toggle loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

See file header for behaviour summary.

Precondition: Boot init has completed.; CPU1 is held in reset.

Postcondition: CPU1 released and the ping-pong loop running.; Function never returns.

Note: Single-threaded entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: Control passes to the active app, or to the ThreadX-hosted DFU device.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss; SystemInit ran.; The embedded image's first two words are a valid MSP + Thumb reset vector.

Postcondition: On success, control is at the image's reset vector in the SRAM run window.; On a failed run-target check, control parks in internal_dcr_panic_halt.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + caches via RA8_BOOT_ENABLE_CACHE_MPU.

Postcondition: Exactly one PASS/FAIL banner is emitted, then the core parks.; The core ends in WFI so ra8_emulator's idle-stop terminates the run.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initializes the demo, executes one comparison per period, increments the exported match or mismatch counter, and toggles the matching LED.

Precondition: Reset startup and SystemInit completed successfully.; DOC and the status LEDs are not owned by another context.

Postcondition: Every iteration increments exactly one HIL result counter.; LED1 represents matches and LED2 represents failures or mismatches.

Note: Does not return during normal operation.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clock tree, MSTP, ISR/ELC, and the VCOM console, programs a software-triggered DTC block copy, runs it with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + caches via RA8_BOOT_ENABLE_CACHE_MPU.

Postcondition: Exactly one PASS/FAIL banner is emitted, then the core parks.; The core ends in WFI so ra8_emulator's idle-stop terminates the run.

Note: Single-threaded; the completion IRQ is left masked and the result polled.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, zeros the shared control block, releases the Cortex-M33, waits for its boot signature, then yields while the M33 counts autonomously to k_bg_target_count. After the M33 sets done, the M85 reads the counter and logs the PASS/FAIL verdict.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has autonomously incremented the counter and set done.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33, confirms it booted, runs k_m85_demo_rounds narrated mailbox rounds, then drops into the idle heartbeat. See the file header for the teaching narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and the mailbox exchange is running.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Fires ELC software events once a second.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the trigger + blink loop.; On any HAL hard error LED2 latches ON.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The geometry-hash banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The framebuffer hash banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The bmp/gif framebuffer-CRC banner is emitted; CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The hit-test / nav result banner is emitted; the CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The nav-result banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The per-chapter page-count + render-hash banner is emitted; loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The svg-size / framebuffer-CRC banner is emitted; CPU loops in WFI.

Since: 0.1.0

Definition at line 249 of file main.c.

References g_fd_heartbeat, g_fd_quotient, internal_log_sink(), internal_panic_halt(), internal_print(), internal_print_uint(), internal_setup_or_halt(), k_fd_ccr_div_0_trp, k_fd_scb_ccr_addr, ra8_isr_globals_enable(), ra8_log_set_byte_sink(), s_fd_dividend, s_fd_divisor, s_msg_armed, s_msg_boot, s_msg_emu_tail, s_msg_survived, and s_msg_unarmed.

Variable Documentation

◆ g_fd_heartbeat

volatile uint32_t g_fd_heartbeat = 0U

Bumps forever in the survival idle loop – liveness for probes.

Note: Read externally only.

Since: 0.1.0

Definition at line 118 of file main.c.

Referenced by main().

◆ g_fd_quotient

volatile uint32_t g_fd_quotient = 0U

Quotient observed when the trap did NOT fire (emulator survival path).

0 by ARM default divide-by-zero semantics; exported volatile for headless probing.

Note: Read externally only (HIL / board emulator).

Since: 0.1.0

Definition at line 110 of file main.c.

Referenced by main().

◆ s_fd_dividend

volatile uint32_t s_fd_dividend = (uint32_t)k_fd_dividend

static

Volatile numerator so the divide executes at run time.

Volatile (and file-scope) so the compiler can neither constant-fold the division nor prove the divisor zero and elide / poison the code path.

Note: Written once at load; read once by main.

Warning: Do not mark const – the volatile load IS the test.

Since: 0.1.0

Definition at line 90 of file main.c.

Referenced by main().

◆ s_fd_divisor

volatile uint32_t s_fd_divisor = (uint32_t)k_fd_divisor

static

Volatile zero divisor – the UDIV of this value must trap.

See s_fd_dividend; same reasoning, opposite operand.

Note: Written once at load; read once by main.

Warning: Stays zero for the app's whole life.

Since: 0.1.0

Definition at line 100 of file main.c.

Referenced by main().

◆ s_msg_armed

const uint8_t s_msg_armed[] = "fault-div0: trap armed\r\n"

static

Definition at line 75 of file main.c.

Referenced by main().

◆ s_msg_boot

const uint8_t s_msg_boot[] = "fault-div0: boot\r\n"

static

Definition at line 73 of file main.c.

◆ s_msg_emu_tail

const uint8_t s_msg_emu_tail[] = " (trap not modelled -- ra8_emulator)\r\n"

static

Definition at line 78 of file main.c.

Referenced by main().

◆ s_msg_fail

const uint8_t s_msg_fail[] = "fault-div0: FAIL init\r\n"

static

Definition at line 74 of file main.c.

◆ s_msg_survived

const uint8_t s_msg_survived[] = "fault-div0: survived divide quotient="

static

Definition at line 77 of file main.c.

Referenced by main().

◆ s_msg_unarmed

const uint8_t s_msg_unarmed[] = "fault-div0: FAIL trap not armed\r\n"

static

Definition at line 76 of file main.c.

Referenced by main().

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ fd_ccr_bits_t

◆ fd_consts_t

◆ fd_scb_addr_t

Function Documentation

◆ internal_log_sink()

◆ internal_panic_halt()

◆ internal_print()

◆ internal_print_uint()

◆ internal_setup_or_halt()

◆ main()

Variable Documentation

◆ g_fd_heartbeat

◆ g_fd_quotient

◆ s_fd_dividend

◆ s_fd_divisor

◆ s_msg_armed

◆ s_msg_boot

◆ s_msg_emu_tail

◆ s_msg_fail

◆ s_msg_survived

◆ s_msg_unarmed