board_periph_eth.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_console.h"
#include "board_net.h"
#include "board_periph_block.h"
#include "emu_host_io_internal.h"
#include "ra8_etha_regs.h"
#include "ra8_ether_regs.h"
#include "ra8_rmac_regs.h"

typedef enum : uint64_t {
  k_eth_win_base = (uint64_t)k_ra8_mfwd_base_addr, 
  k_eth_win_span = 0xF000UL,                       
} eth_win_geom_t;

typedef enum : uint32_t {
  k_eth_desc_bytes    = 8U,          
  k_eth_desc_dt_byte  = 2U,          
  k_eth_desc_dt_shift = 4U,          
  k_eth_desc_dt_lo    = 0x0FU,       
  k_eth_desc_ds_byte1 = 1U,          
  k_eth_desc_ds_hi    = 0x0FU,       
  k_eth_desc_ds_keep  = 0xF0U,       
  k_eth_desc_ptr_off  = 4U,          
  k_eth_reg32_bytes   = 4U,          
  k_eth_byte_mask     = 0xFFU,       
  k_eth_shift_byte    = 8U,          
  k_eth_gwarirm_ariog = 1UL << 0U,   
  k_eth_gwarirm_arr   = 1UL << 1U,   
  k_eth_mpsm_mff      = 1UL << 2U,   
  k_eth_rmac_off_mrfc = 0x0438U,     
  k_eth_frame_max     = 1536U,       
  k_eth_ring_walk_max = 64U,         
  k_eth_rx_inject_max = 8U,          
  k_eth_console_cap   = 48U,         
  k_eth_queue_none    = 0xFFFFFFFFU, 
} eth_model_const_t;

typedef enum : uint16_t {
  k_eth_phy_reg_bmcr    = 0U,      
  k_eth_phy_reg_bmsr    = 1U,      
  k_eth_phy_reg_anlpar  = 5U,      
  k_eth_phy_reg_count   = 32U,     
  k_eth_phy_bmcr_seed   = 0x3100U, 
  k_eth_phy_bmsr_seed   = 0x782DU, 
  k_eth_phy_anlpar_seed = 0x01E1U, 
  k_eth_phy_bmcr_reset  = 0x8000U, 
  k_eth_phy_bmcr_anrst  = 0x0200U, 
} eth_phy_reg_t;

typedef enum : uint32_t {
  k_eth_block_order = 58U, 
} eth_order_t;

typedef struct {
  uint8_t  win[k_eth_win_span];      
  uint32_t linkfix_base;             
  uint32_t rx_queue;                 
  uint16_t phy[k_eth_phy_reg_count]; 
  uint32_t tx_frames;                
  uint32_t rx_frames;                
} eth_state_t;

static eth_state_t s_eth;
 
/* ------------------------------------------------------------------------- */
/* Flat-shadow + descriptor byte helpers. */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static uint64_t internal_eth_shadow_read(uint64_t off, unsigned size)
{
  uint64_t v = 0U;
  for (unsigned i = 0U; (i < size) && ((off + (uint64_t)i) < (uint64_t)k_eth_win_span); ++i) {
    v |= (uint64_t)s_eth.win[off + (uint64_t)i] << (k_eth_shift_byte * i);
  }
  return v;
}

RA8_INTERNAL static void internal_eth_shadow_write(uint64_t off, unsigned size, uint64_t value)
{
  for (unsigned i = 0U; (i < size) && ((off + (uint64_t)i) < (uint64_t)k_eth_win_span); ++i) {
    s_eth.win[off + (uint64_t)i] = (uint8_t)(value >> (k_eth_shift_byte * i));
  }
}

RA8_INTERNAL static uint32_t internal_eth_shadow_u32(uint64_t off)
{
  return (uint32_t)internal_eth_shadow_read(off, k_eth_reg32_bytes);
}

RA8_INTERNAL static uint32_t internal_eth_bytes_u32(const uint8_t* p)
{
  uint32_t v = 0U;
  for (unsigned i = 0U; i < k_eth_reg32_bytes; ++i) {
    v |= (uint32_t)p[i] << (k_eth_shift_byte * i);
  }
  return v;
}

RA8_INTERNAL static void internal_eth_desc_read(uc_engine* uc, uint32_t addr, uint8_t* out8)
{
  (void)emu_mem_read(uc, (uint64_t)addr, out8, (size_t)k_eth_desc_bytes);
}

RA8_INTERNAL static uint32_t internal_eth_desc_dt(const uint8_t* d8)
{
  return ((uint32_t)d8[k_eth_desc_dt_byte] >> k_eth_desc_dt_shift) & (uint32_t)k_eth_desc_dt_lo;
}

RA8_INTERNAL static uint32_t internal_eth_desc_ds(const uint8_t* d8)
{
  return (uint32_t)d8[0] |
         (((uint32_t)d8[k_eth_desc_ds_byte1] & (uint32_t)k_eth_desc_ds_hi) << k_eth_shift_byte);
}

RA8_INTERNAL static uint32_t internal_eth_desc_ptr(const uint8_t* d8)
{
  return internal_eth_bytes_u32(&d8[k_eth_desc_ptr_off]);
}

RA8_INTERNAL static void internal_eth_desc_set_dt(uc_engine* uc, uint32_t addr, uint32_t dt)
{
  uint8_t b = 0U;
  (void)emu_mem_read(uc, (uint64_t)addr + (uint64_t)k_eth_desc_dt_byte, &b, 1U);
  b = (uint8_t)((b & (uint8_t)k_eth_desc_dt_lo) |
                (uint8_t)((dt & (uint32_t)k_eth_desc_dt_lo) << k_eth_desc_dt_shift));
  (void)emu_mem_write(uc, (uint64_t)addr + (uint64_t)k_eth_desc_dt_byte, &b, 1U);
}

RA8_INTERNAL static void internal_eth_desc_set_ds(uc_engine* uc, uint32_t addr, uint32_t ds)
{
  const uint8_t lo = (uint8_t)(ds & (uint32_t)k_eth_byte_mask);
  uint8_t       hi = 0U;
  (void)emu_mem_read(uc, (uint64_t)addr + (uint64_t)k_eth_desc_ds_byte1, &hi, 1U);
  hi = (uint8_t)((hi & (uint8_t)k_eth_desc_ds_keep) |
                 (uint8_t)((ds >> k_eth_shift_byte) & (uint32_t)k_eth_desc_ds_hi));
  (void)emu_mem_write(uc, (uint64_t)addr, &lo, 1U);
  (void)emu_mem_write(uc, (uint64_t)addr + (uint64_t)k_eth_desc_ds_byte1, &hi, 1U);
}
 
/* ------------------------------------------------------------------------- */
/* Sub-block address predicates (bases + offsets from the register headers). */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static bool internal_eth_is_etha_reg(uint64_t addr, uint64_t off)
{
  return (addr == (uint64_t)k_ra8_etha0_base_addr + off) ||
         (addr == (uint64_t)k_ra8_etha1_base_addr + off);
}

RA8_INTERNAL static bool internal_eth_is_rmac_reg(uint64_t addr, uint64_t off)
{
  return (addr == (uint64_t)k_ra8_rmac0_base_addr + off) ||
         (addr == (uint64_t)k_ra8_rmac1_base_addr + off);
}

RA8_INTERNAL static bool internal_eth_is_gwdcc(uint64_t addr, uint32_t* queue)
{
  const uint64_t base = (uint64_t)k_ra8_gwca0_base_addr + (uint64_t)k_ra8_gwca_off_gwdcc_base;
  const uint64_t top  = base + ((uint64_t)k_eth_phy_reg_count * (uint64_t)k_eth_reg32_bytes);
  if ((addr < base) || (addr >= top) || (((addr - base) % (uint64_t)k_eth_reg32_bytes) != 0U)) {
    return false;
  }
  *queue = (uint32_t)((addr - base) / (uint64_t)k_eth_reg32_bytes);
  return true;
}
 
/* ------------------------------------------------------------------------- */
/* PHY (MDIO) model. */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static uint16_t internal_eth_phy_read(uint32_t reg)
{
  if (reg >= (uint32_t)k_eth_phy_reg_count) {
    return 0U;
  }
  return s_eth.phy[reg];
}

RA8_INTERNAL static void internal_eth_phy_write(uint32_t reg, uint16_t value)
{
  if (reg >= (uint32_t)k_eth_phy_reg_count) {
    return;
  }
  if (reg == (uint32_t)k_eth_phy_reg_bmcr) {
    value = (uint16_t)(value & (uint16_t)~(k_eth_phy_bmcr_reset | k_eth_phy_bmcr_anrst));
  }
  s_eth.phy[reg] = value;
}

RA8_INTERNAL static void internal_eth_mpsm_exec(uint64_t mpsm_off, uint32_t value)
{
  const uint32_t pop =
    (value >> (uint32_t)k_ra8_rmac_shift_mpsm_pop) & (uint32_t)k_ra8_rmac_mask_mpsm_op;
  const uint32_t pra =
    (value >> (uint32_t)k_ra8_rmac_shift_mpsm_pra) & (uint32_t)k_ra8_rmac_mask_mpsm_phy_reg;
  const uint32_t prd =
    (value >> (uint32_t)k_ra8_rmac_shift_mpsm_prd) & (uint32_t)k_ra8_rmac_mask_mpsm_data;
  const bool c45 = (value & (uint32_t)k_eth_mpsm_mff) != 0U;
  uint32_t   out = value & ~(uint32_t)k_ra8_rmac_mpsm_psme; /* PSME self-clears. */
  if (!c45 && (pop == (uint32_t)k_ra8_rmac_mdio_op_c22_read)) {
    out = ((uint32_t)internal_eth_phy_read(pra) & (uint32_t)k_ra8_rmac_mask_mpsm_data)
          << (uint32_t)k_ra8_rmac_shift_mpsm_prd;
  } else if (!c45 && (pop == (uint32_t)k_ra8_rmac_mdio_op_c22_write)) {
    internal_eth_phy_write(pra, (uint16_t)prd);
  }
  internal_eth_shadow_write(mpsm_off, k_eth_reg32_bytes, out);
}
 
/* ------------------------------------------------------------------------- */
/* TX descriptor DMA (GWTRC kick -> peer). */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static void internal_eth_tx_kick_queue(uc_engine* uc, uint32_t queue)
{
  if (s_eth.linkfix_base == 0U) {
    return;
  }
  uint8_t        lf[k_eth_desc_bytes];
  const uint32_t lf_addr = s_eth.linkfix_base + (queue * (uint32_t)k_eth_desc_bytes);
  internal_eth_desc_read(uc, lf_addr, lf);
  const uint32_t chain = internal_eth_desc_ptr(lf);
  if (chain == 0U) {
    return;
  }
  uint8_t head[k_eth_desc_bytes];
  internal_eth_desc_read(uc, chain, head);
  if (internal_eth_desc_dt(head) != (uint32_t)k_ra8_gwdcc_dt_fsingle) {
    return; /* multi-fragment / empty head is unmodelled here -- honest no-op. */
  }
  const uint32_t len = internal_eth_desc_ds(head);
  const uint32_t buf = internal_eth_desc_ptr(head);
  if ((len == 0U) || (len > (uint32_t)k_eth_frame_max) || (buf == 0U)) {
    return;
  }
  uint8_t frame[k_eth_frame_max];
  if (emu_mem_read(uc, (uint64_t)buf, frame, (size_t)len) != UC_ERR_OK) {
    return;
  }
  board_net_on_tx(frame, len);
  internal_eth_desc_set_dt(uc, chain, (uint32_t)k_ra8_gwdcc_dt_fempty);
  s_eth.tx_frames++;
  char ln[k_eth_console_cap];
  (void)snprintf(ln, sizeof(ln), "ETH tx q%u %uB", (unsigned)queue, (unsigned)len);
  board_console_push(k_board_console_ch_net, ln);
}

RA8_INTERNAL static void internal_eth_gwtrc_kick(uc_engine* uc, uint32_t bits, uint32_t base_queue)
{
  for (uint32_t i = 0U; i < (uint32_t)k_eth_phy_reg_count; ++i) {
    if ((bits & (1UL << i)) != 0U) {
      internal_eth_tx_kick_queue(uc, base_queue + i);
    }
  }
}
 
/* ------------------------------------------------------------------------- */
/* RX descriptor DMA (peer -> ring, once per tick). */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static bool
internal_eth_rx_find_slot(uc_engine* uc, uint32_t chain, uint32_t* out_slot)
{
  uint32_t cur = chain;
  for (uint32_t i = 0U; i < (uint32_t)k_eth_ring_walk_max; ++i) {
    uint8_t d8[k_eth_desc_bytes];
    internal_eth_desc_read(uc, cur, d8);
    const uint32_t dt = internal_eth_desc_dt(d8);
    if (dt == (uint32_t)k_ra8_gwdcc_dt_fempty) {
      *out_slot = cur;
      return true;
    }
    if ((dt == (uint32_t)k_ra8_gwdcc_dt_link) || (dt == (uint32_t)k_ra8_gwdcc_dt_linkfix)) {
      const uint32_t next = internal_eth_desc_ptr(d8);
      if ((next == 0U) || (next == cur)) {
        return false;
      }
      cur = next;
    } else {
      cur += (uint32_t)k_eth_desc_bytes;
    }
  }
  return false;
}

RA8_INTERNAL static void internal_eth_rx_drain_peer(uc_engine* uc, uint32_t chain)
{
  for (uint32_t n = 0U; n < (uint32_t)k_eth_rx_inject_max; ++n) {
    uint32_t slot = 0U;
    if (!internal_eth_rx_find_slot(uc, chain, &slot)) {
      return; /* ring full -- backpressure, peer frame stays queued. */
    }
    uint8_t d8[k_eth_desc_bytes];
    internal_eth_desc_read(uc, slot, d8);
    const uint32_t cap = internal_eth_desc_ds(d8);
    const uint32_t buf = internal_eth_desc_ptr(d8);
    if ((buf == 0U) || (cap == 0U)) {
      return;
    }
    const uint32_t want = (cap < (uint32_t)k_eth_frame_max) ? cap : (uint32_t)k_eth_frame_max;
    uint8_t        frame[k_eth_frame_max];
    const uint32_t got = board_net_poll_rx(frame, want);
    if (got == 0U) {
      return; /* peer has nothing more. */
    }
    (void)emu_mem_write(uc, (uint64_t)buf, frame, (size_t)got);
    internal_eth_desc_set_ds(uc, slot, got);
    internal_eth_desc_set_dt(uc, slot, (uint32_t)k_ra8_gwdcc_dt_fsingle);
    s_eth.rx_frames++;
  }
}

RA8_INTERNAL static void internal_eth_tick(uc_engine* uc)
{
  if ((s_eth.linkfix_base == 0U) || (s_eth.rx_queue == (uint32_t)k_eth_queue_none)) {
    return;
  }
  const uint64_t gwmc_woff =
    ((uint64_t)k_ra8_gwca0_base_addr - (uint64_t)k_eth_win_base) + (uint64_t)k_ra8_gwca_off_gwmc;
  const uint32_t opc = internal_eth_shadow_u32(gwmc_woff) & (uint32_t)k_ra8_gwmc_opc_mask;
  if (opc != (uint32_t)k_ra8_gwmc_opc_operation) {
    return; /* rings only live in OPERATION mode. */
  }
  uint8_t        lf[k_eth_desc_bytes];
  const uint32_t lf_addr = s_eth.linkfix_base + (s_eth.rx_queue * (uint32_t)k_eth_desc_bytes);
  internal_eth_desc_read(uc, lf_addr, lf);
  const uint32_t chain = internal_eth_desc_ptr(lf);
  if (chain != 0U) {
    internal_eth_rx_drain_peer(uc, chain);
  }
}
 
/* ------------------------------------------------------------------------- */
/* MMIO dispatch. */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static uint64_t internal_eth_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  const uint64_t off   = addr - (uint64_t)k_eth_win_base;
  uint32_t       queue = 0U;
  if (internal_eth_is_etha_reg(addr, (uint64_t)k_ra8_etha_off_eams)) {
    /* EAMS.OPS mirrors the commanded EAMC.OPC (the mode machine converges). */
    /* HUM Ch 32.3.1.2 "EAMS : Mode Status Register" p 1631 */
    const uint64_t eamc = off - ((uint64_t)k_ra8_etha_off_eams - (uint64_t)k_ra8_etha_off_eamc);
    return internal_eth_shadow_u32(eamc) & (uint32_t)k_ra8_etha_mask_ops;
  }
  if (addr == (uint64_t)k_ra8_gwca0_base_addr + (uint64_t)k_ra8_gwca_off_gwms) {
    /* GWMS.OPS mirrors the commanded GWMC.OPC. */
    /* HUM Ch 34.3.2 "GWMS : Mode Status Register" p 1792 */
    const uint64_t gwmc = off - ((uint64_t)k_ra8_gwca_off_gwms - (uint64_t)k_ra8_gwca_off_gwmc);
    return internal_eth_shadow_u32(gwmc) & (uint32_t)k_ra8_gwmc_opc_mask;
  }
  if (addr == (uint64_t)k_ra8_gwca0_base_addr + (uint64_t)k_ra8_gwca_off_gwarirm) {
    /* GWARIRM.ARR (AXI-init done) follows the ARIOG request. */
    /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
    const uint32_t v = internal_eth_shadow_u32(off);
    return ((v & (uint32_t)k_eth_gwarirm_ariog) != 0U) ? (v | (uint32_t)k_eth_gwarirm_arr) : v;
  }
  if (addr == (uint64_t)k_ra8_coma_base_addr + (uint64_t)k_ra8_coma_off_cabpirm) {
    /* CABPIRM.BPR self-sets after the BPIOG kick (buffer-pool init completes
     * ~512 clocks later); modelling it lets the board bring-up's non-emulator
     * BPR poll converge. */
    /* HUM Ch 31.3.2.7 "CABPIRM" p 1599 */
    const uint32_t v = internal_eth_shadow_u32(off);
    return ((v & (uint32_t)k_ra8_coma_cabpirm_bpiog) != 0U) ? (v | (uint32_t)k_ra8_coma_cabpirm_bpr)
                                                            : v;
  }
  if (internal_eth_is_gwdcc(addr, &queue)) {
    /* GWDCC.BALR self-clears after the reload completes. */
    /* HUM Ch 34.3 "GWDCCi" p 1811 */
    return internal_eth_shadow_u32(off) & ~(uint32_t)k_ra8_gwdcc_balr;
  }
  if (internal_eth_is_rmac_reg(addr, (uint64_t)k_ra8_rmac_off_mtgfce)) {
    return s_eth.tx_frames;
  }
  if (internal_eth_is_rmac_reg(addr, (uint64_t)k_eth_rmac_off_mrfc) ||
      internal_eth_is_rmac_reg(addr, (uint64_t)k_ra8_rmac_off_mrgfce)) {
    return s_eth.rx_frames;
  }
  return internal_eth_shadow_read(off, size);
}

RA8_INTERNAL static void
internal_eth_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  const uint64_t off   = addr - (uint64_t)k_eth_win_base;
  uint32_t       queue = 0U;
  if (addr == (uint64_t)k_ra8_gwca0_base_addr + (uint64_t)k_ra8_gwca_off_gwtrc0) {
    internal_eth_shadow_write(off, size, 0U); /* request register clears when consumed. */
    internal_eth_gwtrc_kick(uc, (uint32_t)value, 0U);
    return;
  }
  if (addr == (uint64_t)k_ra8_gwca0_base_addr + (uint64_t)k_ra8_gwca_off_gwtrc1) {
    internal_eth_shadow_write(off, size, 0U);
    internal_eth_gwtrc_kick(uc, (uint32_t)value, (uint32_t)k_eth_phy_reg_count);
    return;
  }
  if (addr == (uint64_t)k_ra8_gwca0_base_addr + (uint64_t)k_ra8_gwca_off_gwdcbac1) {
    /* Capture the descriptor-chain base so the DMA can walk the rings. */
    /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
    s_eth.linkfix_base = (uint32_t)value;
    internal_eth_shadow_write(off, size, value);
    return;
  }
  if (internal_eth_is_rmac_reg(addr, (uint64_t)k_ra8_rmac_off_mpsm) &&
      ((value & (uint32_t)k_ra8_rmac_mpsm_psme) != 0U)) {
    internal_eth_mpsm_exec(off, (uint32_t)value);
    return;
  }
  internal_eth_shadow_write(off, size, value);
  if (internal_eth_is_gwdcc(addr, &queue) && ((value & (uint32_t)k_ra8_gwdcc_dqt) == 0U)) {
    s_eth.rx_queue = queue; /* GWDCC.DQT == 0 marks the reception queue. */
  }
}

RA8_INTERNAL static void internal_eth_reset(void)
{
  s_eth                           = (eth_state_t){};
  s_eth.rx_queue                  = (uint32_t)k_eth_queue_none;
  s_eth.phy[k_eth_phy_reg_bmcr]   = (uint16_t)k_eth_phy_bmcr_seed;
  s_eth.phy[k_eth_phy_reg_bmsr]   = (uint16_t)k_eth_phy_bmsr_seed;
  s_eth.phy[k_eth_phy_reg_anlpar] = (uint16_t)k_eth_phy_anlpar_seed;
}

RA8_INTERNAL static void internal_eth_report(void)
{
  if ((s_eth.tx_frames == 0U) && (s_eth.rx_frames == 0U)) {
    return; /* not a networking run -- stay quiet. */
  }
  (void)priv_emu_io_errf("  R-Switch      : TX %u frame(s) RX %u frame(s) via GWCA/ETHA/RMAC "
                         "regs; link 100M/FD (MDIO)\n",
                         s_eth.tx_frames,
                         s_eth.rx_frames);
}

static const board_periph_block_t s_k_eth_block = {
  .base   = (uint64_t)k_eth_win_base,
  .span   = (uint64_t)k_eth_win_span,
  .order  = (uint32_t)k_eth_block_order,
  .read   = internal_eth_read,
  .write  = internal_eth_write,
  .tick   = internal_eth_tick,
  .reset  = internal_eth_reset,
  .report = internal_eth_report,
  .name   = "R-Switch(ETH)",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_eth_block_register(void)
{
  internal_eth_reset();
  board_periph_register_block(&s_k_eth_block);
}