board_periph_eth.c File Reference

R-Switch (ESWM / MFWD / COMA / ETHA / RMAC / GWCA) model for ra8_emulator. More...

#include <stdint.h>
#include <stdio.h>
#include "board_console.h"
#include "board_net.h"
#include "board_periph_block.h"
#include "emu_host_io_internal.h"
#include "ra8_etha_regs.h"
#include "ra8_ether_regs.h"
#include "ra8_rmac_regs.h"

Include dependency graph for board_periph_eth.c:

Go to the source code of this file.

Data Structures
struct	eth_state_t
	Runtime state of the R-Switch model. More...

Enumerations
enum	eth_win_geom_t : uint64_t {   k_eth_win_base = (uint64_t)k_ra8_mfwd_base_addr ,   k_eth_win_span = 0xF000UL }
	Absolute window the block owns (the contiguous R-Switch cluster). More...
enum	eth_model_const_t : uint32_t {   k_eth_desc_bytes = 8U ,   k_eth_desc_dt_byte = 2U ,   k_eth_desc_dt_shift = 4U ,   k_eth_desc_dt_lo = 0x0FU ,   k_eth_desc_ds_byte1 = 1U ,   k_eth_desc_ds_hi = 0x0FU ,   k_eth_desc_ds_keep = 0xF0U ,   k_eth_desc_ptr_off = 4U ,   k_eth_reg32_bytes = 4U ,   k_eth_byte_mask = 0xFFU ,   k_eth_shift_byte = 8U ,   k_eth_gwarirm_ariog = 1UL << 0U ,   k_eth_gwarirm_arr = 1UL << 1U ,   k_eth_mpsm_mff = 1UL << 2U ,   k_eth_rmac_off_mrfc = 0x0438U ,   k_eth_frame_max = 1536U ,   k_eth_ring_walk_max = 64U ,   k_eth_rx_inject_max = 8U ,   k_eth_console_cap = 48U ,   k_eth_queue_none = 0xFFFFFFFFU }
	Descriptor-byte layout, MDIO decode, and ring-walk bounds. More...
enum	eth_phy_reg_t : uint16_t {   k_eth_phy_reg_bmcr = 0U ,   k_eth_phy_reg_bmsr = 1U ,   k_eth_phy_reg_anlpar = 5U ,   k_eth_phy_reg_count = 32U ,   k_eth_phy_bmcr_seed = 0x3100U ,   k_eth_phy_bmsr_seed = 0x782DU ,   k_eth_phy_anlpar_seed = 0x01E1U ,   k_eth_phy_bmcr_reset = 0x8000U ,   k_eth_phy_bmcr_anrst = 0x0200U }
	Modelled Clause-22 PHY register indices, seed values, and mode bits. More...
enum	eth_order_t : uint32_t { k_eth_block_order = 58U }
	Per-tick order slot: after the DTC/DMAC transfer engines. More...

Functions
static uint64_t	internal_eth_shadow_read (uint64_t off, unsigned size)
	Read up to size bytes little-endian from the register shadow.
static void	internal_eth_shadow_write (uint64_t off, unsigned size, uint64_t value)
	Write up to size bytes little-endian into the register shadow.
static uint32_t	internal_eth_shadow_u32 (uint64_t off)
	Read a 32-bit shadow register at window offset off.
static uint32_t	internal_eth_bytes_u32 (const uint8_t *p)
	Assemble a little-endian 32-bit value from four bytes p[0..3].
static void	internal_eth_desc_read (uc_engine *uc, uint32_t addr, uint8_t *out8)
	Read an 8-byte descriptor header from emulated memory addr.
static uint32_t	internal_eth_desc_dt (const uint8_t *d8)
	Decode the DT (descriptor type) field of an 8-byte header.
static uint32_t	internal_eth_desc_ds (const uint8_t *d8)
	Decode the 12-bit DS (descriptor size) field of an 8-byte header.
static uint32_t	internal_eth_desc_ptr (const uint8_t *d8)
	Decode the 32-bit PTR (buffer / chain address) of an 8-byte header.
static void	internal_eth_desc_set_dt (uc_engine *uc, uint32_t addr, uint32_t dt)
	Write the DT field of the descriptor at emulated address addr.
static void	internal_eth_desc_set_ds (uc_engine *uc, uint32_t addr, uint32_t ds)
	Write the 12-bit DS field of the descriptor at address addr.
static bool	internal_eth_is_etha_reg (uint64_t addr, uint64_t off)
	True if addr is the given off in either ETHA port window.
static bool	internal_eth_is_rmac_reg (uint64_t addr, uint64_t off)
	True if addr is the given off in either RMAC port window.
static bool	internal_eth_is_gwdcc (uint64_t addr, uint32_t *queue)
	True if addr is one of GWCA GWDCC[0..31]; sets *queue.
static uint16_t	internal_eth_phy_read (uint32_t reg)
	Read a modelled Clause-22 PHY register (out-of-range reads 0).
static void	internal_eth_phy_write (uint32_t reg, uint16_t value)
	Write a modelled Clause-22 PHY register (self-clearing BMCR bits).
static void	internal_eth_mpsm_exec (uint64_t mpsm_off, uint32_t value)
	Execute an MPSM (PHY Station Management) transaction on write.
static void	internal_eth_tx_kick_queue (uc_engine *uc, uint32_t queue)
	Move the frame queued on GWCA queue queue out to the peer.
static void	internal_eth_gwtrc_kick (uc_engine *uc, uint32_t bits, uint32_t base_queue)
	Fire internal_eth_tx_kick_queue for every set bit of a GWTRC word.
static bool	internal_eth_rx_find_slot (uc_engine *uc, uint32_t chain, uint32_t *out_slot)
	Walk an RX ring from chain for the next FEMPTY slot.
static void	internal_eth_rx_drain_peer (uc_engine *uc, uint32_t chain)
	Drain waiting peer frames into free slots of the RX ring chain.
static void	internal_eth_tick (uc_engine *uc)
	Per-tick RX pump: stage peer frames once the GWCA is in OPERATION.
static uint64_t	internal_eth_read (uc_engine *uc, uint64_t addr, unsigned size)
	MMIO read handler for the R-Switch window.
static void	internal_eth_write (uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
	MMIO write handler for the R-Switch window.
static void	internal_eth_reset (void)
	Reset the R-Switch model and re-seed the modelled PHY register file.
static void	internal_eth_report (void)
	End-of-run R-Switch section: frames moved through the register model.
static void	internal_eth_block_register (void)
	Register the R-Switch block + seed the PHY file before main runs.

Variables
static eth_state_t	s_eth
	Singleton R-Switch model state.
static const board_periph_block_t	s_k_eth_block
	R-Switch cluster block descriptor.

Detailed Description

R-Switch (ESWM / MFWD / COMA / ETHA / RMAC / GWCA) model for ra8_emulator.

Models the RA8D2 Layer-3 Ethernet switch register cluster so a networking app (threadx_netx_tcp_echo and the eth_* demos) runs the GENUINE ra8_eth / ra8_etha / ra8_rmac / ra8_eth_gwca drivers headless, instead of the function-level seam hooks that used to intercept ra8_eth_write / ra8_eth_read / ra8_eth_link_status and bypass the register path entirely. Retires those seams (see #219 / #218).

The block owns the contiguous cluster window [0x403C0000, 0x403CF000): MFWD (0x403C0000), ESWM (0x403C8000), COMA (0x403C9000), ETHA0/1 (0x403CA000 / 0x403CC000), RMAC0/1 (0x403CB000 / 0x403CD000) and GWCA (0x403CE000). Config registers read back what was written (a flat byte shadow); the load-bearing status / action registers are modelled faithfully:

• ETHA EAMS.OPS mirrors EAMC.OPC (HUM Ch 32.3.1.2 p 1631): the mode state machine converges to the commanded mode, so the driver's CONFIG / DISABLE equality-poll completes instead of spinning ~1e8 MMIO callbacks against the sparse fallback.
• GWCA GWMS.OPS mirrors GWMC.OPC (HUM Ch 34.3.2 p 1798) and GWARIRM.ARR asserts after ARIOG, and GWDCC[i].BALR self-clears.
• RMAC MPSM MDIO: a Clause-22 read returns the modelled PHY register (BMSR link-up + auto-neg-complete, ANLPAR = 100BASE-TX FD), a write self-clears BMCR.RESET; the whole PHY chip-init + link bring-up runs.
• GWCA descriptor DMA: on the GWTRC TX kick the model walks the queue's LINKFIX -> chain-head descriptor in emulated SRAM, moves the frame bytes out to the ::board_net virtual peer and writes the descriptor back to FEMPTY (so the driver's TX-complete wait resolves); once per tick it pulls the peer's reply frames into free RX descriptors so the driver's poll delivers them. MTGFCE / MRFC / MRGFCE count the moved frames.

Honest-model note: an unmodelled descriptor type or an un-configured queue is a no-op (the driver's own timeout fires), never a faked success; the link is reported up at 100 Mb/s full-duplex because ::board_net is a real peer on the wire, not because the value is invented.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file board_periph_eth.c.

Enumeration Type Documentation

eth_model_const_t

enum eth_model_const_t : uint32_t

Descriptor-byte layout, MDIO decode, and ring-walk bounds.

The GWCA descriptor is little-endian: byte 0 = DS[7:0], byte 1 low nibble = DS[11:8], byte 2 bits [7:4] = DT, bytes 4..7 = PTR[31:0] (HUM Ch 34.5.1.2 "General Formats"). MRFC has no named offset in the register header, so it is declared here with its HUM-cited value.

Enumerator
k_eth_desc_bytes	Basic-descriptor / LINKFIX entry size.
k_eth_desc_dt_byte	DT lives in descriptor byte 2.
k_eth_desc_dt_shift	DT occupies bits [7:4] of that byte.
k_eth_desc_dt_lo	Low-nibble mask (bits kept on a DT set).
k_eth_desc_ds_byte1	DS[11:8] in low nibble of byte 1.
k_eth_desc_ds_hi	DS high-nibble mask.
k_eth_desc_ds_keep	Byte-1 high-nibble kept on a DS set.
k_eth_desc_ptr_off	PTR[31:0] at descriptor byte 4.
k_eth_reg32_bytes	One 32-bit register.
k_eth_byte_mask	Low 8 bits of a value.
k_eth_shift_byte	One-byte shift.
k_eth_gwarirm_ariog	GWARIRM.ARIOG AXI-init request.
k_eth_gwarirm_arr	GWARIRM.ARR AXI-init response.
k_eth_mpsm_mff	MPSM.MFF: 1 = Clause-45 frame format.
k_eth_rmac_off_mrfc	RMAC MRFC (RX total frame count).
k_eth_frame_max	Marshal buffer cap (>= max 802.3 frame).
k_eth_ring_walk_max	Bound on a descriptor-ring scan.
k_eth_rx_inject_max	Max frames injected into the ring / tick.
k_eth_console_cap	Console NET-tab line capacity.
k_eth_queue_none	"No RX queue configured yet" sentinel.

Definition at line 82 of file board_periph_eth.c.

eth_order_t

enum eth_order_t : uint32_t

Per-tick order slot: after the DTC/DMAC transfer engines.

Enumerator
k_eth_block_order	Report + tick order (just after DTC=55).

Definition at line 127 of file board_periph_eth.c.

eth_phy_reg_t

enum eth_phy_reg_t : uint16_t

Modelled Clause-22 PHY register indices, seed values, and mode bits.

Standard IEEE 802.3 MII register numbers. The seeds describe a PHY that has auto-negotiated a 100BASE-TX full-duplex link (consistent with the ::board_net peer): BMSR reports LINK + AN-complete, ANLPAR advertises 100BASE-TX FD as the top ability. BMCR.RESET / .AN_RESTART are self-clearing.

Enumerator
k_eth_phy_reg_bmcr	BMCR (basic control).
k_eth_phy_reg_bmsr	BMSR (basic status).
k_eth_phy_reg_anlpar	ANLPAR (link-partner ability).
k_eth_phy_reg_count	Clause-22 register-space size.
k_eth_phy_bmcr_seed	AN enable + 100 Mb/s + full duplex.
k_eth_phy_bmsr_seed	100/10 abilities + AN done + LINK.
k_eth_phy_anlpar_seed	100F/100H/10F/10H + selector.
k_eth_phy_bmcr_reset	BMCR.RESET (self-clearing).
k_eth_phy_bmcr_anrst	BMCR.AN_RESTART (self-clearing).

Definition at line 114 of file board_periph_eth.c.

eth_win_geom_t

enum eth_win_geom_t : uint64_t

Absolute window the block owns (the contiguous R-Switch cluster).

Spans MFWD (the lowest base) through the end of the GWCA register bank. The ESWM media-mux sub-block (MIIRR / MIICR at 0x403E1400) sits outside this window and falls to the sparse fallback – it is config-reflect only, so that is faithful. GPTP (0x403E0000) sits outside this window too but is modelled by its own block (board_periph_gptp.c), whose free-running counter really advances.

Enumerator
k_eth_win_base	MFWD base = window base.
k_eth_win_span	MFWD..GWCA end.

Definition at line 68 of file board_periph_eth.c.

Function Documentation

internal_eth_block_register()

void internal_eth_block_register ( void )

static

Register the R-Switch block + seed the PHY file before main runs.

Definition at line 871 of file board_periph_eth.c.

References board_periph_register_block(), internal_eth_reset(), RA8_INTERNAL, and s_k_eth_block.

internal_eth_bytes_u32()

uint32_t internal_eth_bytes_u32 ( const uint8_t * p )

static

Assemble a little-endian 32-bit value from four bytes p[0..3].

Assemble a little-endian 32-bit value from four bytes p[0..3]; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]

p

Module-owned state object processed by the operation.

Returns

The Ethernet bytes u32 result produced by the board periph Ethernet model.

Return values

value

The operation-specific Ethernet bytes u32 value.

Precondition

Arguments satisfy the ranges documented for Ethernet bytes u32.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 230 of file board_periph_eth.c.

References k_eth_reg32_bytes, k_eth_shift_byte, and RA8_INTERNAL.

Referenced by internal_eth_desc_ptr().

internal_eth_desc_ds()

uint32_t internal_eth_desc_ds ( const uint8_t * d8 )

static

Decode the 12-bit DS (descriptor size) field of an 8-byte header.

Decode the 12-bit ds (descriptor size) field of an 8-byte header; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]

d8

D8 input used by the operation.

Returns

The Ethernet desc ds result produced by the board periph Ethernet model.

Return values

value

The operation-specific Ethernet desc ds value.

Precondition

Arguments satisfy the ranges documented for Ethernet desc ds.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 282 of file board_periph_eth.c.

References k_eth_desc_ds_byte1, k_eth_desc_ds_hi, k_eth_shift_byte, and RA8_INTERNAL.

Referenced by internal_eth_rx_drain_peer(), and internal_eth_tx_kick_queue().

internal_eth_desc_dt()

uint32_t internal_eth_desc_dt ( const uint8_t * d8 )

static

Decode the DT (descriptor type) field of an 8-byte header.

Decode the dt (descriptor type) field of an 8-byte header; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]

d8

D8 input used by the operation.

Returns

The Ethernet desc dt result produced by the board periph Ethernet model.

Return values

value

The operation-specific Ethernet desc dt value.

Precondition

Arguments satisfy the ranges documented for Ethernet desc dt.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 266 of file board_periph_eth.c.

References k_eth_desc_dt_byte, k_eth_desc_dt_lo, k_eth_desc_dt_shift, and RA8_INTERNAL.

Referenced by internal_eth_rx_find_slot(), and internal_eth_tx_kick_queue().

internal_eth_desc_ptr()

uint32_t internal_eth_desc_ptr ( const uint8_t * d8 )

static

Decode the 32-bit PTR (buffer / chain address) of an 8-byte header.

Decode the 32-bit ptr (buffer / chain address) of an 8-byte header; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]

d8

D8 input used by the operation.

Returns

The Ethernet desc ptr result produced by the board periph Ethernet model.

Return values

value

The operation-specific Ethernet desc ptr value.

Precondition

Arguments satisfy the ranges documented for Ethernet desc ptr.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 299 of file board_periph_eth.c.

References internal_eth_bytes_u32(), k_eth_desc_ptr_off, and RA8_INTERNAL.

Referenced by internal_eth_rx_drain_peer(), internal_eth_rx_find_slot(), internal_eth_tick(), and internal_eth_tx_kick_queue().

internal_eth_desc_read()

void internal_eth_desc_read ( uc_engine * uc, uint32_t addr, uint8_t * out8 )

static

Read an 8-byte descriptor header from emulated memory addr.

Read an 8-byte descriptor header from emulated memory addr; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in,out]	out8	Out8 state or storage updated in place by the operation.

Precondition

Arguments satisfy the ranges documented for Ethernet desc read.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 250 of file board_periph_eth.c.

References emu_mem_read(), k_eth_desc_bytes, and RA8_INTERNAL.

Referenced by internal_eth_rx_drain_peer(), internal_eth_rx_find_slot(), internal_eth_tick(), and internal_eth_tx_kick_queue().

internal_eth_desc_set_ds()

void internal_eth_desc_set_ds ( uc_engine * uc, uint32_t addr, uint32_t ds )

static

Write the 12-bit DS field of the descriptor at address addr.

Parameters

[in,out]	uc	Active engine.
[in]	addr	Descriptor base in emulated memory.
[in]	ds	Frame length to store (0..4095).

Returns

Nothing.

Precondition

addr points at a live GWCA descriptor.

ds fits in 12 bits.

Postcondition

Bytes 0..1 of the descriptor carry ds (byte-1 high nibble kept).

Other descriptor bytes are untouched.

Note

Not thread-safe.

Since

0.1.0

Write the 12-bit ds field of the descriptor at address addr; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 343 of file board_periph_eth.c.

References emu_mem_read(), emu_mem_write(), k_eth_byte_mask, k_eth_desc_ds_byte1, k_eth_desc_ds_hi, k_eth_desc_ds_keep, k_eth_shift_byte, and RA8_INTERNAL.

Referenced by internal_eth_rx_drain_peer().

internal_eth_desc_set_dt()

void internal_eth_desc_set_dt ( uc_engine * uc, uint32_t addr, uint32_t dt )

static

Write the DT field of the descriptor at emulated address addr.

Parameters

[in,out]	uc	Active engine.
[in]	addr	Descriptor base in emulated memory.
[in]	dt	New descriptor-type nibble.

Returns

Nothing.

Precondition

addr points at a live GWCA descriptor.

dt is a valid ra8_gwdcc_dt_t nibble.

Postcondition

Byte 2 of the descriptor carries dt in bits [7:4].

Other descriptor bytes are untouched.

Note

Not thread-safe.

Since

0.1.0

Write the dt field of the descriptor at emulated address addr; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 319 of file board_periph_eth.c.

References emu_mem_read(), emu_mem_write(), k_eth_desc_dt_byte, k_eth_desc_dt_lo, k_eth_desc_dt_shift, and RA8_INTERNAL.

Referenced by internal_eth_rx_drain_peer(), and internal_eth_tx_kick_queue().

internal_eth_gwtrc_kick()

void internal_eth_gwtrc_kick ( uc_engine * uc, uint32_t bits, uint32_t base_queue )

static

Fire internal_eth_tx_kick_queue for every set bit of a GWTRC word.

Fire internal_eth_tx_kick_queue for every set bit of a gwtrc word; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	bits	Bits input used by the operation.
[in]	base_queue	Base queue input used by the operation.

Precondition

Arguments satisfy the ranges documented for Ethernet gwtrc kick.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 575 of file board_periph_eth.c.

References internal_eth_tx_kick_queue(), k_eth_phy_reg_count, and RA8_INTERNAL.

Referenced by internal_eth_write().

internal_eth_is_etha_reg()

bool internal_eth_is_etha_reg ( uint64_t addr, uint64_t off )

static

True if addr is the given off in either ETHA port window.

True if addr is the given off in either etha port window; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]	addr	Guest address involved in the operation.
[in]	off	Register or byte offset addressed by the operation.

Returns

The Ethernet is etha reg result produced by the board periph Ethernet model.

Return values

true	The Ethernet is etha reg condition holds or completed successfully; false otherwise.

Precondition

Arguments satisfy the ranges documented for Ethernet is etha reg.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 370 of file board_periph_eth.c.

References k_ra8_etha0_base_addr, k_ra8_etha1_base_addr, and RA8_INTERNAL.

Referenced by internal_eth_read().

internal_eth_is_gwdcc()

bool internal_eth_is_gwdcc ( uint64_t addr, uint32_t * queue )

static

True if addr is one of GWCA GWDCC[0..31]; sets *queue.

Tests the bounded GWCA GWDCC register window and publishes the matching queue index through queue when the address belongs to it.

Parameters

[in]	addr	Guest address involved in the operation.
[in,out]	queue	Queue state or storage updated in place by the operation.

Returns

The Ethernet is gwdcc result produced by the board periph Ethernet model.

Return values

true	The Ethernet is gwdcc condition holds or completed successfully; false otherwise.

Precondition

Arguments satisfy the ranges documented for Ethernet is gwdcc.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 407 of file board_periph_eth.c.

References k_eth_phy_reg_count, k_eth_reg32_bytes, k_ra8_gwca0_base_addr, k_ra8_gwca_off_gwdcc_base, and RA8_INTERNAL.

Referenced by internal_eth_read(), and internal_eth_write().

internal_eth_is_rmac_reg()

bool internal_eth_is_rmac_reg ( uint64_t addr, uint64_t off )

static

True if addr is the given off in either RMAC port window.

True if addr is the given off in either rmac port window; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]	addr	Guest address involved in the operation.
[in]	off	Register or byte offset addressed by the operation.

Returns

The Ethernet is rmac reg result produced by the board periph Ethernet model.

Return values

true	The Ethernet is rmac reg condition holds or completed successfully; false otherwise.

Precondition

Arguments satisfy the ranges documented for Ethernet is rmac reg.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 388 of file board_periph_eth.c.

References k_ra8_rmac0_base_addr, k_ra8_rmac1_base_addr, and RA8_INTERNAL.

Referenced by internal_eth_read(), and internal_eth_write().

internal_eth_mpsm_exec()

void internal_eth_mpsm_exec ( uint64_t mpsm_off, uint32_t value )

static

Execute an MPSM (PHY Station Management) transaction on write.

HUM Ch 33.4.1.1 "MPSM : PHY Station Management Register" p 1707. PSME (bit 0) starts the transfer and self-clears on completion. A Clause-22 read loads the PHY register into PRD[31:16]; a write updates the modelled PHY. The stored word always has PSME cleared so the driver's drain / wait poll resolves. Clause-45 is not modelled beyond clearing PSME (the eth path uses C22 only).

Parameters

[in]	mpsm_off	Window offset of the MPSM register.
[in]	value	Value written to MPSM.

Returns

Nothing.

Precondition

mpsm_off addresses an RMAC MPSM register.

value has PSME set (a live transaction).

Postcondition

The MPSM shadow reads back with PSME == 0 and PRD holding the result.

A C22 write has updated the modelled PHY register file.

Note

Not thread-safe.

Since

0.1.0

Definition at line 487 of file board_periph_eth.c.

References internal_eth_phy_read(), internal_eth_phy_write(), internal_eth_shadow_write(), k_eth_mpsm_mff, k_eth_reg32_bytes, k_ra8_rmac_mask_mpsm_data, k_ra8_rmac_mask_mpsm_op, k_ra8_rmac_mask_mpsm_phy_reg, k_ra8_rmac_mdio_op_c22_read, k_ra8_rmac_mdio_op_c22_write, k_ra8_rmac_mpsm_psme, k_ra8_rmac_shift_mpsm_pop, k_ra8_rmac_shift_mpsm_pra, k_ra8_rmac_shift_mpsm_prd, and RA8_INTERNAL.

Referenced by internal_eth_write().

internal_eth_phy_read()

uint16_t internal_eth_phy_read ( uint32_t reg )

static

Read a modelled Clause-22 PHY register (out-of-range reads 0).

Read a modelled clause-22 phy register (out-of-range reads 0); this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]

reg

Register index or value selected by the operation.

Returns

The Ethernet phy read result produced by the board periph Ethernet model.

Return values

value

The operation-specific Ethernet phy read value.

Precondition

Arguments satisfy the ranges documented for Ethernet phy read.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 433 of file board_periph_eth.c.

References k_eth_phy_reg_count, RA8_INTERNAL, and s_eth.

Referenced by internal_eth_mpsm_exec().

internal_eth_phy_write()

void internal_eth_phy_write ( uint32_t reg, uint16_t value )

static

Write a modelled Clause-22 PHY register (self-clearing BMCR bits).

Parameters

[in]	reg	PHY register index (0..31).
[in]	value	16-bit value written over MDIO.

Returns

Nothing.

Precondition

reg addresses the modelled Clause-22 space.

The caller has decoded a C22 write transaction.

Postcondition

BMCR.RESET / .AN_RESTART are dropped so the driver's poll sees them self-clear, exactly as a real PHY does.

Any other register stores value verbatim.

Note

Not thread-safe.

Since

0.1.0

Write a modelled clause-22 phy register (self-clearing bmcr bits); this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 456 of file board_periph_eth.c.

References k_eth_phy_bmcr_anrst, k_eth_phy_bmcr_reset, k_eth_phy_reg_bmcr, k_eth_phy_reg_count, RA8_INTERNAL, and s_eth.

Referenced by internal_eth_mpsm_exec().

internal_eth_read()

uint64_t internal_eth_read ( uc_engine * uc, uint64_t addr, unsigned size )

static

MMIO read handler for the R-Switch window.

Parameters

[in,out]	uc	Active engine (unused: reads never touch SRAM).
[in]	addr	Absolute register address.
[in]	size	Access width.

Returns

The register value.

Return values

value

Computed status or the config shadow.

Precondition

addr is inside [k_eth_win_base, k_eth_win_base + k_eth_win_span).

size is 1, 2, or 4.

Postcondition

No emulated memory is modified.

Status registers converge to their commanded / modelled value.

Note

Not thread-safe.

Since

0.1.0

MMIO read handler for the r-switch window; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 725 of file board_periph_eth.c.

References internal_eth_is_etha_reg(), internal_eth_is_gwdcc(), internal_eth_is_rmac_reg(), internal_eth_shadow_read(), internal_eth_shadow_u32(), k_eth_gwarirm_ariog, k_eth_gwarirm_arr, k_eth_rmac_off_mrfc, k_eth_win_base, k_ra8_coma_base_addr, k_ra8_coma_cabpirm_bpiog, k_ra8_coma_cabpirm_bpr, k_ra8_coma_off_cabpirm, k_ra8_etha_mask_ops, k_ra8_etha_off_eamc, k_ra8_etha_off_eams, k_ra8_gwca0_base_addr, k_ra8_gwca_off_gwarirm, k_ra8_gwca_off_gwmc, k_ra8_gwca_off_gwms, k_ra8_gwdcc_balr, k_ra8_gwmc_opc_mask, k_ra8_rmac_off_mrgfce, k_ra8_rmac_off_mtgfce, RA8_INTERNAL, and s_eth.

internal_eth_report()

void internal_eth_report ( void )

static

End-of-run R-Switch section: frames moved through the register model.

End-of-run r-switch section: frames moved through the register model; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Precondition

Arguments satisfy the ranges documented for Ethernet report.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 846 of file board_periph_eth.c.

References priv_emu_io_errf(), RA8_INTERNAL, and s_eth.

internal_eth_reset()

void internal_eth_reset ( void )

static

Reset the R-Switch model and re-seed the modelled PHY register file.

Reset the r-switch model and re-seed the modelled phy register file; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Precondition

Arguments satisfy the ranges documented for Ethernet reset.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 829 of file board_periph_eth.c.

References k_eth_phy_anlpar_seed, k_eth_phy_bmcr_seed, k_eth_phy_bmsr_seed, k_eth_phy_reg_anlpar, k_eth_phy_reg_bmcr, k_eth_phy_reg_bmsr, k_eth_queue_none, RA8_INTERNAL, and s_eth.

Referenced by internal_eth_block_register().

internal_eth_rx_drain_peer()

void internal_eth_rx_drain_peer ( uc_engine * uc, uint32_t chain )

static

Drain waiting peer frames into free slots of the RX ring chain.

For each free FEMPTY slot the model pulls one frame from board_net_poll_rx (bounded by the slot buffer capacity), writes it into the slot buffer, sets DS to the length and DT to FSINGLE so the driver's poll delivers it. The peer is polled ONLY when a free slot exists, so a frame is never dequeued and dropped – a full ring is honest backpressure.

Parameters

[in,out]	uc	Active engine.
[in]	chain	RX ring chain-head address.

Returns

Nothing.

Precondition

The RX ring lives in mapped emulated memory.

The GWCA is in OPERATION (checked by the caller).

Postcondition

Up to k_eth_rx_inject_max frames are staged FSINGLE in the ring.

s_eth.rx_frames / the MRFC / MRGFCE mirrors advance per frame.

Note

Not thread-safe.

Since

0.1.0

Definition at line 649 of file board_periph_eth.c.

References board_net_poll_rx(), emu_mem_write(), internal_eth_desc_ds(), internal_eth_desc_ptr(), internal_eth_desc_read(), internal_eth_desc_set_ds(), internal_eth_desc_set_dt(), internal_eth_rx_find_slot(), k_eth_desc_bytes, k_eth_frame_max, k_eth_rx_inject_max, k_ra8_gwdcc_dt_fsingle, RA8_INTERNAL, and s_eth.

Referenced by internal_eth_tick().

internal_eth_rx_find_slot()

bool internal_eth_rx_find_slot ( uc_engine * uc, uint32_t chain, uint32_t * out_slot )

static

Walk an RX ring from chain for the next FEMPTY slot.

Parameters

[in,out]	uc	Active engine.
[in]	chain	Ring chain-head address in emulated memory.
[out]	out_slot	Address of the first FEMPTY descriptor.

Returns

true if a free slot was found, else false (ring full / malformed).

Return values

true	*out_slot holds a FEMPTY descriptor address.
false	No free slot within the walk bound.

Precondition

chain addresses a live descriptor ring.

out_slot is non-null.

Postcondition

On true, *out_slot is a FEMPTY descriptor; on false it is untouched.

The walk is bounded by k_eth_ring_walk_max (NASA P10 Rule 2).

Note

Not thread-safe.

Since

0.1.0

Walk an rx ring from chain for the next fempty slot; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 606 of file board_periph_eth.c.

References internal_eth_desc_dt(), internal_eth_desc_ptr(), internal_eth_desc_read(), k_eth_desc_bytes, k_eth_ring_walk_max, k_ra8_gwdcc_dt_fempty, k_ra8_gwdcc_dt_link, and k_ra8_gwdcc_dt_linkfix.

Referenced by internal_eth_rx_drain_peer().

internal_eth_shadow_read()

uint64_t internal_eth_shadow_read ( uint64_t off, unsigned size )

static

Read up to size bytes little-endian from the register shadow.

Parameters

[in]	off	Byte offset inside the window.
[in]	size	Access width (1 / 2 / 4).

Returns

The assembled value.

Return values

value

Little-endian shadow bytes.

Precondition

off is inside [0, k_eth_win_span).

size is 1, 2, or 4.

Postcondition

No state is modified.

Bytes past the window read as zero.

Note

Not thread-safe.

Since

0.1.0

Read up to size bytes little-endian from the register shadow; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 172 of file board_periph_eth.c.

References k_eth_shift_byte, k_eth_win_span, RA8_INTERNAL, and s_eth.

Referenced by internal_eth_read(), and internal_eth_shadow_u32().

internal_eth_shadow_u32()

uint32_t internal_eth_shadow_u32 ( uint64_t off )

static

Read a 32-bit shadow register at window offset off.

Read a 32-bit shadow register at window offset off; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in]

off

Register or byte offset addressed by the operation.

Returns

The Ethernet shadow u32 result produced by the board periph Ethernet model.

Return values

value

The operation-specific Ethernet shadow u32 value.

Precondition

Arguments satisfy the ranges documented for Ethernet shadow u32.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 214 of file board_periph_eth.c.

References internal_eth_shadow_read(), k_eth_reg32_bytes, and RA8_INTERNAL.

Referenced by internal_eth_read(), and internal_eth_tick().

internal_eth_shadow_write()

void internal_eth_shadow_write ( uint64_t off, unsigned size, uint64_t value )

static

Write up to size bytes little-endian into the register shadow.

Parameters

[in]	off	Byte offset inside the window.
[in]	size	Access width (1 / 2 / 4).
[in]	value	Value to store.

Returns

Nothing.

Precondition

off is inside [0, k_eth_win_span).

size is 1, 2, or 4.

Postcondition

The shadow bytes reflect value.

Bytes past the window are dropped.

Note

Not thread-safe.

Since

0.1.0

Write up to size bytes little-endian into the register shadow; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 196 of file board_periph_eth.c.

References k_eth_shift_byte, k_eth_win_span, RA8_INTERNAL, and s_eth.

Referenced by internal_eth_mpsm_exec(), and internal_eth_write().

internal_eth_tick()

void internal_eth_tick ( uc_engine * uc )

static

Per-tick RX pump: stage peer frames once the GWCA is in OPERATION.

Per-tick rx pump: stage peer frames once the gwca is in operation; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Parameters

[in,out]

uc

Unicorn engine whose emulated state is read or updated.

Precondition

Arguments satisfy the ranges documented for Ethernet tick.

The call executes on the emulator's single owning thread.

Postcondition

State changes remain confined to the board periph Ethernet model and documented output objects.

Ownership of caller-supplied storage is unchanged.

Note

The operation is synchronous and does not transfer heap ownership.

Since

0.1.0

Definition at line 685 of file board_periph_eth.c.

References internal_eth_desc_ptr(), internal_eth_desc_read(), internal_eth_rx_drain_peer(), internal_eth_shadow_u32(), k_eth_desc_bytes, k_eth_queue_none, k_eth_win_base, k_ra8_gwca0_base_addr, k_ra8_gwca_off_gwmc, k_ra8_gwmc_opc_mask, k_ra8_gwmc_opc_operation, RA8_INTERNAL, and s_eth.

internal_eth_tx_kick_queue()

void internal_eth_tx_kick_queue ( uc_engine * uc, uint32_t queue )

static

Move the frame queued on GWCA queue queue out to the peer.

On the TX kick the model reads LINKFIX[queue] to find the chain head, and if the head descriptor is FSINGLE (the only type the NIC TX path emits) copies its frame out of emulated SRAM to board_net_on_tx and marks the descriptor FEMPTY so the driver's TX-complete wait resolves. A head that is not FSINGLE is left untouched (the driver's own timeout fires) – never a faked completion.

Parameters

[in,out]	uc	Active engine (reads the rings from SRAM).
[in]	queue	GWCA queue number that was kicked.

Returns

Nothing.

Precondition

The descriptor rings live in mapped emulated memory.

s_eth.linkfix_base was captured from GWDCBAC1.

Postcondition

A single-fragment frame has been delivered and its slot freed.

s_eth.tx_frames / the MTGFCE mirror advanced on delivery.

Note

Not thread-safe.

Since

0.1.0

Definition at line 530 of file board_periph_eth.c.

References board_console_push(), board_net_on_tx(), emu_mem_read(), internal_eth_desc_ds(), internal_eth_desc_dt(), internal_eth_desc_ptr(), internal_eth_desc_read(), internal_eth_desc_set_dt(), k_board_console_ch_net, k_eth_console_cap, k_eth_desc_bytes, k_eth_frame_max, k_ra8_gwdcc_dt_fempty, k_ra8_gwdcc_dt_fsingle, RA8_INTERNAL, and s_eth.

Referenced by internal_eth_gwtrc_kick().

internal_eth_write()

void internal_eth_write ( uc_engine * uc, uint64_t addr, unsigned size, uint64_t value )

static

MMIO write handler for the R-Switch window.

Parameters

[in,out]	uc	Active engine (TX kick reads the rings from SRAM).
[in]	addr	Absolute register address.
[in]	size	Access width.
[in]	value	Value written.

Returns

Nothing.

Precondition

addr is inside the block window.

size is 1, 2, or 4.

Postcondition

Config registers reflect value; action registers run their model.

GWDCBAC1 captures the ring base; a GWDCC write records the RX queue.

Note

Not thread-safe.

Since

0.1.0

MMIO write handler for the r-switch window; this step is contained within the board periph Ethernet model and uses bounded caller or module-owned storage.

Definition at line 789 of file board_periph_eth.c.

References internal_eth_gwtrc_kick(), internal_eth_is_gwdcc(), internal_eth_is_rmac_reg(), internal_eth_mpsm_exec(), internal_eth_shadow_write(), k_eth_phy_reg_count, k_eth_win_base, k_ra8_gwca0_base_addr, k_ra8_gwca_off_gwdcbac1, k_ra8_gwca_off_gwtrc0, k_ra8_gwca_off_gwtrc1, k_ra8_gwdcc_dqt, k_ra8_rmac_mpsm_psme, k_ra8_rmac_off_mpsm, and s_eth.

Variable Documentation

s_eth

eth_state_t s_eth

static

Singleton R-Switch model state.

Definition at line 151 of file board_periph_eth.c.

Referenced by internal_eth_phy_read(), internal_eth_phy_write(), internal_eth_read(), internal_eth_report(), internal_eth_reset(), internal_eth_rx_drain_peer(), internal_eth_shadow_read(), internal_eth_shadow_write(), internal_eth_tick(), internal_eth_tx_kick_queue(), and internal_eth_write().

s_k_eth_block

const board_periph_block_t s_k_eth_block

static

Initial value:

                                                = {
  .base   = (uint64_t)k_eth_win_base,
  .span   = (uint64_t)k_eth_win_span,
  .order  = (uint32_t)k_eth_block_order,
  .read   = internal_eth_read,
  .write  = internal_eth_write,
  .tick   = internal_eth_tick,
  .reset  = internal_eth_reset,
  .report = internal_eth_report,
  .name   = "R-Switch(ETH)",
}

R-Switch cluster block descriptor.

Definition at line 858 of file board_periph_eth.c.

Referenced by internal_eth_block_register().