ra8_spi_regs.h File Reference

SPI_B register layout for the Renesas RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

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Data Structures
struct	r_spi_regs_t
	SPI_B register-window mirror (matches FSP R_SPI_B0_Type, 0x70 bytes). More...

Enumerations
enum	ra8_spi_addr_t : uintptr_t {   k_ra8_spi0_base_addr = 0x4035C000UL ,   k_ra8_spi1_base_addr = 0x4035C100UL }
	SPI_B register-window base addresses (FSP R_SPI_B0_BASE / R_SPI_B1_BASE). More...
enum	ra8_spi_limits_t : uint16_t {   k_ra8_spi_primary_count = 2U ,   k_ra8_spi_channel_stride = 0x100U ,   k_ra8_spi_cmd_count = 8U ,   k_ra8_spi_block_size = 0x70U }
	SPI_B static dimensioning constants. More...
enum	ra8_spcr_bit_t : uint8_t {   k_ra8_spcr_bit_spe = 0U ,   k_ra8_spcr_bit_sppe = 8U ,   k_ra8_spcr_bit_spoe = 9U ,   k_ra8_spcr_bit_pte = 11U ,   k_ra8_spcr_bit_sckase = 12U ,   k_ra8_spcr_bit_bfds = 13U ,   k_ra8_spcr_bit_modfen = 14U ,   k_ra8_spcr_bit_speie = 16U ,   k_ra8_spcr_bit_sprie = 17U ,   k_ra8_spcr_bit_spiie = 18U ,   k_ra8_spcr_bit_spdres = 19U ,   k_ra8_spcr_bit_sptie = 20U ,   k_ra8_spcr_bit_cendie = 21U ,   k_ra8_spcr_bit_spms = 24U ,   k_ra8_spcr_bit_spfrf = 25U ,   k_ra8_spcr_bit_txmd_lo = 28U ,   k_ra8_spcr_bit_txmd_hi = 29U ,   k_ra8_spcr_bit_mstr = 30U ,   k_ra8_spcr_bit_bpen = 31U }
	SPCR (control register 1) bit positions. More...
enum	ra8_spcr_mask_t : uint32_t {   k_ra8_spcr_mask_spe = 0x00000001UL ,   k_ra8_spcr_mask_modfen = 0x00004000UL ,   k_ra8_spcr_mask_speie = 0x00010000UL ,   k_ra8_spcr_mask_sprie = 0x00020000UL ,   k_ra8_spcr_mask_sptie = 0x00100000UL ,   k_ra8_spcr_mask_cendie = 0x00200000UL ,   k_ra8_spcr_mask_sckase = 0x00001000UL ,   k_ra8_spcr_mask_mstr = 0x40000000UL ,   k_ra8_spcr_mask_txmd = 0x30000000UL }
	SPCR bit-masks. More...
enum	ra8_spsr_bit_t : uint8_t {   k_ra8_spsr_bit_spdrf = 23U ,   k_ra8_spsr_bit_ovrf = 24U ,   k_ra8_spsr_bit_idlnf = 25U ,   k_ra8_spsr_bit_modf = 26U ,   k_ra8_spsr_bit_perf = 27U ,   k_ra8_spsr_bit_udrf = 28U ,   k_ra8_spsr_bit_sptef = 29U ,   k_ra8_spsr_bit_cendf = 30U ,   k_ra8_spsr_bit_sprf = 31U }
	SPSR (status register) bit positions. More...
enum	ra8_spsr_mask_t : uint32_t {   k_ra8_spsr_mask_spdrf = 0x00800000UL ,   k_ra8_spsr_mask_ovrf = 0x01000000UL ,   k_ra8_spsr_mask_idlnf = 0x02000000UL ,   k_ra8_spsr_mask_modf = 0x04000000UL ,   k_ra8_spsr_mask_perf = 0x08000000UL ,   k_ra8_spsr_mask_udrf = 0x10000000UL ,   k_ra8_spsr_mask_sptef = 0x20000000UL ,   k_ra8_spsr_mask_cendf = 0x40000000UL ,   k_ra8_spsr_mask_sprf = 0x80000000UL ,   k_ra8_spsr_mask_errs = 0x1D000000UL }
	SPSR bit-masks. More...
enum	ra8_spsrc_mask_t : uint32_t {   k_ra8_spsrc_mask_spdrfc = 0x00800000UL ,   k_ra8_spsrc_mask_ovrfc = 0x01000000UL ,   k_ra8_spsrc_mask_modfc = 0x04000000UL ,   k_ra8_spsrc_mask_perfc = 0x08000000UL ,   k_ra8_spsrc_mask_udrfc = 0x10000000UL ,   k_ra8_spsrc_mask_sptefc = 0x20000000UL ,   k_ra8_spsrc_mask_cendfc = 0x40000000UL ,   k_ra8_spsrc_mask_sprfc = 0x80000000UL ,   k_ra8_spsrc_mask_all = 0xFD800000UL }
	SPSRC (status clear, write-1-to-clear) masks. More...
enum	ra8_spcmd_bit_t : uint8_t {   k_ra8_spcmd_bit_cpha = 0U ,   k_ra8_spcmd_bit_cpol = 1U ,   k_ra8_spcmd_bit_brdv0 = 2U ,   k_ra8_spcmd_bit_brdv1 = 3U ,   k_ra8_spcmd_bit_sslkp = 7U ,   k_ra8_spcmd_bit_lsbf = 12U ,   k_ra8_spcmd_bit_spnden = 13U ,   k_ra8_spcmd_bit_slnden = 14U ,   k_ra8_spcmd_bit_sckden = 15U ,   k_ra8_spcmd_bit_spb_lo = 16U }
	SPCMDn (command register) bit positions. More...
enum	ra8_spcmd_mask_t : uint32_t {   k_ra8_spcmd_mask_cpha = 0x00000001UL ,   k_ra8_spcmd_mask_cpol = 0x00000002UL ,   k_ra8_spcmd_mask_brdv = 0x0000000CUL ,   k_ra8_spcmd_mask_sslkp = 0x00000080UL ,   k_ra8_spcmd_mask_lsbf = 0x00001000UL ,   k_ra8_spcmd_mask_spnden = 0x00002000UL ,   k_ra8_spcmd_mask_slnden = 0x00004000UL ,   k_ra8_spcmd_mask_sckden = 0x00008000UL ,   k_ra8_spcmd_mask_spb = 0x001F0000UL ,   k_ra8_spcmd_mask_ssla = 0x07000000UL }
	SPCMDn bit-masks (HUM Ch 43.2.7 p 2893). More...
enum	ra8_spcmd_spb_t : uint8_t {   k_ra8_spcmd_spb_8bit = 0x07U ,   k_ra8_spcmd_spb_16bit = 0x0FU ,   k_ra8_spcmd_spb_32bit = 0x1FU }
	SPB[4:0] data-length encodings used by the driver. More...
enum	ra8_spcr3_bit_t : uint8_t {   k_ra8_spcr3_bit_ssl0p = 0U ,   k_ra8_spcr3_bit_ssl1p = 1U ,   k_ra8_spcr3_bit_ssl2p = 2U ,   k_ra8_spcr3_bit_ssl3p = 3U ,   k_ra8_spcr3_bit_spbr = 8U ,   k_ra8_spcr3_bit_spsln = 24U }
	SPCR3 bit positions (SSLnP polarity, SPBR, SPSLN). More...
enum	ra8_spcr3_mask_t : uint32_t {   k_ra8_spcr3_mask_ssl_pol = 0x0000000FUL ,   k_ra8_spcr3_mask_spbr = 0x0000FF00UL ,   k_ra8_spcr3_mask_spsln = 0x07000000UL }
	SPCR3 masks. More...
enum	ra8_spcr3_misc_t : uint8_t { k_ra8_spbr_max = 0xFFU }
	SPCR3 misc constants used in driver-side bit-shifting math. More...
enum	ra8_spfcr_mask_t : uint32_t { k_ra8_spfcr_mask_spfrst = 0x00000001UL }
	SPFCR (FIFO clear) masks. More...
enum	ra8_spcr2_mask_t : uint32_t {   k_ra8_spcr2_mask_splp = 0x00010000UL ,   k_ra8_spcr2_mask_splp2 = 0x00020000UL ,   k_ra8_spcr2_mask_moife = 0x00200000UL ,   k_ra8_spcr2_mask_moifv = 0x00100000UL }
	SPCR2 (control 2) masks. More...
enum	ra8_sppsr_mask_t : uint32_t { k_ra8_sppsr_mask_speps = 0x00000001UL }
	SPPSR (polling status) masks. More...
enum	ra8_spi_b_channel_count_t : uint8_t { k_ra8_spi_b_channel_count = 2U }
	Channel count addressed by the SPI_B driver. More...

Functions
static volatile r_spi_regs_t *	ra8_spi (uint8_t channel)
	Get pointer to SPI_B channel channel (0..1).

Detailed Description

SPI_B register layout for the Renesas RA8D2.

The RA8D2 has two channels of the SPI_B (Type-B SPI) peripheral. HUM Ch 43 "Serial Peripheral Interface (SPI)" (p 2877-2985) opens with the explicit note that "this is the SPI_B version of the SPI peripheral module" and that SPI_B is referred to as SPI in the chapter. The earlier (legacy) SPI block in ra8_spi_regs.h before this commit was modeled after the older 8/16-bit register stack (SPCR uint8_t, SPCMD[8] uint16_t, SPPCR/SPCKD/SSLND/SPND single-byte registers). That layout does not exist on RA8D2 – SPI_B uses a fully 32-bit register file with FIFO and three SPCR registers.

This header is re-derived against FSP R_SPI_B0_Type (R7KA8D2KF_core0.h lines 25545-25946; total size 0x70 = 112 bytes per channel) at base 0x4035C000 (SPI0) / 0x4035C100 (SPI1).

Offset	Name	Width	HUM	Purpose
0x00	SPDR	32	2881	Data (FIFO front-end).
0x04	SPDECR	32	2883	Delay control (SCKDL/...).
0x08	SPCR	32	2884	Control 1 (SPE/MSTR/SPTIE/...)
0x0C	SPCR2	32	2889	Control 2 (loopback, MOIFE).
0x10	SPCR3	32	2891	Control 3 (SPBR, SSLnP).
0x14	SPCMD0	32	2893	Command 0 (CPHA/CPOL/SPB).
0x18	SPCMD1	32	2893	Command 1.
0x1C	SPCMD2	32	2893	Command 2.
0x20	SPCMD3	32	2893	Command 3.
0x24	SPCMD4	32	2893	Command 4.
0x28	SPCMD5	32	2893	Command 5.
0x2C	SPCMD6	32	2893	Command 6.
0x30	SPCMD7	32	2893	Command 7.
0x40	SPDCR	32	2896	Data control (BYSW/SPFC).
0x44	SPDCR2	32	2897	Data control 2 (RTRG/TTRG).
0x50	SPSR	32	2898	Status.
0x58	SPTFSR	32	2904	TX FIFO data stage.
0x5C	SPRFSR	32	2904	RX FIFO data stage.
0x60	SPPSR	32	2905	Polling status.
0x68	SPSRC	32	2905	Status clear (write-1).
0x6C	SPFCR	32	2906	FIFO clear (SPFRST).

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_spi_regs.h.

Enumeration Type Documentation

ra8_spcmd_bit_t

enum ra8_spcmd_bit_t : uint8_t

SPCMDn (command register) bit positions.

HUM Ch 43.2.7 p 2893.

Enumerator
k_ra8_spcmd_bit_cpha	Clock Phase.
k_ra8_spcmd_bit_cpol	Clock Polarity.
k_ra8_spcmd_bit_brdv0	Bit-Rate Division bit 0.
k_ra8_spcmd_bit_brdv1	Bit-Rate Division bit 1.
k_ra8_spcmd_bit_sslkp	SSL Signal Level Hold.
k_ra8_spcmd_bit_lsbf	LSB-first.
k_ra8_spcmd_bit_spnden	Next-Access Delay Enable.
k_ra8_spcmd_bit_slnden	SSL Negation Delay Enable.
k_ra8_spcmd_bit_sckden	SCK Delay Enable.
k_ra8_spcmd_bit_spb_lo	Data Length [20:16] low.

Definition at line 207 of file ra8_spi_regs.h.

ra8_spcmd_mask_t

enum ra8_spcmd_mask_t : uint32_t

SPCMDn bit-masks (HUM Ch 43.2.7 p 2893).

Enumerator
k_ra8_spcmd_mask_cpha	RA8 spcmd mask cpha.
k_ra8_spcmd_mask_cpol	RA8 spcmd mask cpol.
k_ra8_spcmd_mask_brdv	[3:2]
k_ra8_spcmd_mask_sslkp	RA8 spcmd mask sslkp.
k_ra8_spcmd_mask_lsbf	RA8 spcmd mask lsbf.
k_ra8_spcmd_mask_spnden	RA8 spcmd mask spnden.
k_ra8_spcmd_mask_slnden	RA8 spcmd mask slnden.
k_ra8_spcmd_mask_sckden	RA8 spcmd mask sckden.
k_ra8_spcmd_mask_spb	[20:16] data length
k_ra8_spcmd_mask_ssla	[26:24] SSL select

Definition at line 224 of file ra8_spi_regs.h.

ra8_spcmd_spb_t

enum ra8_spcmd_spb_t : uint8_t

SPB[4:0] data-length encodings used by the driver.

HUM Ch 43.2.7 lists the full SPB encoding table – SPB = (N-1) for an N-bit frame width. Mirrored against FSP spi_bit_width_t so the same numeric value can flow from the public driver enum straight into the SPCMDn.SPB field. Values not used by the bring-up driver are not exposed here.

Enumerator
k_ra8_spcmd_spb_8bit	0b00111 -> 8-bit frame.
k_ra8_spcmd_spb_16bit	0b01111 -> 16-bit frame.
k_ra8_spcmd_spb_32bit	0b11111 -> 32-bit frame.

Definition at line 248 of file ra8_spi_regs.h.

ra8_spcr2_mask_t

enum ra8_spcr2_mask_t : uint32_t

SPCR2 (control 2) masks.

HUM Ch 43.2.4 p 2889.

Enumerator
k_ra8_spcr2_mask_splp	Inverting loopback (rx = ~tx).
k_ra8_spcr2_mask_splp2	Non-inverting loopback (rx = tx).
k_ra8_spcr2_mask_moife	COPI Idle Fixed Value Enable.
k_ra8_spcr2_mask_moifv	COPI Idle Fixed Value.

Definition at line 297 of file ra8_spi_regs.h.

ra8_spcr3_bit_t

enum ra8_spcr3_bit_t : uint8_t

SPCR3 bit positions (SSLnP polarity, SPBR, SPSLN).

HUM Ch 43.2.6 p 2891.

Enumerator
k_ra8_spcr3_bit_ssl0p	SSL0 polarity (0=active low).
k_ra8_spcr3_bit_ssl1p	SSL1 polarity.
k_ra8_spcr3_bit_ssl2p	SSL2 polarity.
k_ra8_spcr3_bit_ssl3p	SSL3 polarity.
k_ra8_spcr3_bit_spbr	SPBR field [15:8] – bit-rate divider.
k_ra8_spcr3_bit_spsln	SPSLN field [26:24] – sequence length.

Definition at line 258 of file ra8_spi_regs.h.

ra8_spcr3_mask_t

enum ra8_spcr3_mask_t : uint32_t

SPCR3 masks.

HUM Ch 43.2.6 p 2891.

Enumerator
k_ra8_spcr3_mask_ssl_pol	[3:0] SSLnP.
k_ra8_spcr3_mask_spbr	[15:8] bit-rate divider.
k_ra8_spcr3_mask_spsln	[26:24] sequence length.

Definition at line 271 of file ra8_spi_regs.h.

ra8_spcr3_misc_t

enum ra8_spcr3_misc_t : uint8_t

SPCR3 misc constants used in driver-side bit-shifting math.

Enumerator
k_ra8_spbr_max	SPBR is 8-bit unsigned.

Definition at line 281 of file ra8_spi_regs.h.

ra8_spcr_bit_t

enum ra8_spcr_bit_t : uint8_t

SPCR (control register 1) bit positions.

HUM Ch 43.2.4 p 2884.

Enumerator
k_ra8_spcr_bit_spe	SPI Function Enable.
k_ra8_spcr_bit_sppe	Parity Enable.
k_ra8_spcr_bit_spoe	Parity Mode (0=even, 1=odd).
k_ra8_spcr_bit_pte	Parity Self-Diagnosis Enable.
k_ra8_spcr_bit_sckase	RSPCK Auto-Stop Function Enable.
k_ra8_spcr_bit_bfds	Between Burst Transfer Frames Delay Sel.
k_ra8_spcr_bit_modfen	Mode Fault Error Detection Enable.
k_ra8_spcr_bit_speie	Error Interrupt Enable.
k_ra8_spcr_bit_sprie	RX Buffer Full Interrupt Enable.
k_ra8_spcr_bit_spiie	Idle Interrupt Enable.
k_ra8_spcr_bit_spdres	Receive Data Ready Error Select.
k_ra8_spcr_bit_sptie	TX Buffer Empty Interrupt Enable.
k_ra8_spcr_bit_cendie	Communication End Interrupt Enable.
k_ra8_spcr_bit_spms	3-Wire Mode Select (1) vs 4-Wire (0).
k_ra8_spcr_bit_spfrf	Frame Format Select (Motorola/TI SSP).
k_ra8_spcr_bit_txmd_lo	Communication Mode bit 0.
k_ra8_spcr_bit_txmd_hi	Communication Mode bit 1.
k_ra8_spcr_bit_mstr	Controller/Peripheral Mode Select (1=controller).
k_ra8_spcr_bit_bpen	Synchronization Circuit Bypass Enable.

Definition at line 116 of file ra8_spi_regs.h.

ra8_spcr_mask_t

enum ra8_spcr_mask_t : uint32_t

SPCR bit-masks.

HUM Ch 43.2.4 p 2884.

Enumerator
k_ra8_spcr_mask_spe	RA8 spcr mask spe.
k_ra8_spcr_mask_modfen	RA8 spcr mask modfen.
k_ra8_spcr_mask_speie	RA8 spcr mask speie.
k_ra8_spcr_mask_sprie	RA8 spcr mask sprie.
k_ra8_spcr_mask_sptie	RA8 spcr mask sptie.
k_ra8_spcr_mask_cendie	RA8 spcr mask cendie.
k_ra8_spcr_mask_sckase	RA8 spcr mask sckase.
k_ra8_spcr_mask_mstr	RA8 spcr mask mstr.
k_ra8_spcr_mask_txmd	[29:28] communication mode.

Definition at line 142 of file ra8_spi_regs.h.

ra8_spfcr_mask_t

enum ra8_spfcr_mask_t : uint32_t

SPFCR (FIFO clear) masks.

HUM Ch 43.2.14 p 2906.

Enumerator
k_ra8_spfcr_mask_spfrst	Reset both FIFOs.

Definition at line 289 of file ra8_spi_regs.h.

ra8_spi_addr_t

enum ra8_spi_addr_t : uintptr_t

SPI_B register-window base addresses (FSP R_SPI_B0_BASE / R_SPI_B1_BASE).

Enumerator
k_ra8_spi0_base_addr	HUM Ch 43, SPI0 base.
k_ra8_spi1_base_addr	HUM Ch 43, SPI1 base.

Definition at line 64 of file ra8_spi_regs.h.

ra8_spi_b_channel_count_t

enum ra8_spi_b_channel_count_t : uint8_t

Channel count addressed by the SPI_B driver.

Shared between ra8_spi_b.c (core ops + ISR dispatch) and ra8_spi_b_dma.c (DMA pipes) so both translation units bound their per-channel tables and channel-range checks against the same constant.

Enumerator
k_ra8_spi_b_channel_count	SPI0 + SPI1.

Definition at line 321 of file ra8_spi_regs.h.

ra8_spi_limits_t

enum ra8_spi_limits_t : uint16_t

SPI_B static dimensioning constants.

Enumerator
k_ra8_spi_primary_count	Number of SPI_B channels.
k_ra8_spi_channel_stride	256-byte channel stride.
k_ra8_spi_cmd_count	SPCMD0..SPCMD7 sequence slots.
k_ra8_spi_block_size	112-byte register footprint.

Definition at line 73 of file ra8_spi_regs.h.

ra8_sppsr_mask_t

enum ra8_sppsr_mask_t : uint32_t

SPPSR (polling status) masks.

HUM Ch 43.2.12 p 2905.

Enumerator
k_ra8_sppsr_mask_speps	Asserted while SPI is busy.

Definition at line 308 of file ra8_spi_regs.h.

ra8_spsr_bit_t

enum ra8_spsr_bit_t : uint8_t

SPSR (status register) bit positions.

HUM Ch 43.2.9 p 2898.

Enumerator
k_ra8_spsr_bit_spdrf	Receive Data Ready Flag.
k_ra8_spsr_bit_ovrf	Overrun Error Flag.
k_ra8_spsr_bit_idlnf	Idle Flag.
k_ra8_spsr_bit_modf	Mode Fault Error Flag.
k_ra8_spsr_bit_perf	Parity Error Flag.
k_ra8_spsr_bit_udrf	Underrun Error Flag.
k_ra8_spsr_bit_sptef	TX Buffer Empty Flag.
k_ra8_spsr_bit_cendf	Communication End Flag.
k_ra8_spsr_bit_sprf	RX Buffer Full Flag.

Definition at line 158 of file ra8_spi_regs.h.

ra8_spsr_mask_t

enum ra8_spsr_mask_t : uint32_t

SPSR bit-masks.

HUM Ch 43.2.9 p 2898.

Enumerator
k_ra8_spsr_mask_spdrf	RA8 spsr mask spdrf.
k_ra8_spsr_mask_ovrf	RA8 spsr mask ovrf.
k_ra8_spsr_mask_idlnf	RA8 spsr mask idlnf.
k_ra8_spsr_mask_modf	RA8 spsr mask modf.
k_ra8_spsr_mask_perf	RA8 spsr mask perf.
k_ra8_spsr_mask_udrf	RA8 spsr mask udrf.
k_ra8_spsr_mask_sptef	RA8 spsr mask sptef.
k_ra8_spsr_mask_cendf	RA8 spsr mask cendf.
k_ra8_spsr_mask_sprf	RA8 spsr mask sprf.
k_ra8_spsr_mask_errs	OVRF | MODF | PERF | UDRF.

Definition at line 174 of file ra8_spi_regs.h.

ra8_spsrc_mask_t

enum ra8_spsrc_mask_t : uint32_t

SPSRC (status clear, write-1-to-clear) masks.

HUM Ch 43.2.13 p 2905.

Enumerator
k_ra8_spsrc_mask_spdrfc	RA8 spsrc mask spdrfc.
k_ra8_spsrc_mask_ovrfc	RA8 spsrc mask ovrfc.
k_ra8_spsrc_mask_modfc	RA8 spsrc mask modfc.
k_ra8_spsrc_mask_perfc	RA8 spsrc mask perfc.
k_ra8_spsrc_mask_udrfc	RA8 spsrc mask udrfc.
k_ra8_spsrc_mask_sptefc	RA8 spsrc mask sptefc.
k_ra8_spsrc_mask_cendfc	RA8 spsrc mask cendfc.
k_ra8_spsrc_mask_sprfc	RA8 spsrc mask sprfc.
k_ra8_spsrc_mask_all	Clear every flag at once.

Definition at line 191 of file ra8_spi_regs.h.

Function Documentation

ra8_spi()

volatile r_spi_regs_t * ra8_spi ( uint8_t channel )

inlinestatic

Get pointer to SPI_B channel channel (0..1).

Parameters

[in]

channel

Channel index, must be < k_ra8_spi_primary_count.

Returns

Volatile pointer to the channel register window, or nullptr for an out-of-range channel.

Precondition

channel encoded as uint8_t (0..255).

Caller has enabled the SPI MSTP gate before any RW access.

Postcondition

No side effect on the register block.

Note

Thread-safe (pure pointer arithmetic, no shared state).

Since

0.1.0

Definition at line 341 of file ra8_spi_regs.h.

References k_ra8_spi0_base_addr, k_ra8_spi_channel_stride, and k_ra8_spi_primary_count.

Referenced by internal_xfer_common(), ra8_spi_b_target_init(), ra8_spi_b_target_xfer(), ra8_spi_clear_errors(), ra8_spi_controller_init(), ra8_spi_deinit(), ra8_spi_enter_stop(), ra8_spi_get_errors(), ra8_spi_init(), ra8_spi_read_dma(), ra8_spi_set_clock(), ra8_spi_write_dma(), and ra8_spi_xfer8().