ra8_spi_b_target.c

Go to the documentation of this file.

 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_spi.h"
#include "ra8_spi_regs.h"
 
static const char* s_tag = "SPI_B_TGT";
 
/* =============================================================================
 * Constants
 * =============================================================================
 */

static const ra8_mstp_t s_spi_mstp_table[k_ra8_spi_b_channel_count] = {
  k_ra8_mstp_spi0,
  k_ra8_mstp_spi1,
};

typedef enum : uint32_t {
  k_spi_b_target_poll_limit = 200000U, 
} ra8_spi_b_target_poll_t;
 
/* =============================================================================
 * Internal helpers
 * =============================================================================
 */

RA8_INTERNAL static ra8_err_t internal_target_wait_spsr(volatile r_spi_regs_t* reg,
                                                        uint32_t               flag_mask)
{
  /* Bounded busy-poll of SPSR. On the host test build the ra8_hw_err MMIO fault
   * seam (ra8_fake_mmio_*) drives this real loop to succeed-after-N or to time out,
   * so both the success and timeout legs are exercised on host (T1-01) rather
   * than compiled out behind an RA8_OFF_TARGET short-circuit. On target it is
   * a plain register spin with a fixed iteration bound. */
  /* HUM Ch 43.2.9 "SPSR : SPI Status Register" p 2898 */
  return ra8_hw_wait_flag_set32(&reg->SPSR, flag_mask, (uint32_t)k_spi_b_target_poll_limit);
}

RA8_INTERNAL static uint32_t internal_target_spcr(void)
{
  uint32_t v = 0U;
  /* SPCR.MSTR (bit 30) is NOT set -- Peripheral (Target) mode. */
  /* SPCR.SCKASE (bit 12) is NOT set -- valid in controller mode only. */
  v |= (uint32_t)k_ra8_spcr_mask_spe;    /* SPI Function Enable.        */
  v |= (uint32_t)k_ra8_spcr_mask_modfen; /* Mode Fault Error Detection. */
  return v;
}

RA8_INTERNAL static uint32_t internal_spcmd_target(const ra8_spi_cfg_t* cfg)
{
  uint32_t v = 0U;
  switch (cfg->mode) {
    case k_ra8_spi_mode_1:
      v |= (uint32_t)k_ra8_spcmd_mask_cpha;
      break;
    case k_ra8_spi_mode_2:
      v |= (uint32_t)k_ra8_spcmd_mask_cpol;
      break;
    case k_ra8_spi_mode_3:
      v |= (uint32_t)k_ra8_spcmd_mask_cpha;
      v |= (uint32_t)k_ra8_spcmd_mask_cpol;
      break;
    case k_ra8_spi_mode_0:
    default:
      break;
  }
  if (cfg->lsb_first) {
    v |= (uint32_t)k_ra8_spcmd_mask_lsbf;
  }
  /* 8-bit frame. */
  v |= ((uint32_t)k_ra8_spcmd_spb_8bit << k_ra8_spcmd_bit_spb_lo) & k_ra8_spcmd_mask_spb;
  return v;
}

RA8_INTERNAL static void internal_target_program_regs(volatile r_spi_regs_t* reg,
                                                      const ra8_spi_cfg_t*   cfg)
{
  /* HUM Ch 43.2.13 "SPSRC : SPI Status Clear Register" p 2905 */
  reg->SPSRC = (uint32_t)k_ra8_spsrc_mask_all;
 
  /* SPBR=0 in target mode: clock is external; field ignored by HW. */
  /* HUM Ch 43.2.6 "SPCR3 : SPI Control Register 3" p 2891 */
  reg->SPCR3 = 0U;
 
  /* HUM Ch 43.2.3 "SPDECR : SPI Delay Control Register" p 2883 */
  reg->SPDECR = 0U;
 
  /* No loopback in target mode. SPCR2 must be written while SPE=0. */
  /* HUM Ch 43.2.4 "SPCR2 : SPI Control Register 2" p 2889 */
  reg->SPCR2 = 0U;
 
  /* HUM Ch 43.2.7 "SPCMDm : SPI Command Register" p 2893 */
  reg->SPCMD[0] = internal_spcmd_target(cfg);
 
  /* HUM Ch 43.2.10 "SPDCR : SPI Data Control Register" p 2896 */
  reg->SPDCR  = 0U;
  reg->SPDCR2 = 0U;
 
  /* HUM Ch 43.2.14 "SPFCR : SPI FIFO Clear Register" p 2906 */
  reg->SPFCR = (uint32_t)k_ra8_spfcr_mask_spfrst;
 
  /* Re-clear status after FIFO reset in case SPRF was set by flush. */
  /* HUM Ch 43.2.13 "SPSRC : SPI Status Clear Register" p 2905 */
  reg->SPSRC = (uint32_t)k_ra8_spsrc_mask_all;
}
 
/* =============================================================================
 * Public API -- definitions (declarations + Doxygen live in ra8_spi.h)
 * =============================================================================
 */
 
ra8_err_t ra8_spi_b_target_init(uint8_t channel, const ra8_spi_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_tag, "target_init: cfg");
  if (channel >= (uint8_t)k_ra8_spi_b_channel_count) {
    return k_ra8_err_invalid_arg;
  }
  volatile r_spi_regs_t* reg = ra8_spi(channel);
  if (reg == nullptr) {           /* GCOVR_EXCL_BR_LINE -- bounded channel yields non-null reg */
    return k_ra8_err_invalid_arg; /* GCOVR_EXCL_LINE -- bounded channel yields non-null reg    */
  }
  /* HUM Ch 11.2.7 "MSTPCRB : Module Stop Control Register B" p 444 */
  const ra8_err_t mst_err = ra8_mstp_enable(s_spi_mstp_table[channel]);
  /* GCOVR_EXCL_BR_START -- MSTP HW readback */
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "target_init: mstp");
  /* GCOVR_EXCL_BR_STOP */
 
  /* Disable (SPE=0) before reprogramming. */
  /* HUM Ch 43.2.4 "SPCR : SPI Control Register" p 2884 */
  reg->SPCR = 0U;
 
  internal_target_program_regs(reg, cfg);
 
  /* Enable SPI in target/peripheral mode: MSTR=0, MODFEN=1, SPE=1. */
  /* HUM Ch 43.2.4 "SPCR : SPI Control Register" p 2884 */
  /* HUM Ch 43.3.14 "SPI peripheral-mode operation" p 2912 */
  reg->SPCR = internal_target_spcr();
 
  ra8_log_info_val(s_tag, "target_init channel", (uint32_t)channel);
  return k_ra8_ok;
}
 
ra8_err_t ra8_spi_b_target_xfer(uint8_t channel, uint8_t tx, uint8_t* rx)
{
  volatile r_spi_regs_t* reg = ra8_spi(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "target_xfer: channel out of range");
 
  /* Wait until the TX buffer is empty (safe to pre-load response). */
  /* HUM Ch 43.2.9 "SPSR : SPI Status Register" p 2898 */
  ra8_err_t err = internal_target_wait_spsr(reg, (uint32_t)k_ra8_spsr_mask_sptef);
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Pre-load the response byte -- shifted out on CIPO when the external */
  /* controller asserts CS and provides RSPCK. */
  /* HUM Ch 43.2.2 "SPDR : SPI Data Register" p 2881 */
  reg->SPDR = (uint32_t)tx;
 
  /* Clear TX-empty flag (write-1-to-clear). */
  /* HUM Ch 43.2.13 "SPSRC : SPI Status Clear Register" p 2905 */
  reg->SPSRC = (uint32_t)k_ra8_spsrc_mask_sptefc;
 
  /* Wait for the external controller to complete a full frame (SPRF). */
  /* HUM Ch 43.2.9 "SPSR : SPI Status Register" p 2898 */
  err = internal_target_wait_spsr(reg, (uint32_t)k_ra8_spsr_mask_sprf);
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Drain the byte received on COPI from the RX FIFO front-end. */
  /* HUM Ch 43.2.2 "SPDR : SPI Data Register" p 2881 */
  const uint8_t received = (uint8_t)reg->SPDR;
 
  /* Clear RX-full flag. */
  /* HUM Ch 43.2.13 "SPSRC : SPI Status Clear Register" p 2905 */
  reg->SPSRC = (uint32_t)k_ra8_spsrc_mask_sprfc;
 
  if (rx != nullptr) {
    *rx = received;
  }
  return k_ra8_ok;
}