ra8_spi_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_spi0_base_addr = 0x4035C000UL, 
  k_ra8_spi1_base_addr = 0x4035C100UL, 
} ra8_spi_addr_t;

typedef enum : uint16_t {
  k_ra8_spi_primary_count  = 2U,     
  k_ra8_spi_channel_stride = 0x100U, 
  k_ra8_spi_cmd_count      = 8U,     
  k_ra8_spi_block_size     = 0x70U,  
} ra8_spi_limits_t;

typedef struct {
  volatile uint32_t SPDR;          
  volatile uint32_t SPDECR;        
  volatile uint32_t SPCR;          
  volatile uint32_t SPCR2;         
  volatile uint32_t SPCR3;         
  volatile uint32_t SPCMD[8];      
  volatile uint32_t _reserved0[3]; 
  volatile uint32_t SPDCR;         
  volatile uint32_t SPDCR2;        
  volatile uint32_t _reserved1[2]; 
  volatile uint32_t SPSR;          
  volatile uint32_t _reserved2;    
  volatile uint32_t SPTFSR;        
  volatile uint32_t SPRFSR;        
  volatile uint32_t SPPSR;         
  volatile uint32_t _reserved3;    
  volatile uint32_t SPSRC;         
  volatile uint32_t SPFCR;         
} r_spi_regs_t;

typedef enum : uint8_t {
  k_ra8_spcr_bit_spe     = 0U,  
  k_ra8_spcr_bit_sppe    = 8U,  
  k_ra8_spcr_bit_spoe    = 9U,  
  k_ra8_spcr_bit_pte     = 11U, 
  k_ra8_spcr_bit_sckase  = 12U, 
  k_ra8_spcr_bit_bfds    = 13U, 
  k_ra8_spcr_bit_modfen  = 14U, 
  k_ra8_spcr_bit_speie   = 16U, 
  k_ra8_spcr_bit_sprie   = 17U, 
  k_ra8_spcr_bit_spiie   = 18U, 
  k_ra8_spcr_bit_spdres  = 19U, 
  k_ra8_spcr_bit_sptie   = 20U, 
  k_ra8_spcr_bit_cendie  = 21U, 
  k_ra8_spcr_bit_spms    = 24U, 
  k_ra8_spcr_bit_spfrf   = 25U, 
  k_ra8_spcr_bit_txmd_lo = 28U, 
  k_ra8_spcr_bit_txmd_hi = 29U, 
  k_ra8_spcr_bit_mstr    = 30U, 
  k_ra8_spcr_bit_bpen    = 31U, 
} ra8_spcr_bit_t;

typedef enum : uint32_t {
  k_ra8_spcr_mask_spe    = 0x00000001UL, 
  k_ra8_spcr_mask_modfen = 0x00004000UL, 
  k_ra8_spcr_mask_speie  = 0x00010000UL, 
  k_ra8_spcr_mask_sprie  = 0x00020000UL, 
  k_ra8_spcr_mask_sptie  = 0x00100000UL, 
  k_ra8_spcr_mask_cendie = 0x00200000UL, 
  k_ra8_spcr_mask_sckase = 0x00001000UL, 
  k_ra8_spcr_mask_mstr   = 0x40000000UL, 
  k_ra8_spcr_mask_txmd   = 0x30000000UL, 
} ra8_spcr_mask_t;

typedef enum : uint8_t {
  k_ra8_spsr_bit_spdrf = 23U, 
  k_ra8_spsr_bit_ovrf  = 24U, 
  k_ra8_spsr_bit_idlnf = 25U, 
  k_ra8_spsr_bit_modf  = 26U, 
  k_ra8_spsr_bit_perf  = 27U, 
  k_ra8_spsr_bit_udrf  = 28U, 
  k_ra8_spsr_bit_sptef = 29U, 
  k_ra8_spsr_bit_cendf = 30U, 
  k_ra8_spsr_bit_sprf  = 31U, 
} ra8_spsr_bit_t;

typedef enum : uint32_t {
  k_ra8_spsr_mask_spdrf = 0x00800000UL, 
  k_ra8_spsr_mask_ovrf  = 0x01000000UL, 
  k_ra8_spsr_mask_idlnf = 0x02000000UL, 
  k_ra8_spsr_mask_modf  = 0x04000000UL, 
  k_ra8_spsr_mask_perf  = 0x08000000UL, 
  k_ra8_spsr_mask_udrf  = 0x10000000UL, 
  k_ra8_spsr_mask_sptef = 0x20000000UL, 
  k_ra8_spsr_mask_cendf = 0x40000000UL, 
  k_ra8_spsr_mask_sprf  = 0x80000000UL, 
  k_ra8_spsr_mask_errs  = 0x1D000000UL, 
} ra8_spsr_mask_t;

typedef enum : uint32_t {
  k_ra8_spsrc_mask_spdrfc = 0x00800000UL, 
  k_ra8_spsrc_mask_ovrfc  = 0x01000000UL, 
  k_ra8_spsrc_mask_modfc  = 0x04000000UL, 
  k_ra8_spsrc_mask_perfc  = 0x08000000UL, 
  k_ra8_spsrc_mask_udrfc  = 0x10000000UL, 
  k_ra8_spsrc_mask_sptefc = 0x20000000UL, 
  k_ra8_spsrc_mask_cendfc = 0x40000000UL, 
  k_ra8_spsrc_mask_sprfc  = 0x80000000UL, 
  k_ra8_spsrc_mask_all    = 0xFD800000UL, 
} ra8_spsrc_mask_t;

typedef enum : uint8_t {
  k_ra8_spcmd_bit_cpha   = 0U,  
  k_ra8_spcmd_bit_cpol   = 1U,  
  k_ra8_spcmd_bit_brdv0  = 2U,  
  k_ra8_spcmd_bit_brdv1  = 3U,  
  k_ra8_spcmd_bit_sslkp  = 7U,  
  k_ra8_spcmd_bit_lsbf   = 12U, 
  k_ra8_spcmd_bit_spnden = 13U, 
  k_ra8_spcmd_bit_slnden = 14U, 
  k_ra8_spcmd_bit_sckden = 15U, 
  k_ra8_spcmd_bit_spb_lo = 16U, 
} ra8_spcmd_bit_t;

typedef enum : uint32_t {
  k_ra8_spcmd_mask_cpha   = 0x00000001UL, 
  k_ra8_spcmd_mask_cpol   = 0x00000002UL, 
  k_ra8_spcmd_mask_brdv   = 0x0000000CUL, 
  k_ra8_spcmd_mask_sslkp  = 0x00000080UL, 
  k_ra8_spcmd_mask_lsbf   = 0x00001000UL, 
  k_ra8_spcmd_mask_spnden = 0x00002000UL, 
  k_ra8_spcmd_mask_slnden = 0x00004000UL, 
  k_ra8_spcmd_mask_sckden = 0x00008000UL, 
  k_ra8_spcmd_mask_spb    = 0x001F0000UL, 
  k_ra8_spcmd_mask_ssla   = 0x07000000UL, 
} ra8_spcmd_mask_t;

typedef enum : uint8_t {
  k_ra8_spcmd_spb_8bit  = 0x07U, 
  k_ra8_spcmd_spb_16bit = 0x0FU, 
  k_ra8_spcmd_spb_32bit = 0x1FU, 
} ra8_spcmd_spb_t;

typedef enum : uint8_t {
  k_ra8_spcr3_bit_ssl0p = 0U,  
  k_ra8_spcr3_bit_ssl1p = 1U,  
  k_ra8_spcr3_bit_ssl2p = 2U,  
  k_ra8_spcr3_bit_ssl3p = 3U,  
  k_ra8_spcr3_bit_spbr  = 8U,  
  k_ra8_spcr3_bit_spsln = 24U, 
} ra8_spcr3_bit_t;

typedef enum : uint32_t {
  k_ra8_spcr3_mask_ssl_pol = 0x0000000FUL, 
  k_ra8_spcr3_mask_spbr    = 0x0000FF00UL, 
  k_ra8_spcr3_mask_spsln   = 0x07000000UL, 
} ra8_spcr3_mask_t;

typedef enum : uint8_t {
  k_ra8_spbr_max = 0xFFU, 
} ra8_spcr3_misc_t;

typedef enum : uint32_t {
  k_ra8_spfcr_mask_spfrst = 0x00000001UL, 
} ra8_spfcr_mask_t;

typedef enum : uint32_t {
  k_ra8_spcr2_mask_splp  = 0x00010000UL, 
  k_ra8_spcr2_mask_splp2 = 0x00020000UL, 
  k_ra8_spcr2_mask_moife = 0x00200000UL, 
  k_ra8_spcr2_mask_moifv = 0x00100000UL, 
} ra8_spcr2_mask_t;

typedef enum : uint32_t {
  k_ra8_sppsr_mask_speps = 0x00000001UL, 
} ra8_sppsr_mask_t;

typedef enum : uint8_t {
  k_ra8_spi_b_channel_count = 2U, 
} ra8_spi_b_channel_count_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_spi_regs_t* ra8_spi(uint8_t channel)
{
  if ((uint16_t)channel >= k_ra8_spi_primary_count) {
    return nullptr;
  }
  return (volatile r_spi_regs_t*)(k_ra8_spi0_base_addr +
                                  ((uintptr_t)channel * (uintptr_t)k_ra8_spi_channel_stride));
}
 
#ifdef __cplusplus
}
#endif