r_spi_regs_t Struct Reference

SPI_B register-window mirror (matches FSP R_SPI_B0_Type, 0x70 bytes). More...

#include <ra8_spi_regs.h>

Data Fields
volatile uint32_t	SPDR
	+0x00 SPI Data Register.
volatile uint32_t	SPDECR
	+0x04 SPI Delay Control Register.
volatile uint32_t	SPCR
	+0x08 SPI Control Register 1.
volatile uint32_t	SPCR2
	+0x0C SPI Control Register 2.
volatile uint32_t	SPCR3
	+0x10 SPI Control Register 3.
volatile uint32_t	SPCMD [8]
	+0x14..0x30 Command Registers SPCMD0..7.
volatile uint32_t	_reserved0 [3]
	+0x34..0x3C reserved.
volatile uint32_t	SPDCR
	+0x40 SPI Data Control Register.
volatile uint32_t	SPDCR2
	+0x44 SPI Data Control Register 2.
volatile uint32_t	_reserved1 [2]
	+0x48..0x4C reserved.
volatile uint32_t	SPSR
	+0x50 SPI Status Register.
volatile uint32_t	_reserved2
	+0x54 reserved.
volatile uint32_t	SPTFSR
	+0x58 TX FIFO Status Register.
volatile uint32_t	SPRFSR
	+0x5C RX FIFO Status Register.
volatile uint32_t	SPPSR
	+0x60 SPI Polling Register.
volatile uint32_t	_reserved3
	+0x64 reserved.
volatile uint32_t	SPSRC
	+0x68 SPI Status Clear Register.
volatile uint32_t	SPFCR
	+0x6C SPI FIFO Clear Register.

Detailed Description

SPI_B register-window mirror (matches FSP R_SPI_B0_Type, 0x70 bytes).

Every register is 32-bit. The layout is taken verbatim from R7KA8D2KF_core0.h, with the FSP nested anonymous unions / bit structs flattened to plain uint32_t words. Bit-level access goes through the masks/positions enums in this header instead of named bit-fields so layout is debugger-stable.

Definition at line 91 of file ra8_spi_regs.h.

Field Documentation

_reserved0

volatile uint32_t r_spi_regs_t::_reserved0[3]

+0x34..0x3C reserved.

Definition at line 98 of file ra8_spi_regs.h.

_reserved1

volatile uint32_t r_spi_regs_t::_reserved1[2]

+0x48..0x4C reserved.

Definition at line 101 of file ra8_spi_regs.h.

_reserved2

volatile uint32_t r_spi_regs_t::_reserved2

+0x54 reserved.

Definition at line 103 of file ra8_spi_regs.h.

_reserved3

volatile uint32_t r_spi_regs_t::_reserved3

+0x64 reserved.

Definition at line 107 of file ra8_spi_regs.h.

SPCMD

volatile uint32_t r_spi_regs_t::SPCMD[8]

+0x14..0x30 Command Registers SPCMD0..7.

Definition at line 97 of file ra8_spi_regs.h.

Referenced by internal_apply_bit_width(), internal_spi_program_regs(), and internal_target_program_regs().

SPCR

volatile uint32_t r_spi_regs_t::SPCR

+0x08 SPI Control Register 1.

Definition at line 94 of file ra8_spi_regs.h.

Referenced by ra8_spi_b_target_init(), ra8_spi_deinit(), ra8_spi_enter_stop(), and ra8_spi_init().

SPCR2

volatile uint32_t r_spi_regs_t::SPCR2

+0x0C SPI Control Register 2.

Definition at line 95 of file ra8_spi_regs.h.

Referenced by internal_spi_program_regs(), and internal_target_program_regs().

SPCR3

volatile uint32_t r_spi_regs_t::SPCR3

+0x10 SPI Control Register 3.

Definition at line 96 of file ra8_spi_regs.h.

Referenced by internal_spi_program_regs(), internal_target_program_regs(), and ra8_spi_set_clock().

SPDCR

volatile uint32_t r_spi_regs_t::SPDCR

+0x40 SPI Data Control Register.

Definition at line 99 of file ra8_spi_regs.h.

Referenced by internal_spi_program_regs(), and internal_target_program_regs().

SPDCR2

volatile uint32_t r_spi_regs_t::SPDCR2

+0x44 SPI Data Control Register 2.

Definition at line 100 of file ra8_spi_regs.h.

Referenced by internal_spi_program_regs(), and internal_target_program_regs().

SPDECR

volatile uint32_t r_spi_regs_t::SPDECR

+0x04 SPI Delay Control Register.

Definition at line 93 of file ra8_spi_regs.h.

Referenced by internal_spi_program_regs(), and internal_target_program_regs().

SPDR

volatile uint32_t r_spi_regs_t::SPDR

+0x00 SPI Data Register.

Definition at line 92 of file ra8_spi_regs.h.

Referenced by internal_pop_unit(), internal_push_unit(), ra8_spi_b_target_xfer(), ra8_spi_read_dma(), ra8_spi_write_dma(), and ra8_spi_xfer8().

SPFCR

volatile uint32_t r_spi_regs_t::SPFCR

+0x6C SPI FIFO Clear Register.

Definition at line 109 of file ra8_spi_regs.h.

Referenced by internal_spi_program_regs(), and internal_target_program_regs().

SPPSR

volatile uint32_t r_spi_regs_t::SPPSR

+0x60 SPI Polling Register.

Definition at line 106 of file ra8_spi_regs.h.

SPRFSR

volatile uint32_t r_spi_regs_t::SPRFSR

+0x5C RX FIFO Status Register.

Definition at line 105 of file ra8_spi_regs.h.

SPSR

volatile uint32_t r_spi_regs_t::SPSR

+0x50 SPI Status Register.

Definition at line 102 of file ra8_spi_regs.h.

Referenced by internal_target_wait_spsr(), internal_wait_spsr(), and ra8_spi_get_errors().

SPSRC

volatile uint32_t r_spi_regs_t::SPSRC

+0x68 SPI Status Clear Register.

Definition at line 108 of file ra8_spi_regs.h.

Referenced by internal_spi_program_regs(), internal_target_program_regs(), internal_xfer_common(), ra8_spi_b_target_xfer(), ra8_spi_clear_errors(), and ra8_spi_xfer8().

SPTFSR

volatile uint32_t r_spi_regs_t::SPTFSR

+0x58 TX FIFO Status Register.

Definition at line 104 of file ra8_spi_regs.h.

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The documentation for this struct was generated from the following file:

• libs/ra8_hal/inc/ra8_spi_regs.h