ra8_spi_b_dma.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_cache.h"
#include "ra8_check.h"
#include "ra8_dma.h"
#include "ra8_dmac.h"
#include "ra8_err.h"
#include "ra8_spi.h"
#include "ra8_spi_regs.h"
 
static const char* s_tag = "SPI_B";

RA8_INTERNAL static ra8_err_t internal_dma_args_ok(uint8_t channel, uint16_t len)
{
  ra8_err_t err = k_ra8_ok;
  if (channel >= k_ra8_spi_b_channel_count) {
    err = k_ra8_err_invalid_arg;
  }
  if (len == 0U) {
    err = k_ra8_err_invalid_arg;
  }
  return err;
}
 
/* =============================================================================
 * DMA TX / RX
 * =============================================================================
 */

typedef struct {
  void*                 rx_buf;           
  uint16_t              rx_len;           
  ra8_dma_complete_fn_t user_on_complete; 
  void*                 user_ctx;         
} ra8_spi_dma_rx_ctx_t;

static ra8_spi_dma_rx_ctx_t s_spi_dma_rx_ctx[k_ra8_spi_b_channel_count];

RA8_INTERNAL static uint32_t internal_round_up_to_cache_line(uint32_t bytes)
{
  if (bytes == 0U) {
    return 0U;
  }
  const uint32_t line = ra8_cache_dcache_line_bytes();
  if (line == 0U) { /* GCOVR_EXCL_BR_LINE -- cache line size fixed nonzero by architecture */
    return bytes;   /* GCOVR_EXCL_LINE -- cache line size fixed nonzero by architecture    */
  }
  return (bytes + (line - 1U)) & ~(line - 1U);
}

RA8_INTERNAL static void internal_spi_dma_rx_complete(void* ctx)
{
  ra8_spi_dma_rx_ctx_t* rxc = (ra8_spi_dma_rx_ctx_t*)ctx;
  if (rxc == nullptr) { /* GCOVR_EXCL_BR_LINE -- callback set by internal caller, never null */
    return;             /* GCOVR_EXCL_LINE -- callback set by internal caller, never null    */
  }
  ra8_cache_dcache_invalidate_by_addr(rxc->rx_buf, internal_round_up_to_cache_line(rxc->rx_len));
  if (rxc->user_on_complete != nullptr) {
    rxc->user_on_complete(rxc->user_ctx);
  }
}
 
ra8_err_t ra8_spi_write_dma(uint8_t               channel,
                            const uint8_t*        data,
                            uint16_t              len,
                            ra8_dma_complete_fn_t on_complete,
                            void*                 ctx,
                            uint8_t*              out_dma_channel)
{
  RA8_CHECK_NULL_PTR(data, s_tag, "spi_write_dma: data");
  RA8_CHECK_NULL_PTR(out_dma_channel, s_tag, "spi_write_dma: out_dma_channel");
  const ra8_err_t args_ok = internal_dma_args_ok(channel, len);
  if (args_ok != k_ra8_ok) {
    return args_ok;
  }
  volatile r_spi_regs_t* reg = ra8_spi(channel);
  if (reg == nullptr) {           /* GCOVR_EXCL_BR_LINE -- internal caller proves reg non-null */
    return k_ra8_err_invalid_arg; /* GCOVR_EXCL_LINE -- internal caller proves reg non-null    */
  }
  /* Cache coherency: the SPI DMA reads CPU-written 'data' straight from
   * memory, so flush any dirty lines covering it before the engine starts.
   * No-op when the D-cache is disabled. */
  ra8_cache_dcache_clean_by_addr(data, internal_round_up_to_cache_line(len));
  /* Byte-wide DMA writes target the low byte of SPDR; wider-frame
   * streaming is a future wave. */
  /* HUM Ch 43.2.2 "SPDR : SPI Data Register" p 2881 */
  ra8_dma_request_t req = {};
  req.src_addr          = (uintptr_t)data;
  req.dst_addr          = (uintptr_t)&reg->SPDR;
  req.count             = len;
  req.width             = k_ra8_dmac_width_byte;
  req.src_inc           = true;
  req.dst_inc           = false;
  req.trigger           = (ra8_elc_event_t)0;
  req.on_complete       = on_complete;
  req.ctx               = ctx;
  return ra8_dma_request(&req, out_dma_channel);
}
 
ra8_err_t ra8_spi_read_dma(uint8_t               channel,
                           uint8_t*              out_buf,
                           uint16_t              len,
                           ra8_dma_complete_fn_t on_complete,
                           void*                 ctx,
                           uint8_t*              out_dma_channel)
{
  RA8_CHECK_NULL_PTR(out_buf, s_tag, "spi_read_dma: out_buf");
  RA8_CHECK_NULL_PTR(out_dma_channel, s_tag, "spi_read_dma: out_dma_channel");
  const ra8_err_t args_ok = internal_dma_args_ok(channel, len);
  if (args_ok != k_ra8_ok) {
    return args_ok;
  }
  volatile r_spi_regs_t* reg = ra8_spi(channel);
  if (reg == nullptr) {           /* GCOVR_EXCL_BR_LINE -- internal caller proves reg non-null */
    return k_ra8_err_invalid_arg; /* GCOVR_EXCL_LINE -- internal caller proves reg non-null    */
  }
  /* Cache coherency: the RX DMA writes out_buf straight to memory. Wrap the
   * caller's completion so the CPU invalidates those lines once the transfer
   * is known-complete -- before it (or the caller's callback) reads them.
   * The wrapper is the only known-complete hook in this asynchronous path
   * (ra8_dma_request returns immediately; completion fires from the DMAC
   * transfer-end ISR). No-op when the D-cache is disabled. */
  ra8_spi_dma_rx_ctx_t* rxc = &s_spi_dma_rx_ctx[channel];
  rxc->rx_buf               = out_buf;
  rxc->rx_len               = len;
  rxc->user_on_complete     = on_complete;
  rxc->user_ctx             = ctx;
 
  /* HUM Ch 43.2.2 "SPDR : SPI Data Register" p 2881 */
  ra8_dma_request_t req = {};
  req.src_addr          = (uintptr_t)&reg->SPDR;
  req.dst_addr          = (uintptr_t)out_buf;
  req.count             = len;
  req.width             = k_ra8_dmac_width_byte;
  req.src_inc           = false;
  req.dst_inc           = true;
  req.trigger           = (ra8_elc_event_t)0;
  req.on_complete       = internal_spi_dma_rx_complete;
  req.ctx               = rxc;
  return ra8_dma_request(&req, out_dma_channel);
}