Capture Engine Unit (CEU) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_glcdc_regs.h"

Include dependency graph for ra8_ceu_regs.h:

This graph shows which files directly or indirectly include this file:

Enumerations
enum	ra8_ceu_plane_off_t : uint16_t { k_ra8_ceu_plane_a_off = 0x0000U , k_ra8_ceu_plane_b_off = 0x1000U , k_ra8_ceu_plane_mirror_off = 0x2000U }
	Plane stride between Plane A, Plane B, and the mirror view. More...
enum	ra8_ceu_off_t : uint16_t { k_ra8_ceu_off_capsr = 0x0000U , k_ra8_ceu_off_capcr = 0x0004U , k_ra8_ceu_off_camcr = 0x0008U , k_ra8_ceu_off_cmcyr = 0x000CU , k_ra8_ceu_off_camor = 0x0010U , k_ra8_ceu_off_capwr = 0x0014U , k_ra8_ceu_off_caifr = 0x0018U , k_ra8_ceu_off_crcntr = 0x0028U , k_ra8_ceu_off_crcmpr = 0x002CU , k_ra8_ceu_off_cflcr = 0x0030U , k_ra8_ceu_off_cfszr = 0x0034U , k_ra8_ceu_off_cdwdr = 0x0038U , k_ra8_ceu_off_cdayr = 0x003CU , k_ra8_ceu_off_cdacr = 0x0040U , k_ra8_ceu_off_cdbyr = 0x0044U , k_ra8_ceu_off_cdbcr = 0x0048U , k_ra8_ceu_off_cbdsr = 0x004CU , k_ra8_ceu_off_cfwcr = 0x005CU , k_ra8_ceu_off_clfcr = 0x0060U , k_ra8_ceu_off_cdocr = 0x0064U , k_ra8_ceu_off_ceier = 0x0070U , k_ra8_ceu_off_cetcr = 0x0074U , k_ra8_ceu_off_cstsr = 0x007CU , k_ra8_ceu_off_cdssr = 0x0084U , k_ra8_ceu_off_cdayr2 = 0x0090U , k_ra8_ceu_off_cdacr2 = 0x0094U , k_ra8_ceu_off_cdbyr2 = 0x0098U , k_ra8_ceu_off_cdbcr2 = 0x009CU }
	Plane A register offsets inside the CEU window. More...
enum	ra8_ceu_capsr_bit_t : uint8_t { k_ra8_ceu_capsr_bit_ce = 0U , k_ra8_ceu_capsr_bit_cpkil = 16U }
	CAPSR (offset 0x0000) bit positions. More...
enum	ra8_ceu_capsr_mask_t : uint32_t { k_ra8_ceu_capsr_mask_ce = (1UL << 0) , k_ra8_ceu_capsr_mask_cpkil = (1UL << 16) }
	CAPSR bit masks (full 32-bit register). More...
enum	ra8_ceu_capcr_shift_t : uint8_t { k_ra8_ceu_capcr_shift_ctncp = 16U , k_ra8_ceu_capcr_shift_mtcm = 20U , k_ra8_ceu_capcr_shift_fdrp = 24U }
	CAPCR (offset 0x0004) field shifts. More...
enum	ra8_ceu_capcr_mask_t : uint32_t { k_ra8_ceu_capcr_mask_ctncp = (1UL << 16) , k_ra8_ceu_capcr_mask_mtcm = (3UL << 20) , k_ra8_ceu_capcr_mask_fdrp = (0xFFUL << 24) }
	CAPCR field masks. More...
enum	ra8_ceu_camcr_shift_t : uint8_t { k_ra8_ceu_camcr_shift_hdpol = 0U , k_ra8_ceu_camcr_shift_vdpol = 1U , k_ra8_ceu_camcr_shift_jpg = 4U , k_ra8_ceu_camcr_shift_dtary = 8U , k_ra8_ceu_camcr_shift_dtif = 12U , k_ra8_ceu_camcr_shift_fldpol = 16U , k_ra8_ceu_camcr_shift_dsel = 24U , k_ra8_ceu_camcr_shift_fldsel = 25U , k_ra8_ceu_camcr_shift_hdsel = 26U , k_ra8_ceu_camcr_shift_vdsel = 27U }
	CAMCR (offset 0x0008) field shifts. More...
enum	ra8_ceu_camcr_mask_t : uint32_t { k_ra8_ceu_camcr_mask_hdpol = (1UL << 0) , k_ra8_ceu_camcr_mask_vdpol = (1UL << 1) , k_ra8_ceu_camcr_mask_jpg = (3UL << 4) , k_ra8_ceu_camcr_mask_dtary = (3UL << 8) , k_ra8_ceu_camcr_mask_dtif = (1UL << 12) , k_ra8_ceu_camcr_mask_fldpol = (1UL << 16) , k_ra8_ceu_camcr_mask_dsel = (1UL << 24) , k_ra8_ceu_camcr_mask_fldsel = (1UL << 25) , k_ra8_ceu_camcr_mask_hdsel = (1UL << 26) , k_ra8_ceu_camcr_mask_vdsel = (1UL << 27) }
	CAMCR field masks. More...
enum	ra8_ceu_cmcyr_shift_t : uint8_t { k_ra8_ceu_cmcyr_shift_hcyl = 0U , k_ra8_ceu_cmcyr_shift_vcyl = 16U }
	CMCYR (offset 0x000C) field shifts. More...
enum	ra8_ceu_cmcyr_mask_t : uint32_t { k_ra8_ceu_cmcyr_mask_hcyl = 0x00003FFFUL , k_ra8_ceu_cmcyr_mask_vcyl = 0x3FFF0000UL }
	CMCYR field masks. More...
enum	ra8_ceu_camor_shift_t : uint8_t { k_ra8_ceu_camor_shift_hofst = 0U , k_ra8_ceu_camor_shift_vofst = 16U }
	CAMOR (offset 0x0010) field shifts. More...
enum	ra8_ceu_camor_mask_t : uint32_t { k_ra8_ceu_camor_mask_hofst = 0x00001FFFUL , k_ra8_ceu_camor_mask_vofst = 0x0FFF0000UL }
	CAMOR field masks. More...
enum	ra8_ceu_capwr_shift_t : uint8_t { k_ra8_ceu_capwr_shift_hwdth = 0U , k_ra8_ceu_capwr_shift_vwdth = 16U }
	CAPWR (offset 0x0014) field shifts. More...
enum	ra8_ceu_capwr_mask_t : uint32_t { k_ra8_ceu_capwr_mask_hwdth = 0x00001FFFUL , k_ra8_ceu_capwr_mask_vwdth = 0x0FFF0000UL }
	CAPWR field masks. More...
enum	ra8_ceu_caifr_shift_t : uint8_t { k_ra8_ceu_caifr_shift_fci = 0U , k_ra8_ceu_caifr_shift_cim = 4U , k_ra8_ceu_caifr_shift_ifs = 8U }
	CAIFR (offset 0x0018) field shifts. More...
enum	ra8_ceu_caifr_mask_t : uint32_t { k_ra8_ceu_caifr_mask_fci = (3UL << 0) , k_ra8_ceu_caifr_mask_cim = (1UL << 4) , k_ra8_ceu_caifr_mask_ifs = (1UL << 8) }
	CAIFR field masks. More...
enum	ra8_ceu_crcntr_mask_t : uint32_t { k_ra8_ceu_crcntr_mask_rc = (1UL << 0) , k_ra8_ceu_crcntr_mask_rs = (1UL << 1) , k_ra8_ceu_crcntr_mask_rvs = (1UL << 4) }
	CRCNTR (offset 0x0028) bit masks. More...
enum	ra8_ceu_crcmpr_mask_t : uint32_t { k_ra8_ceu_crcmpr_mask_ra = (1UL << 0) }
	CRCMPR (offset 0x002C) bit masks. More...
enum	ra8_ceu_cflcr_shift_t : uint8_t { k_ra8_ceu_cflcr_shift_hfrac = 0U , k_ra8_ceu_cflcr_shift_hmant = 12U , k_ra8_ceu_cflcr_shift_vfrac = 16U , k_ra8_ceu_cflcr_shift_vmant = 28U }
	CFLCR (offset 0x0030) field shifts. More...
enum	ra8_ceu_cflcr_mask_t : uint32_t { k_ra8_ceu_cflcr_mask_hfrac = 0x00000FFFUL , k_ra8_ceu_cflcr_mask_hmant = 0x0000F000UL , k_ra8_ceu_cflcr_mask_vfrac = 0x0FFF0000UL , k_ra8_ceu_cflcr_mask_vmant = 0xF0000000UL }
	CFLCR field masks. More...
enum	ra8_ceu_cfszr_shift_t : uint8_t { k_ra8_ceu_cfszr_shift_hfclp = 0U , k_ra8_ceu_cfszr_shift_vfclp = 16U }
	CFSZR (offset 0x0034) field shifts. More...
enum	ra8_ceu_cfszr_mask_t : uint32_t { k_ra8_ceu_cfszr_mask_hfclp = 0x00000FFFUL , k_ra8_ceu_cfszr_mask_vfclp = 0x0FFF0000UL }
	CFSZR field masks. More...
enum	ra8_ceu_cdwdr_mask_t : uint32_t { k_ra8_ceu_cdwdr_mask_chdw = 0x00001FFFUL }
	CDWDR (offset 0x0038) bit masks. More...
enum	ra8_ceu_cbdsr_mask_t : uint32_t { k_ra8_ceu_cbdsr_mask_cbvs = 0x007FFFFFUL }
	CBDSR (offset 0x004C) bit masks. More...
enum	ra8_ceu_cfwcr_shift_t : uint8_t { k_ra8_ceu_cfwcr_shift_fwe = 0U , k_ra8_ceu_cfwcr_shift_fwv = 5U }
	CFWCR (offset 0x005C) field shifts. More...
enum	ra8_ceu_cfwcr_mask_t : uint32_t { k_ra8_ceu_cfwcr_mask_fwe = (1UL << 0) , k_ra8_ceu_cfwcr_mask_fwv = 0xFFFFFFE0UL }
	CFWCR field masks. More...
enum	ra8_ceu_clfcr_mask_t : uint32_t { k_ra8_ceu_clfcr_mask_lpf = (1UL << 0) }
	CLFCR (offset 0x0060) bit masks. More...
enum	ra8_ceu_cdocr_shift_t : uint8_t { k_ra8_ceu_cdocr_shift_cobs = 0U , k_ra8_ceu_cdocr_shift_cows = 1U , k_ra8_ceu_cdocr_shift_cols = 2U , k_ra8_ceu_cdocr_shift_cds = 4U , k_ra8_ceu_cdocr_shift_cbe = 16U }
	CDOCR (offset 0x0064) field shifts. More...
enum	ra8_ceu_cdocr_mask_t : uint32_t { k_ra8_ceu_cdocr_mask_cobs = (1UL << 0) , k_ra8_ceu_cdocr_mask_cows = (1UL << 1) , k_ra8_ceu_cdocr_mask_cols = (1UL << 2) , k_ra8_ceu_cdocr_mask_cds = (1UL << 4) , k_ra8_ceu_cdocr_mask_cbe = (1UL << 16) }
	CDOCR field masks. More...
enum	ra8_ceu_cstsr_mask_t : uint32_t { k_ra8_ceu_cstsr_mask_cpton = (1UL << 0) , k_ra8_ceu_cstsr_mask_cpfld = (1UL << 16) , k_ra8_ceu_cstsr_mask_crst = (1UL << 24) }
	CSTSR (offset 0x007C) status bit masks. More...
enum	ra8_ceu_cetcr_mask_t : uint32_t { k_ra8_ceu_evt_cpe = (1UL << 0) , k_ra8_ceu_evt_cfe = (1UL << 1) , k_ra8_ceu_evt_igrw = (1UL << 4) , k_ra8_ceu_evt_hd = (1UL << 8) , k_ra8_ceu_evt_vd = (1UL << 9) , k_ra8_ceu_evt_cpbe1 = (1UL << 12) , k_ra8_ceu_evt_cpbe2 = (1UL << 13) , k_ra8_ceu_evt_cpbe3 = (1UL << 14) , k_ra8_ceu_evt_cpbe4 = (1UL << 15) , k_ra8_ceu_evt_cram_overflow = (1UL << 16) , k_ra8_ceu_evt_hd_mismatch = (1UL << 17) , k_ra8_ceu_evt_vd_mismatch = (1UL << 18) , k_ra8_ceu_evt_vd_error = (1UL << 20) , k_ra8_ceu_evt_firewall = (1UL << 23) , k_ra8_ceu_evt_hd_missing = (1UL << 24) , k_ra8_ceu_evt_vd_missing = (1UL << 25) }
	CETCR (offset 0x0074) event flag bit positions. More...
enum	ra8_ceu_evt_mask_group_t : uint32_t { k_ra8_ceu_evt_mask_all_errors , k_ra8_ceu_evt_mask_all_bundle , k_ra8_ceu_evt_mask_all_sync , k_ra8_ceu_evt_mask_all_end , k_ra8_ceu_evt_mask_all = 0x03F7F713UL }
	Convenience groupings of CETCR events for callbacks. More...
enum	ra8_ceu_cdssr_mask_t : uint32_t { k_ra8_ceu_cdssr_mask_cdss = 0xFFFFFFFFUL }
	CDSSR (offset 0x0084) bit mask. More...
enum	ra8_ceu_align_t : uint32_t { k_ra8_ceu_buffer_align_bytes = 8U }
	Capture buffer alignment requirement. More...
enum	ra8_ceu_burst_align_t : uint32_t { k_ra8_ceu_bundle_align_mask = 0x7U }
	CBDSR write-granularity alignment. More...
enum	ra8_ceu_firewall_align_t : uint32_t { k_ra8_ceu_firewall_align_mask = 0x1FU }
	CFWCR.FWV alignment. More...

Functions
static volatile uint32_t *	ra8_ceu_reg32 (ra8_ceu_off_t offset)
	Pointer to a 32-bit register inside the CEU window.
static volatile uint32_t *	ra8_ceu_reg32_plane (ra8_ceu_off_t offset, ra8_ceu_plane_off_t plane)
	Pointer to a 32-bit register on a specific CEU plane.

Detailed Description

Capture Engine Unit (CEU) register layout for the RA8D2.

Tag: [Ring 3 / HAL] {World: NS}

The CEU drives the parallel camera input path (VIO_D[15:0], VIO_VD, VIO_HD, VIO_CLK, VIO_FLD) and DMAs captured frames into SRAM/SDRAM. On the EK-RA8D2 board this is the path used by the on-board OV5640 5MP CMOS sensor.

Most CEU registers exist in three planes:

Plane A at base + 0x0000 (active programming view)
Plane B at base + 0x1000 (shadow plane, writable while A is in use; the CEU swaps planes on the next VD edge)
Mirror at base + 0x2000 (always targets the inactive plane)

Per HUM Ch 60.2 Table 60.4 "Register configuration of CEU" p 3629, the offset registers (CAMOR, CAPWR), filter registers (CFLCR, CFSZR), destination width (CDWDR), every address register (CDAYR/CDACR/CDBYR/CDBCR/CBDSR), the low-pass and data output controls (CLFCR, CDOCR), and the bundle 2 address group (CDAYR2/CDACR2/CDBYR2/CDBCR2) all expose the three-plane window. Single-plane registers – CAPSR, CAPCR, CAMCR, CMCYR, CAIFR, CRCNTR, CRCMPR, CFWCR, CEIER, CETCR, CSTSR, CDSSR – only have a Plane A address and ignore the +0x1000 / +0x2000 offsets.

Register table (verified against HUM Table 60.4 p 3629-3630)

Offset	Name	R/W	Purpose
0x0000	CAPSR	R/W	Capture start (CE) / software reset (CPKIL)
0x0004	CAPCR	R/W	Capture control (continuous, burst mode)
0x0008	CAMCR	R/W	Camera interface control
0x000C	CMCYR	R/W	Camera interface cycle (HCYL / VCYL)
0x0010	CAMOR	R/W	Camera offset (HOFST / VOFST) [3-plane]
0x0014	CAPWR	R/W	Camera capture width (HWDTH / VWDTH)
0x0018	CAIFR	R/W	Camera interface input format
0x0028	CRCNTR	R/W	Register control (plane-swap)
0x002C	CRCMPR	R/W	Register forcible control
0x0030	CFLCR	R/W	Capture filter control (scale-down factor)
0x0034	CFSZR	R/W	Capture filter size clip
0x0038	CDWDR	R/W	Capture destination width
0x003C	CDAYR	R/W	Capture data Y address (top-field / frame)
0x0040	CDACR	R/W	Capture data C address
0x0044	CDBYR	R/W	Capture data Y bottom-field
0x0048	CDBCR	R/W	Capture data C bottom-field
0x004C	CBDSR	R/W	Capture bundle destination size
0x005C	CFWCR	R/W	Firewall operation control
0x0060	CLFCR	R/W	Low-pass filter control
0x0064	CDOCR	R/W	Data output control (byte swap, format)
0x0070	CEIER	R/W	Event interrupt enable
0x0074	CETCR	R/W	Event flag clear (write-0-to-clear)
0x007C	CSTSR	R	Status (CPTON: capture in progress)
0x0084	CDSSR	R/W	Data size status
0x0090	CDAYR2	R/W	Bundle 2 Y address
0x0094	CDACR2	R/W	Bundle 2 C address
0x0098	CDBYR2	R/W	Bundle 2 Y bottom-field
0x009C	CDBCR2	R/W	Bundle 2 C bottom-field

The base address itself is already declared in ra8_glcdc_regs.h (k_ra8_ceu_base_addr in the ra8_display_addr_t enum), so this header pulls that header in rather than redeclaring the constant.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_ceu_regs.h.

Enumeration Type Documentation

◆ ra8_ceu_align_t

enum ra8_ceu_align_t : uint32_t

Capture buffer alignment requirement.

The CDAYR / CDACR / CDBYR / CDBCR address registers require their lower 3 bits to be zero (8-byte alignment) per HUM Ch 60.2.13 "CDAYR" / 60.2.14 "CDACR" / 60.2.15 "CDBYR" / 60.2.16 "CDBCR" p 3656-3658.

Enumerator
k_ra8_ceu_buffer_align_bytes	RA8 CEU buffer align bytes.

Definition at line 640 of file ra8_ceu_regs.h.

◆ ra8_ceu_burst_align_t

enum ra8_ceu_burst_align_t : uint32_t

CBDSR write-granularity alignment.

HUM Ch 60.2.17 p 3660 says CBDSR writes ignore the lower 3 bits.

Enumerator
k_ra8_ceu_bundle_align_mask	RA8 CEU bundle align mask.

Definition at line 651 of file ra8_ceu_regs.h.

◆ ra8_ceu_caifr_mask_t

enum ra8_ceu_caifr_mask_t : uint32_t

CAIFR field masks.

Enumerator
k_ra8_ceu_caifr_mask_fci	FCI[1:0] mask.
k_ra8_ceu_caifr_mask_cim	CIM mask.
k_ra8_ceu_caifr_mask_ifs	IFS mask.

Definition at line 334 of file ra8_ceu_regs.h.

◆ ra8_ceu_caifr_shift_t

enum ra8_ceu_caifr_shift_t : uint8_t

CAIFR (offset 0x0018) field shifts.

HUM Ch 60.2.7 "CAIFR : Camera Interface Input Format Register" p 3647 splits the register into:

bits 1:0 FCI[1:0]: first-captured-image select for interlace (00=immediate, 01=top, 10=bottom).
bit 4 CIM : capture image (0 = both-field, 1 = one-field).
bit 8 IFS : input format select (0 = progressive, 1 = interlace).

Enumerator
k_ra8_ceu_caifr_shift_fci	FCI[1:0] @ [1:0].
k_ra8_ceu_caifr_shift_cim	CIM @ bit 4.
k_ra8_ceu_caifr_shift_ifs	IFS @ bit 8.

Definition at line 324 of file ra8_ceu_regs.h.

◆ ra8_ceu_camcr_mask_t

enum ra8_ceu_camcr_mask_t : uint32_t

CAMCR field masks.

Enumerator
k_ra8_ceu_camcr_mask_hdpol	RA8 CEU camcr mask hdpol.
k_ra8_ceu_camcr_mask_vdpol	RA8 CEU camcr mask vdpol.
k_ra8_ceu_camcr_mask_jpg	RA8 CEU camcr mask jpg.
k_ra8_ceu_camcr_mask_dtary	RA8 CEU camcr mask dtary.
k_ra8_ceu_camcr_mask_dtif	RA8 CEU camcr mask dtif.
k_ra8_ceu_camcr_mask_fldpol	RA8 CEU camcr mask fldpol.
k_ra8_ceu_camcr_mask_dsel	RA8 CEU camcr mask dsel.
k_ra8_ceu_camcr_mask_fldsel	RA8 CEU camcr mask fldsel.
k_ra8_ceu_camcr_mask_hdsel	RA8 CEU camcr mask hdsel.
k_ra8_ceu_camcr_mask_vdsel	RA8 CEU camcr mask vdsel.

Definition at line 227 of file ra8_ceu_regs.h.

◆ ra8_ceu_camcr_shift_t

enum ra8_ceu_camcr_shift_t : uint8_t

CAMCR (offset 0x0008) field shifts.

Per HUM Ch 60.2.3 "CAMCR : Camera Interface Control Register" p 3636-3641 the layout is:

bit 0 HDPOL : HD polarity.
bit 1 VDPOL : VD polarity.
bits 5:4 JPG[1:0]: capture format (image / data sync / data en).
bits 9:8 DTARY[1:0]: input order for image-capture mode.
bit 12 DTIF : data bus width (8/16-bit).
bit 16 FLDPOL : field signal polarity (interlace).
bit 24 DSEL : data latch edge select.
bit 25 FLDSEL : FLD latch edge select.
bit 26 HDSEL : HD latch edge select.
bit 27 VDSEL : VD latch edge select.

Enumerator
k_ra8_ceu_camcr_shift_hdpol	HDPOL @ bit 0.
k_ra8_ceu_camcr_shift_vdpol	VDPOL @ bit 1.
k_ra8_ceu_camcr_shift_jpg	JPG[1:0] @ [5:4].
k_ra8_ceu_camcr_shift_dtary	DTARY[1:0] @ [9:8].
k_ra8_ceu_camcr_shift_dtif	DTIF @ bit 12.
k_ra8_ceu_camcr_shift_fldpol	FLDPOL @ bit 16.
k_ra8_ceu_camcr_shift_dsel	DSEL @ bit 24.
k_ra8_ceu_camcr_shift_fldsel	FLDSEL @ bit 25.
k_ra8_ceu_camcr_shift_hdsel	HDSEL @ bit 26.
k_ra8_ceu_camcr_shift_vdsel	VDSEL @ bit 27.

Definition at line 210 of file ra8_ceu_regs.h.

◆ ra8_ceu_camor_mask_t

enum ra8_ceu_camor_mask_t : uint32_t

CAMOR field masks.

Enumerator
k_ra8_ceu_camor_mask_hofst	HOFST @ [12:0].
k_ra8_ceu_camor_mask_vofst	VOFST @ [27:16].

Definition at line 283 of file ra8_ceu_regs.h.

◆ ra8_ceu_camor_shift_t

enum ra8_ceu_camor_shift_t : uint8_t

CAMOR (offset 0x0010) field shifts.

HUM Ch 60.2.5 "CAMOR : Camera Interface Offset Register" p 3642 splits the register into:

bits 12:0 HOFST[12:0]: horizontal capture-start offset.
bits 27:16 VOFST[11:0]: vertical capture-start offset.

Enumerator
k_ra8_ceu_camor_shift_hofst	HOFST[12:0] @ [12:0].
k_ra8_ceu_camor_shift_vofst	VOFST[11:0] @ [27:16].

Definition at line 274 of file ra8_ceu_regs.h.

◆ ra8_ceu_capcr_mask_t

enum ra8_ceu_capcr_mask_t : uint32_t

CAPCR field masks.

Enumerator
k_ra8_ceu_capcr_mask_ctncp	CTNCP: continuous mode.
k_ra8_ceu_capcr_mask_mtcm	MTCM[1:0] burst-size sel.
k_ra8_ceu_capcr_mask_fdrp	FDRP[7:0] frame-drop cnt.

Definition at line 186 of file ra8_ceu_regs.h.

◆ ra8_ceu_capcr_shift_t

enum ra8_ceu_capcr_shift_t : uint8_t

CAPCR (offset 0x0004) field shifts.

Per HUM Ch 60.2.2 "CAPCR : Capture Control Register" p 3634-3635 the layout is:

bit 16 CTNCP : continuous capture enable.
bits 21:20 MTCM[1:0]: bus burst mode (32/64/128/256-byte unit).
bits 31:24 FDRP[7:0]: frame-drop interval count.

Enumerator
k_ra8_ceu_capcr_shift_ctncp	CTNCP @ bit 16.
k_ra8_ceu_capcr_shift_mtcm	MTCM[1:0] @ [21:20].
k_ra8_ceu_capcr_shift_fdrp	FDRP[7:0] @ [31:24].

Definition at line 176 of file ra8_ceu_regs.h.

◆ ra8_ceu_capsr_bit_t

enum ra8_ceu_capsr_bit_t : uint8_t

CAPSR (offset 0x0000) bit positions.

Per HUM Ch 60.2.1 "CAPSR : Capture Start Register" p 3630-3631:

bit 0 (CE) : 0 stops capture, 1 starts capture at next VD.
bit 16 (CPKIL): 1 issues a software reset of capturing.

Enumerator
k_ra8_ceu_capsr_bit_ce	CE @ bit 0.
k_ra8_ceu_capsr_bit_cpkil	CPKIL @ bit 16.

Definition at line 151 of file ra8_ceu_regs.h.

◆ ra8_ceu_capsr_mask_t

enum ra8_ceu_capsr_mask_t : uint32_t

CAPSR bit masks (full 32-bit register).

Enumerator
k_ra8_ceu_capsr_mask_ce	CE: capture-enable bit.
k_ra8_ceu_capsr_mask_cpkil	CPKIL: software reset bit.

Definition at line 160 of file ra8_ceu_regs.h.

◆ ra8_ceu_capwr_mask_t

enum ra8_ceu_capwr_mask_t : uint32_t

CAPWR field masks.

Enumerator
k_ra8_ceu_capwr_mask_hwdth	RA8 CEU capwr mask hwdth.
k_ra8_ceu_capwr_mask_vwdth	RA8 CEU capwr mask vwdth.

Definition at line 307 of file ra8_ceu_regs.h.

◆ ra8_ceu_capwr_shift_t

enum ra8_ceu_capwr_shift_t : uint8_t

CAPWR (offset 0x0014) field shifts.

HUM Ch 60.2.6 "CAPWR : Camera Interface Width Register" p 3646 splits the register into:

bits 12:0 HWDTH[12:0]: horizontal capture width (cycles).
bits 27:16 VWDTH[11:0]: vertical capture lines.

Enumerator
k_ra8_ceu_capwr_shift_hwdth	HWDTH[12:0] @ [12:0].
k_ra8_ceu_capwr_shift_vwdth	VWDTH[11:0] @ [27:16].

Definition at line 298 of file ra8_ceu_regs.h.

◆ ra8_ceu_cbdsr_mask_t

enum ra8_ceu_cbdsr_mask_t : uint32_t

CBDSR (offset 0x004C) bit masks.

HUM Ch 60.2.17 "CBDSR : Capture Bundle Destination Size Register" p 3660. Number of lines (image / sync fetch) or bytes (data-enable fetch) for each bundle write. Writes to bits [2:0] are ignored (8-line / 32-byte alignment).

Enumerator
k_ra8_ceu_cbdsr_mask_cbvs	CBVS[22:0] bundle size.

Definition at line 445 of file ra8_ceu_regs.h.

◆ ra8_ceu_cdocr_mask_t

enum ra8_ceu_cdocr_mask_t : uint32_t

CDOCR field masks.

Enumerator
k_ra8_ceu_cdocr_mask_cobs	RA8 CEU cdocr mask cobs.
k_ra8_ceu_cdocr_mask_cows	RA8 CEU cdocr mask cows.
k_ra8_ceu_cdocr_mask_cols	RA8 CEU cdocr mask cols.
k_ra8_ceu_cdocr_mask_cds	RA8 CEU cdocr mask cds.
k_ra8_ceu_cdocr_mask_cbe	RA8 CEU cdocr mask cbe.

Definition at line 513 of file ra8_ceu_regs.h.

◆ ra8_ceu_cdocr_shift_t

enum ra8_ceu_cdocr_shift_t : uint8_t

CDOCR (offset 0x0064) field shifts.

HUM Ch 60.2.20 "CDOCR : Capture Data Output Control Register" p 3662-3663:

bit 0 COBS: 8-bit unit byte swap.
bit 1 COWS: 16-bit unit byte swap.
bit 2 COLS: 32-bit unit byte swap.
bit 4 CDS : output format (0 = YCbCr420, 1 = YCbCr422).
bit 16 CBE : bundle write enable.

Enumerator
k_ra8_ceu_cdocr_shift_cobs	RA8 CEU cdocr shift cobs.
k_ra8_ceu_cdocr_shift_cows	RA8 CEU cdocr shift cows.
k_ra8_ceu_cdocr_shift_cols	RA8 CEU cdocr shift cols.
k_ra8_ceu_cdocr_shift_cds	RA8 CEU cdocr shift cds.
k_ra8_ceu_cdocr_shift_cbe	RA8 CEU cdocr shift cbe.

Definition at line 501 of file ra8_ceu_regs.h.

◆ ra8_ceu_cdssr_mask_t

enum ra8_ceu_cdssr_mask_t : uint32_t

CDSSR (offset 0x0084) bit mask.

HUM Ch 60.2.24 "CDSSR : Capture Data Size Register" p 3674. The full 32 bits hold the byte count written by the most recent data-enable-fetch capture. In bundle-write mode the value is the tail count after the last bundle boundary; if the boundary coincides with the capture-end the register reads 0.

Enumerator
k_ra8_ceu_cdssr_mask_cdss	CDSS[31:0] data byte count.

Definition at line 626 of file ra8_ceu_regs.h.

◆ ra8_ceu_cdwdr_mask_t

enum ra8_ceu_cdwdr_mask_t : uint32_t

CDWDR (offset 0x0038) bit masks.

HUM Ch 60.2.12 "CDWDR : Capture Destination Width Register" p 3654. Holds the destination horizontal stride in 4-byte units.

Enumerator
k_ra8_ceu_cdwdr_mask_chdw	CHDW[12:0] stride.

Definition at line 431 of file ra8_ceu_regs.h.

◆ ra8_ceu_cetcr_mask_t

enum ra8_ceu_cetcr_mask_t : uint32_t

CETCR (offset 0x0074) event flag bit positions.

HUM Ch 60.2.22 "CETCR : Capture Event Flag Clear Register" p 3664-3667. CEIER uses identical bit positions to gate which events raise the CEU IRQ. Writing 0 to any CETCR bit clears it (write-0-to-clear); writing 1 leaves it asserted.

Every documented event in HUM Table 60.10 / Figure 60.45 is enumerated here so the dispatcher can fan out the full mask:

Bit	Mnemonic	Description
0	CPE	One-frame capture end
1	CFE	One-field capture end
4	IGRW	Illegal register write during capture
8	HD	Horizontal sync detect
9	VD	Vertical sync detect
12	CPBE1	Bundle write end on CDAYR / CDACR
13	CPBE2	Bundle write end on CDAYR2 / CDACR2
14	CPBE3	Bundle write end on CDBYR / CDBCR
15	CPBE4	Bundle write end on CDBYR2 / CDBCR2
16	CDTOF	CRAM overflow
17	IGHS	HD-line-count mismatch vs CMCYR
18	IGVS	VD-line-count mismatch vs CMCYR
20	VBP	Invalid VD condition
23	FWF	Firewall address fault
24	NHD	HD expected but absent
25	NVD	VD expected but absent

Enumerator
k_ra8_ceu_evt_cpe	CPE: one-frame capture end.
k_ra8_ceu_evt_cfe	CFE: one-field capture end.
k_ra8_ceu_evt_igrw	IGRW: illegal register write.
k_ra8_ceu_evt_hd	HD: horizontal sync.
k_ra8_ceu_evt_vd	VD: vertical sync.
k_ra8_ceu_evt_cpbe1	CPBE1: bundle 1 write end.
k_ra8_ceu_evt_cpbe2	CPBE2: bundle 2 write end.
k_ra8_ceu_evt_cpbe3	CPBE3: bundle 3 write end.
k_ra8_ceu_evt_cpbe4	CPBE4: bundle 4 write end.
k_ra8_ceu_evt_cram_overflow	CDTOF: CRAM overflow.
k_ra8_ceu_evt_hd_mismatch	IGHS: HD line-count mismatch.
k_ra8_ceu_evt_vd_mismatch	IGVS: VD line-count mismatch.
k_ra8_ceu_evt_vd_error	VBP: invalid VD condition.
k_ra8_ceu_evt_firewall	FWF: firewall-address fault.
k_ra8_ceu_evt_hd_missing	NHD: HD expected but absent.
k_ra8_ceu_evt_vd_missing	NVD: VD expected but absent.

Definition at line 571 of file ra8_ceu_regs.h.

◆ ra8_ceu_cflcr_mask_t

enum ra8_ceu_cflcr_mask_t : uint32_t

CFLCR field masks.

Enumerator
k_ra8_ceu_cflcr_mask_hfrac	RA8 CEU cflcr mask hfrac.
k_ra8_ceu_cflcr_mask_hmant	RA8 CEU cflcr mask hmant.
k_ra8_ceu_cflcr_mask_vfrac	RA8 CEU cflcr mask vfrac.
k_ra8_ceu_cflcr_mask_vmant	RA8 CEU cflcr mask vmant.

Definition at line 393 of file ra8_ceu_regs.h.

◆ ra8_ceu_cflcr_shift_t

enum ra8_ceu_cflcr_shift_t : uint8_t

CFLCR (offset 0x0030) field shifts.

HUM Ch 60.2.10 "CFLCR : Capture Filter Control Register" p 3650. Scale-down factor encoded as fixed-point fraction.fmant:

bits 11:0 HFRAC[11:0]: horizontal scale fractional bits.
bits 15:12 HMANT[3:0]: horizontal scale mantissa bits.
bits 27:16 VFRAC[11:0]: vertical scale fractional bits.
bits 31:28 VMANT[3:0]: vertical scale mantissa bits.

Enumerator
k_ra8_ceu_cflcr_shift_hfrac	RA8 CEU cflcr shift hfrac.
k_ra8_ceu_cflcr_shift_hmant	RA8 CEU cflcr shift hmant.
k_ra8_ceu_cflcr_shift_vfrac	RA8 CEU cflcr shift vfrac.
k_ra8_ceu_cflcr_shift_vmant	RA8 CEU cflcr shift vmant.

Definition at line 382 of file ra8_ceu_regs.h.

◆ ra8_ceu_cfszr_mask_t

enum ra8_ceu_cfszr_mask_t : uint32_t

CFSZR field masks.

Enumerator
k_ra8_ceu_cfszr_mask_hfclp	RA8 CEU cfszr mask hfclp.
k_ra8_ceu_cfszr_mask_vfclp	RA8 CEU cfszr mask vfclp.

Definition at line 418 of file ra8_ceu_regs.h.

◆ ra8_ceu_cfszr_shift_t

enum ra8_ceu_cfszr_shift_t : uint8_t

CFSZR (offset 0x0034) field shifts.

HUM Ch 60.2.11 "CFSZR : Capture Filter Size Clip Register" p 3651:

bits 11:0 HFCLP[11:0]: horizontal clip in 4-pixel units.
bits 27:16 VFCLP[11:0]: vertical clip in 4-pixel units.

Enumerator
k_ra8_ceu_cfszr_shift_hfclp	RA8 CEU cfszr shift hfclp.
k_ra8_ceu_cfszr_shift_vfclp	RA8 CEU cfszr shift vfclp.

Definition at line 409 of file ra8_ceu_regs.h.

◆ ra8_ceu_cfwcr_mask_t

enum ra8_ceu_cfwcr_mask_t : uint32_t

CFWCR field masks.

Enumerator
k_ra8_ceu_cfwcr_mask_fwe	FWE: enable.
k_ra8_ceu_cfwcr_mask_fwv	FWV[26:0] @ [31:5].

Definition at line 470 of file ra8_ceu_regs.h.

◆ ra8_ceu_cfwcr_shift_t

enum ra8_ceu_cfwcr_shift_t : uint8_t

CFWCR (offset 0x005C) field shifts.

HUM Ch 60.2.18 "CFWCR : Firewall Operation Control Register" p 3661. Programs a TrustZone-style window of legal write addresses for data-enable fetch:

bit 0 FWE : firewall enable.
bits 31:5 FWV[26:0]: upper firewall address bits (lower 5 are implicitly 0x1F).

Enumerator
k_ra8_ceu_cfwcr_shift_fwe	RA8 CEU cfwcr shift fwe.
k_ra8_ceu_cfwcr_shift_fwv	RA8 CEU cfwcr shift fwv.

Definition at line 461 of file ra8_ceu_regs.h.

◆ ra8_ceu_clfcr_mask_t

enum ra8_ceu_clfcr_mask_t : uint32_t

CLFCR (offset 0x0060) bit masks.

HUM Ch 60.2.19 "CLFCR : Capture Low-Pass Filter Control Register" p 3662. Single-bit enable for the input low-pass filter ahead of the scale-down stage.

Enumerator
k_ra8_ceu_clfcr_mask_lpf	LPF: enable LPF.

Definition at line 484 of file ra8_ceu_regs.h.

◆ ra8_ceu_cmcyr_mask_t

enum ra8_ceu_cmcyr_mask_t : uint32_t

CMCYR field masks.

Enumerator
k_ra8_ceu_cmcyr_mask_hcyl	HCYL[13:0] @ [13:0].
k_ra8_ceu_cmcyr_mask_vcyl	VCYL[13:0] @ [29:16].

Definition at line 259 of file ra8_ceu_regs.h.

◆ ra8_ceu_cmcyr_shift_t

enum ra8_ceu_cmcyr_shift_t : uint8_t

CMCYR (offset 0x000C) field shifts.

HUM Ch 60.2.4 "CMCYR : Camera Interface Cycle Register" p 3641 splits the register into:

bits 13:0 HCYL[13:0]: horizontal cycle count.
bits 29:16 VCYL[13:0]: vertical line count.

Enumerator
k_ra8_ceu_cmcyr_shift_hcyl	HCYL[13:0] @ [13:0].
k_ra8_ceu_cmcyr_shift_vcyl	VCYL[13:0] @ [29:16].

Definition at line 250 of file ra8_ceu_regs.h.

◆ ra8_ceu_crcmpr_mask_t

enum ra8_ceu_crcmpr_mask_t : uint32_t

CRCMPR (offset 0x002C) bit masks.

HUM Ch 60.2.9 "CRCMPR : CEU Register Forcible Control Register" p 3649. Bit 0 (RA) forces an immediate plane swap regardless of VD timing.

Enumerator
k_ra8_ceu_crcmpr_mask_ra	RA: force plane swap.

Definition at line 366 of file ra8_ceu_regs.h.

◆ ra8_ceu_crcntr_mask_t

enum ra8_ceu_crcntr_mask_t : uint32_t

CRCNTR (offset 0x0028) bit masks.

HUM Ch 60.2.8 "CRCNTR : CEU Register Control Register" p 3649 lays out the plane-swap control:

bit 0 RC : Plane A enable.
bit 1 RS : Plane B enable.
bit 4 RVS: register-set sync enable (latch on VD).

Enumerator
k_ra8_ceu_crcntr_mask_rc	RC: enable Plane A.
k_ra8_ceu_crcntr_mask_rs	RS: enable Plane B.
k_ra8_ceu_crcntr_mask_rvs	RVS: VD-sync update.

Definition at line 351 of file ra8_ceu_regs.h.

◆ ra8_ceu_cstsr_mask_t

enum ra8_ceu_cstsr_mask_t : uint32_t

CSTSR (offset 0x007C) status bit masks.

HUM Ch 60.2.23 "CSTSR : Capture Status Register" p 3672. CSTSR is read-only:

bit 0 CPTON: 1 -> capture currently running.
bit 16 CPFLD: current field (0 = top, 1 = bottom) when in interlace mode.
bit 24 CRST : 1 -> CEU is in software-reset (CPKIL) sequence.

Enumerator
k_ra8_ceu_cstsr_mask_cpton	CPTON: capture running.
k_ra8_ceu_cstsr_mask_cpfld	CPFLD: current field.
k_ra8_ceu_cstsr_mask_crst	CRST: reset in flight.

Definition at line 533 of file ra8_ceu_regs.h.

◆ ra8_ceu_evt_mask_group_t

enum ra8_ceu_evt_mask_group_t : uint32_t

Convenience groupings of CETCR events for callbacks.

Hand-curated unions of ra8_ceu_cetcr_mask_t values that callers tend to enable as a set. k_ra8_ceu_evt_mask_all_errors covers every fault condition the HUM lists; k_ra8_ceu_evt_mask_all is the universal mask used by ra8_ceu_clear_status callers that want to ack every pending flag.

Enumerator
k_ra8_ceu_evt_mask_all_errors	RA8 CEU evt mask all errors.
k_ra8_ceu_evt_mask_all_bundle	RA8 CEU evt mask all bundle.
k_ra8_ceu_evt_mask_all_sync	RA8 CEU evt mask all sync.
k_ra8_ceu_evt_mask_all_end	RA8 CEU evt mask all end.
k_ra8_ceu_evt_mask_all	RA8 CEU evt mask all.

Definition at line 601 of file ra8_ceu_regs.h.

◆ ra8_ceu_firewall_align_t

enum ra8_ceu_firewall_align_t : uint32_t

CFWCR.FWV alignment.

Per HUM Ch 60.2.18 p 3661 the firewall value is the upper 27 bits of an address; the lower 5 bits are forced to 0x1F. This mask is used by ra8_ceu_firewall_set to compose the value.

Enumerator
k_ra8_ceu_firewall_align_mask	RA8 CEU firewall align mask.

Definition at line 664 of file ra8_ceu_regs.h.

◆ ra8_ceu_off_t

enum ra8_ceu_off_t : uint16_t

Plane A register offsets inside the CEU window.

Verified byte-for-byte against HUM Ch 60.2 Table 60.4 "Register configuration of CEU" p 3629-3630. Mirror addresses for the Plane A view (used by this driver) follow the FSP convention of "+0x1000 -> Plane B, +0x2000 -> mirror" – see ra8_ceu_plane_off_t and ra8_ceu_reg32_plane.

Enumerator
k_ra8_ceu_off_capsr	Capture Start Register.
k_ra8_ceu_off_capcr	Capture Control Register.
k_ra8_ceu_off_camcr	Camera Interface Control Register.
k_ra8_ceu_off_cmcyr	Camera Interface Cycle Register.
k_ra8_ceu_off_camor	Camera Interface Offset Register.
k_ra8_ceu_off_capwr	Camera Interface Width Register.
k_ra8_ceu_off_caifr	Camera Interface Input Format Register.
k_ra8_ceu_off_crcntr	Register Control Register.
k_ra8_ceu_off_crcmpr	Register Forcible Control Register.
k_ra8_ceu_off_cflcr	Capture Filter Control Register.
k_ra8_ceu_off_cfszr	Capture Filter Size Clip Register.
k_ra8_ceu_off_cdwdr	Capture Destination Width Register.
k_ra8_ceu_off_cdayr	Capture Data Y Address Register.
k_ra8_ceu_off_cdacr	Capture Data C Address Register.
k_ra8_ceu_off_cdbyr	Capture Data Y Bottom-Field Register.
k_ra8_ceu_off_cdbcr	Capture Data C Bottom-Field Register.
k_ra8_ceu_off_cbdsr	Capture Bundle Destination Size.
k_ra8_ceu_off_cfwcr	Firewall Operation Control Register.
k_ra8_ceu_off_clfcr	Capture Low-Pass Filter Control.
k_ra8_ceu_off_cdocr	Capture Data Output Control Register.
k_ra8_ceu_off_ceier	Capture Event Interrupt Enable Register.
k_ra8_ceu_off_cetcr	Capture Event Flag Clear Register.
k_ra8_ceu_off_cstsr	Capture Status Register (R).
k_ra8_ceu_off_cdssr	Capture Data Size Status Register.
k_ra8_ceu_off_cdayr2	Capture Data Y Address Register 2.
k_ra8_ceu_off_cdacr2	Capture Data C Address Register 2.
k_ra8_ceu_off_cdbyr2	Capture Data Y2 Bottom-Field Register.
k_ra8_ceu_off_cdbcr2	Capture Data C2 Bottom-Field Register.

Definition at line 111 of file ra8_ceu_regs.h.

◆ ra8_ceu_plane_off_t

enum ra8_ceu_plane_off_t : uint16_t

Plane stride between Plane A, Plane B, and the mirror view.

Per HUM Ch 60.2 Table 60.4 "Register configuration of CEU" p 3629-3630, only a subset of CEU registers expose the three-plane layout; for those that do, Plane B sits at base

0x1000 and the mirror at base + 0x2000.

Enumerator
k_ra8_ceu_plane_a_off	Plane A (active).
k_ra8_ceu_plane_b_off	Plane B (shadow).
k_ra8_ceu_plane_mirror_off	Mirror (inactive plane).

Definition at line 94 of file ra8_ceu_regs.h.

Function Documentation

◆ ra8_ceu_reg32()

volatile uint32_t * ra8_ceu_reg32 ( ra8_ceu_off_t offset )

inlinestatic

Pointer to a 32-bit register inside the CEU window.

All CEU registers are 32 bits wide and accessed by 32-bit reads and writes (HUM Ch 60.2 Table 60.4 "Access size" column = 32).

Parameters

[in] offset One of the k_ra8_ceu_off_* enum values.

Returns: Volatile pointer to the register at k_ra8_ceu_base_addr + offset.

Precondition: offset is a member of ra8_ceu_off_t (compile-time enforced by the parameter type).; The CEU module-stop bit (MSTPC16) is cleared before any access via this pointer.

Postcondition: Returned pointer is non-null and properly aligned for a 32-bit access.

Note: Routes through ra8_fake_mmap on host test builds so that writes target real RAM rather than segfaulting.

Since: 0.1.0

Definition at line 692 of file ra8_ceu_regs.h.

References k_ra8_ceu_base_addr.

Referenced by internal_arm_capture(), internal_program_addresses(), internal_wait_idle(), priv_ra8_ceu_program_destination(), priv_ra8_ceu_program_format(), priv_ra8_ceu_program_geometry(), ra8_ceu_bundle_size_set(), ra8_ceu_byte_swap_set(), ra8_ceu_capture_disarm(), ra8_ceu_capture_mode_set(), ra8_ceu_capture_start(), ra8_ceu_clear_status(), ra8_ceu_data_size_get(), ra8_ceu_deinit(), ra8_ceu_dispatch(), ra8_ceu_enter_stop(), ra8_ceu_firewall_set(), ra8_ceu_frame_drop_set(), ra8_ceu_get_status(), ra8_ceu_init(), ra8_ceu_interrupts_set(), ra8_ceu_low_pass_set(), ra8_ceu_plane_b_program(), ra8_ceu_plane_swap_force(), ra8_ceu_reset(), and ra8_ceu_status_snapshot().

◆ ra8_ceu_reg32_plane()

volatile uint32_t * ra8_ceu_reg32_plane	(	ra8_ceu_off_t	offset,
		ra8_ceu_plane_off_t	plane )