ra8_ceu_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_glcdc_regs.h" /* pulls in k_ra8_ceu_base_addr */

typedef enum : uint16_t {
  k_ra8_ceu_plane_a_off      = 0x0000U, 
  k_ra8_ceu_plane_b_off      = 0x1000U, 
  k_ra8_ceu_plane_mirror_off = 0x2000U, 
} ra8_ceu_plane_off_t;

typedef enum : uint16_t {
  k_ra8_ceu_off_capsr  = 0x0000U, 
  k_ra8_ceu_off_capcr  = 0x0004U, 
  k_ra8_ceu_off_camcr  = 0x0008U, 
  k_ra8_ceu_off_cmcyr  = 0x000CU, 
  k_ra8_ceu_off_camor  = 0x0010U, 
  k_ra8_ceu_off_capwr  = 0x0014U, 
  k_ra8_ceu_off_caifr  = 0x0018U, 
  k_ra8_ceu_off_crcntr = 0x0028U, 
  k_ra8_ceu_off_crcmpr = 0x002CU, 
  k_ra8_ceu_off_cflcr  = 0x0030U, 
  k_ra8_ceu_off_cfszr  = 0x0034U, 
  k_ra8_ceu_off_cdwdr  = 0x0038U, 
  k_ra8_ceu_off_cdayr  = 0x003CU, 
  k_ra8_ceu_off_cdacr  = 0x0040U, 
  k_ra8_ceu_off_cdbyr  = 0x0044U, 
  k_ra8_ceu_off_cdbcr  = 0x0048U, 
  k_ra8_ceu_off_cbdsr  = 0x004CU, 
  k_ra8_ceu_off_cfwcr  = 0x005CU, 
  k_ra8_ceu_off_clfcr  = 0x0060U, 
  k_ra8_ceu_off_cdocr  = 0x0064U, 
  k_ra8_ceu_off_ceier  = 0x0070U, 
  k_ra8_ceu_off_cetcr  = 0x0074U, 
  k_ra8_ceu_off_cstsr  = 0x007CU, 
  k_ra8_ceu_off_cdssr  = 0x0084U, 
  k_ra8_ceu_off_cdayr2 = 0x0090U, 
  k_ra8_ceu_off_cdacr2 = 0x0094U, 
  k_ra8_ceu_off_cdbyr2 = 0x0098U, 
  k_ra8_ceu_off_cdbcr2 = 0x009CU, 
} ra8_ceu_off_t;

typedef enum : uint8_t {
  k_ra8_ceu_capsr_bit_ce    = 0U,  
  k_ra8_ceu_capsr_bit_cpkil = 16U, 
} ra8_ceu_capsr_bit_t;

typedef enum : uint32_t {
  k_ra8_ceu_capsr_mask_ce    = (1UL << 0),  
  k_ra8_ceu_capsr_mask_cpkil = (1UL << 16), 
} ra8_ceu_capsr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_capcr_shift_ctncp = 16U, 
  k_ra8_ceu_capcr_shift_mtcm  = 20U, 
  k_ra8_ceu_capcr_shift_fdrp  = 24U, 
} ra8_ceu_capcr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_capcr_mask_ctncp = (1UL << 16),    
  k_ra8_ceu_capcr_mask_mtcm  = (3UL << 20),    
  k_ra8_ceu_capcr_mask_fdrp  = (0xFFUL << 24), 
} ra8_ceu_capcr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_camcr_shift_hdpol  = 0U,  
  k_ra8_ceu_camcr_shift_vdpol  = 1U,  
  k_ra8_ceu_camcr_shift_jpg    = 4U,  
  k_ra8_ceu_camcr_shift_dtary  = 8U,  
  k_ra8_ceu_camcr_shift_dtif   = 12U, 
  k_ra8_ceu_camcr_shift_fldpol = 16U, 
  k_ra8_ceu_camcr_shift_dsel   = 24U, 
  k_ra8_ceu_camcr_shift_fldsel = 25U, 
  k_ra8_ceu_camcr_shift_hdsel  = 26U, 
  k_ra8_ceu_camcr_shift_vdsel  = 27U, 
} ra8_ceu_camcr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_camcr_mask_hdpol  = (1UL << 0),  
  k_ra8_ceu_camcr_mask_vdpol  = (1UL << 1),  
  k_ra8_ceu_camcr_mask_jpg    = (3UL << 4),  
  k_ra8_ceu_camcr_mask_dtary  = (3UL << 8),  
  k_ra8_ceu_camcr_mask_dtif   = (1UL << 12), 
  k_ra8_ceu_camcr_mask_fldpol = (1UL << 16), 
  k_ra8_ceu_camcr_mask_dsel   = (1UL << 24), 
  k_ra8_ceu_camcr_mask_fldsel = (1UL << 25), 
  k_ra8_ceu_camcr_mask_hdsel  = (1UL << 26), 
  k_ra8_ceu_camcr_mask_vdsel  = (1UL << 27), 
} ra8_ceu_camcr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_cmcyr_shift_hcyl = 0U,  
  k_ra8_ceu_cmcyr_shift_vcyl = 16U, 
} ra8_ceu_cmcyr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_cmcyr_mask_hcyl = 0x00003FFFUL, 
  k_ra8_ceu_cmcyr_mask_vcyl = 0x3FFF0000UL, 
} ra8_ceu_cmcyr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_camor_shift_hofst = 0U,  
  k_ra8_ceu_camor_shift_vofst = 16U, 
} ra8_ceu_camor_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_camor_mask_hofst = 0x00001FFFUL, 
  k_ra8_ceu_camor_mask_vofst = 0x0FFF0000UL, 
} ra8_ceu_camor_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_capwr_shift_hwdth = 0U,  
  k_ra8_ceu_capwr_shift_vwdth = 16U, 
} ra8_ceu_capwr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_capwr_mask_hwdth = 0x00001FFFUL, 
  k_ra8_ceu_capwr_mask_vwdth = 0x0FFF0000UL, 
} ra8_ceu_capwr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_caifr_shift_fci = 0U, 
  k_ra8_ceu_caifr_shift_cim = 4U, 
  k_ra8_ceu_caifr_shift_ifs = 8U, 
} ra8_ceu_caifr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_caifr_mask_fci = (3UL << 0), 
  k_ra8_ceu_caifr_mask_cim = (1UL << 4), 
  k_ra8_ceu_caifr_mask_ifs = (1UL << 8), 
} ra8_ceu_caifr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_crcntr_mask_rc  = (1UL << 0), 
  k_ra8_ceu_crcntr_mask_rs  = (1UL << 1), 
  k_ra8_ceu_crcntr_mask_rvs = (1UL << 4), 
} ra8_ceu_crcntr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_crcmpr_mask_ra = (1UL << 0), 
} ra8_ceu_crcmpr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_cflcr_shift_hfrac = 0U,  
  k_ra8_ceu_cflcr_shift_hmant = 12U, 
  k_ra8_ceu_cflcr_shift_vfrac = 16U, 
  k_ra8_ceu_cflcr_shift_vmant = 28U, 
} ra8_ceu_cflcr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_cflcr_mask_hfrac = 0x00000FFFUL, 
  k_ra8_ceu_cflcr_mask_hmant = 0x0000F000UL, 
  k_ra8_ceu_cflcr_mask_vfrac = 0x0FFF0000UL, 
  k_ra8_ceu_cflcr_mask_vmant = 0xF0000000UL, 
} ra8_ceu_cflcr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_cfszr_shift_hfclp = 0U,  
  k_ra8_ceu_cfszr_shift_vfclp = 16U, 
} ra8_ceu_cfszr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_cfszr_mask_hfclp = 0x00000FFFUL, 
  k_ra8_ceu_cfszr_mask_vfclp = 0x0FFF0000UL, 
} ra8_ceu_cfszr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_cdwdr_mask_chdw = 0x00001FFFUL, 
} ra8_ceu_cdwdr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_cbdsr_mask_cbvs = 0x007FFFFFUL, 
} ra8_ceu_cbdsr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_cfwcr_shift_fwe = 0U, 
  k_ra8_ceu_cfwcr_shift_fwv = 5U, 
} ra8_ceu_cfwcr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_cfwcr_mask_fwe = (1UL << 0),   
  k_ra8_ceu_cfwcr_mask_fwv = 0xFFFFFFE0UL, 
} ra8_ceu_cfwcr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_clfcr_mask_lpf = (1UL << 0), 
} ra8_ceu_clfcr_mask_t;

typedef enum : uint8_t {
  k_ra8_ceu_cdocr_shift_cobs = 0U,  
  k_ra8_ceu_cdocr_shift_cows = 1U,  
  k_ra8_ceu_cdocr_shift_cols = 2U,  
  k_ra8_ceu_cdocr_shift_cds  = 4U,  
  k_ra8_ceu_cdocr_shift_cbe  = 16U, 
} ra8_ceu_cdocr_shift_t;

typedef enum : uint32_t {
  k_ra8_ceu_cdocr_mask_cobs = (1UL << 0),  
  k_ra8_ceu_cdocr_mask_cows = (1UL << 1),  
  k_ra8_ceu_cdocr_mask_cols = (1UL << 2),  
  k_ra8_ceu_cdocr_mask_cds  = (1UL << 4),  
  k_ra8_ceu_cdocr_mask_cbe  = (1UL << 16), 
} ra8_ceu_cdocr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_cstsr_mask_cpton = (1UL << 0),  
  k_ra8_ceu_cstsr_mask_cpfld = (1UL << 16), 
  k_ra8_ceu_cstsr_mask_crst  = (1UL << 24), 
} ra8_ceu_cstsr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_evt_cpe           = (1UL << 0),  
  k_ra8_ceu_evt_cfe           = (1UL << 1),  
  k_ra8_ceu_evt_igrw          = (1UL << 4),  
  k_ra8_ceu_evt_hd            = (1UL << 8),  
  k_ra8_ceu_evt_vd            = (1UL << 9),  
  k_ra8_ceu_evt_cpbe1         = (1UL << 12), 
  k_ra8_ceu_evt_cpbe2         = (1UL << 13), 
  k_ra8_ceu_evt_cpbe3         = (1UL << 14), 
  k_ra8_ceu_evt_cpbe4         = (1UL << 15), 
  k_ra8_ceu_evt_cram_overflow = (1UL << 16), 
  k_ra8_ceu_evt_hd_mismatch   = (1UL << 17), 
  k_ra8_ceu_evt_vd_mismatch   = (1UL << 18), 
  k_ra8_ceu_evt_vd_error      = (1UL << 20), 
  k_ra8_ceu_evt_firewall      = (1UL << 23), 
  k_ra8_ceu_evt_hd_missing    = (1UL << 24), 
  k_ra8_ceu_evt_vd_missing    = (1UL << 25), 
} ra8_ceu_cetcr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_evt_mask_all_errors =
    (k_ra8_ceu_evt_igrw | k_ra8_ceu_evt_cram_overflow | k_ra8_ceu_evt_hd_mismatch |
     k_ra8_ceu_evt_vd_mismatch | k_ra8_ceu_evt_vd_error | k_ra8_ceu_evt_firewall |
     k_ra8_ceu_evt_hd_missing | k_ra8_ceu_evt_vd_missing), 
  k_ra8_ceu_evt_mask_all_bundle = (k_ra8_ceu_evt_cpbe1 | k_ra8_ceu_evt_cpbe2 | k_ra8_ceu_evt_cpbe3 |
                                   k_ra8_ceu_evt_cpbe4), 
  k_ra8_ceu_evt_mask_all_sync =
    (k_ra8_ceu_evt_hd | k_ra8_ceu_evt_vd), 
  k_ra8_ceu_evt_mask_all_end =
    (k_ra8_ceu_evt_cpe | k_ra8_ceu_evt_cfe), 
  k_ra8_ceu_evt_mask_all = 0x03F7F713UL,     
} ra8_ceu_evt_mask_group_t;

typedef enum : uint32_t {
  k_ra8_ceu_cdssr_mask_cdss = 0xFFFFFFFFUL, 
} ra8_ceu_cdssr_mask_t;

typedef enum : uint32_t {
  k_ra8_ceu_buffer_align_bytes = 8U, 
} ra8_ceu_align_t;

typedef enum : uint32_t {
  k_ra8_ceu_bundle_align_mask = 0x7U, 
} ra8_ceu_burst_align_t;

typedef enum : uint32_t {
  k_ra8_ceu_firewall_align_mask = 0x1FU, 
} ra8_ceu_firewall_align_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_ceu_reg32(ra8_ceu_off_t offset)
{
  return (volatile uint32_t*)(k_ra8_ceu_base_addr + (uint16_t)offset);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_ceu_reg32_plane(ra8_ceu_off_t       offset,
                                                     ra8_ceu_plane_off_t plane)
{
  return (volatile uint32_t*)(k_ra8_ceu_base_addr + (uint16_t)plane + (uint16_t)offset);
}
 
#ifdef __cplusplus
}
#endif