ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_ceu_init_regs.c
Go to the documentation of this file.
1
21
22#include <stdint.h>
23
24#include "ra8_attributes.h"
25#include "ra8_ceu.h"
26#include "ra8_ceu_internal.h"
27#include "ra8_ceu_regs.h"
28
48static uint32_t internal_pack_camcr(const ra8_ceu_config_t* cfg)
49{
50 uint32_t camcr = 0U;
51 camcr |= ((uint32_t)cfg->hsync_polarity) << k_ra8_ceu_camcr_shift_hdpol;
52 camcr |= ((uint32_t)cfg->vsync_polarity) << k_ra8_ceu_camcr_shift_vdpol;
53 camcr |= ((uint32_t)cfg->capture_format) << k_ra8_ceu_camcr_shift_jpg;
54 camcr |= ((uint32_t)cfg->input_order) << k_ra8_ceu_camcr_shift_dtary;
55 camcr |= ((uint32_t)cfg->data_bus) << k_ra8_ceu_camcr_shift_dtif;
56 camcr |= ((uint32_t)cfg->field_polarity) << k_ra8_ceu_camcr_shift_fldpol;
57 camcr |= ((uint32_t)cfg->edge.data) << k_ra8_ceu_camcr_shift_dsel;
58 camcr |= ((uint32_t)cfg->edge.field) << k_ra8_ceu_camcr_shift_fldsel;
59 camcr |= ((uint32_t)cfg->edge.hsync) << k_ra8_ceu_camcr_shift_hdsel;
60 camcr |= ((uint32_t)cfg->edge.vsync) << k_ra8_ceu_camcr_shift_vdsel;
61 return camcr;
62}
63
82static uint32_t internal_pack_capcr(const ra8_ceu_config_t* cfg)
83{
84 uint32_t capcr = 0U;
86 capcr |= (1U << k_ra8_ceu_capcr_shift_ctncp);
87 }
88 capcr |= ((uint32_t)cfg->burst_mode) << k_ra8_ceu_capcr_shift_mtcm;
89 capcr |= ((uint32_t)cfg->frame_drop) << k_ra8_ceu_capcr_shift_fdrp;
90 return capcr;
91}
92
111static uint32_t internal_pack_caifr(const ra8_ceu_config_t* cfg)
112{
113 uint32_t caifr = 0U;
114 caifr |= ((uint32_t)cfg->first_field) << k_ra8_ceu_caifr_shift_fci;
115 if (cfg->one_field_only) {
116 caifr |= (1U << k_ra8_ceu_caifr_shift_cim);
117 }
118 if (cfg->interlace) {
119 caifr |= (1U << k_ra8_ceu_caifr_shift_ifs);
120 }
121 return caifr;
122}
123
142static uint32_t internal_pack_cflcr(const ra8_ceu_config_t* cfg)
143{
144 uint32_t cflcr = 0U;
145 cflcr |= (((uint32_t)cfg->scale.h_fraction) & k_ra8_ceu_cflcr_mask_hfrac)
147 cflcr |= ((((uint32_t)cfg->scale.h_mantissa) << k_ra8_ceu_cflcr_shift_hmant) &
149 cflcr |= ((((uint32_t)cfg->scale.v_fraction) << k_ra8_ceu_cflcr_shift_vfrac) &
151 cflcr |= ((((uint32_t)cfg->scale.v_mantissa) << k_ra8_ceu_cflcr_shift_vmant) &
153 return cflcr;
154}
155
174static uint32_t internal_pack_cfszr(const ra8_ceu_config_t* cfg)
175{
176 uint32_t cfszr = 0U;
177 cfszr |= (((uint32_t)cfg->scale.h_output_clip) << k_ra8_ceu_cfszr_shift_hfclp) &
179 cfszr |= (((uint32_t)cfg->scale.v_output_clip) << k_ra8_ceu_cfszr_shift_vfclp) &
181 return cfszr;
182}
183
202static uint32_t internal_pack_cdocr(const ra8_ceu_config_t* cfg)
203{
204 uint32_t cdocr = 0U;
205 if (cfg->byte_swap.swap_8_bit) {
207 }
208 if (cfg->byte_swap.swap_16_bit) {
210 }
211 if (cfg->byte_swap.swap_32_bit) {
213 }
215 if (cfg->bundle_write) {
217 }
218 return cdocr;
219}
220
222{
224 /* HUM Ch 60.2.4-60.2.6: data-enable fetch does not use cycle
225 * validation, capture offsets, or the fixed capture window. Nonzero
226 * geometry falsely treats variable JPEG framing as synchronous pixels. */
230 return;
231 }
232
233 /* HUM Ch 60.2.4 "CMCYR : Camera Interface Cycle Register" p 3641 */
234 const uint32_t cmcyr =
235 (((uint32_t)cfg->height_px) << k_ra8_ceu_cmcyr_shift_vcyl) | (uint32_t)cfg->width_px;
237
238 /* HUM Ch 60.2.5 "CAMOR : Camera Interface Offset Register" p 3641 */
239 const uint32_t camor =
240 (((uint32_t)cfg->y_start_px) << k_ra8_ceu_camor_shift_vofst) | (uint32_t)cfg->x_start_px;
242
243 /* HUM Ch 60.2.6 "CAPWR : Camera Interface Width Register" p 3643 */
244 uint16_t hwdth = cfg->width_px;
245 if (cfg->x_capture_px != 0U) {
246 hwdth = cfg->x_capture_px;
247 }
248 uint16_t vwdth = cfg->height_px;
249 if (cfg->y_capture_lines != 0U) {
250 vwdth = cfg->y_capture_lines;
251 }
252 const uint32_t capwr = (((uint32_t)vwdth) << k_ra8_ceu_capwr_shift_vwdth) | (uint32_t)hwdth;
254}
255
263
265{
266 /* HUM Ch 60.2.11 "CFSZR : Capture Filter Size Clip Register" p 3653 */
268
269 /* HUM Ch 60.2.12 "CDWDR : Capture Destination Width Register" p 3654 */
271
272 /* HUM Ch 60.2.18 "CFWCR : Firewall Operation Control Register" p 3661 */
274
275 /* HUM Ch 60.2.19 "CLFCR : Capture Low-Pass Filter Control" p 3662 */
276 uint32_t clfcr = 0U;
277 if (cfg->low_pass_filter) {
278 clfcr = 1U;
279 }
281
282 /* HUM Ch 60.2.20 "CDOCR : Capture Data Output Control Register" p 3662 */
284
285 /* HUM Ch 60.2.22 "CETCR : Capture Event Flag Clear Register" p 3669 */
287}
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Capture Engine Unit (CEU) camera-capture driver.
static uint32_t internal_pack_camcr(const ra8_ceu_config_t *cfg)
Build the CAMCR value from a configuration descriptor.
static uint32_t internal_pack_cdocr(const ra8_ceu_config_t *cfg)
Build the CDOCR value from a configuration descriptor.
void priv_ra8_ceu_program_format(const ra8_ceu_config_t *cfg)
Program filter / format / camera-interface registers.
static uint32_t internal_pack_caifr(const ra8_ceu_config_t *cfg)
Build the CAIFR value from a configuration descriptor.
static uint32_t internal_pack_capcr(const ra8_ceu_config_t *cfg)
Build the CAPCR value from a configuration descriptor.
void priv_ra8_ceu_program_geometry(const ra8_ceu_config_t *cfg)
Program the CMCYR/CAMOR/CAPWR geometry registers.
static uint32_t internal_pack_cfszr(const ra8_ceu_config_t *cfg)
Build the CFSZR value from a configuration descriptor.
void priv_ra8_ceu_program_destination(const ra8_ceu_config_t *cfg)
Program destination / firewall / output / event registers.
static uint32_t internal_pack_cflcr(const ra8_ceu_config_t *cfg)
Build the CFLCR value from a configuration descriptor.
Cross-TU surface for the ra8_ceu driver split.
Capture Engine Unit (CEU) register layout for the RA8D2.
@ k_ra8_ceu_capcr_shift_fdrp
FDRP[7:0] @ [31:24].
@ k_ra8_ceu_capcr_shift_mtcm
MTCM[1:0] @ [21:20].
@ k_ra8_ceu_capcr_shift_ctncp
CTNCP @ bit 16.
@ k_ra8_ceu_cflcr_shift_hfrac
RA8 CEU cflcr shift hfrac.
@ k_ra8_ceu_cflcr_shift_hmant
RA8 CEU cflcr shift hmant.
@ k_ra8_ceu_cflcr_shift_vmant
RA8 CEU cflcr shift vmant.
@ k_ra8_ceu_cflcr_shift_vfrac
RA8 CEU cflcr shift vfrac.
@ k_ra8_ceu_cmcyr_shift_vcyl
VCYL[13:0] @ [29:16].
@ k_ra8_ceu_caifr_shift_fci
FCI[1:0] @ [1:0].
@ k_ra8_ceu_caifr_shift_cim
CIM @ bit 4.
@ k_ra8_ceu_caifr_shift_ifs
IFS @ bit 8.
@ k_ra8_ceu_cdocr_shift_cds
RA8 CEU cdocr shift cds.
@ k_ra8_ceu_cdocr_mask_cbe
RA8 CEU cdocr mask cbe.
@ k_ra8_ceu_cdocr_mask_cows
RA8 CEU cdocr mask cows.
@ k_ra8_ceu_cdocr_mask_cobs
RA8 CEU cdocr mask cobs.
@ k_ra8_ceu_cdocr_mask_cds
RA8 CEU cdocr mask cds.
@ k_ra8_ceu_cdocr_mask_cols
RA8 CEU cdocr mask cols.
@ k_ra8_ceu_camor_shift_vofst
VOFST[11:0] @ [27:16].
@ k_ra8_ceu_cflcr_mask_vfrac
RA8 CEU cflcr mask vfrac.
@ k_ra8_ceu_cflcr_mask_vmant
RA8 CEU cflcr mask vmant.
@ k_ra8_ceu_cflcr_mask_hmant
RA8 CEU cflcr mask hmant.
@ k_ra8_ceu_cflcr_mask_hfrac
RA8 CEU cflcr mask hfrac.
@ k_ra8_ceu_capwr_shift_vwdth
VWDTH[11:0] @ [27:16].
static volatile uint32_t * ra8_ceu_reg32(ra8_ceu_off_t offset)
Pointer to a 32-bit register inside the CEU window.
@ k_ra8_ceu_cfszr_shift_hfclp
RA8 CEU cfszr shift hfclp.
@ k_ra8_ceu_cfszr_shift_vfclp
RA8 CEU cfszr shift vfclp.
@ k_ra8_ceu_cfszr_mask_vfclp
RA8 CEU cfszr mask vfclp.
@ k_ra8_ceu_cfszr_mask_hfclp
RA8 CEU cfszr mask hfclp.
@ k_ra8_ceu_camcr_shift_dtary
DTARY[1:0] @ [9:8].
@ k_ra8_ceu_camcr_shift_hdsel
HDSEL @ bit 26.
@ k_ra8_ceu_camcr_shift_dtif
DTIF @ bit 12.
@ k_ra8_ceu_camcr_shift_vdsel
VDSEL @ bit 27.
@ k_ra8_ceu_camcr_shift_fldpol
FLDPOL @ bit 16.
@ k_ra8_ceu_camcr_shift_hdpol
HDPOL @ bit 0.
@ k_ra8_ceu_camcr_shift_jpg
JPG[1:0] @ [5:4].
@ k_ra8_ceu_camcr_shift_dsel
DSEL @ bit 24.
@ k_ra8_ceu_camcr_shift_fldsel
FLDSEL @ bit 25.
@ k_ra8_ceu_camcr_shift_vdpol
VDPOL @ bit 1.
@ k_ra8_ceu_off_capwr
Camera Interface Width Register.
@ k_ra8_ceu_off_cfszr
Capture Filter Size Clip Register.
@ k_ra8_ceu_off_cdocr
Capture Data Output Control Register.
@ k_ra8_ceu_off_camor
Camera Interface Offset Register.
@ k_ra8_ceu_off_caifr
Camera Interface Input Format Register.
@ k_ra8_ceu_off_cmcyr
Camera Interface Cycle Register.
@ k_ra8_ceu_off_cetcr
Capture Event Flag Clear Register.
@ k_ra8_ceu_off_cfwcr
Firewall Operation Control Register.
@ k_ra8_ceu_off_capcr
Capture Control Register.
@ k_ra8_ceu_off_cdwdr
Capture Destination Width Register.
@ k_ra8_ceu_off_cflcr
Capture Filter Control Register.
@ k_ra8_ceu_off_camcr
Camera Interface Control Register.
@ k_ra8_ceu_off_clfcr
Capture Low-Pass Filter Control.
@ k_ra8_ceu_capture_continuous
CE stays asserted across frames.
@ k_ra8_ceu_fmt_data_enable
JPEG / data-enable fetch.
bool swap_16_bit
COWS: word-swap inside 32-bit dwords.
bool swap_8_bit
COBS: byte-swap inside 16-bit words.
bool swap_32_bit
COLS: dword-swap inside 64-bit qwords.
Full configuration descriptor for ra8_ceu_init.
ra8_ceu_polarity_t field_polarity
CAMCR.FLDPOL.
ra8_ceu_capture_format_t capture_format
CAMCR.JPG.
uint16_t dst_stride
Destination stride bytes (CDWDR).
uint16_t y_capture_lines
CAPWR.VWDTH capture line count.
uint16_t width_px
Captured image width (CMCYR.HCYL).
bool one_field_only
CAIFR.CIM = 1 if true.
ra8_ceu_polarity_t vsync_polarity
CAMCR.VDPOL.
ra8_ceu_byte_swap_t byte_swap
CDOCR.COBS/COWS/COLS.
bool low_pass_filter
CLFCR.LPF = 1 if true.
ra8_ceu_input_order_t input_order
CAMCR.DTARY (image mode).
bool bundle_write
CDOCR.CBE = 1 if true.
ra8_ceu_capture_mode_t capture_mode
CAPCR.CTNCP single/continuous.
uint8_t frame_drop
CAPCR.FDRP[7:0].
uint16_t height_px
Captured image height (CMCYR.VCYL).
ra8_ceu_edge_info_t edge
CAMCR.DSEL/HDSEL/VDSEL/FLDSEL.
uint16_t x_capture_px
CAPWR.HWDTH capture width cycles.
ra8_ceu_field_select_t first_field
CAIFR.FCI.
uint16_t x_start_px
CAMOR.HOFST start offset.
ra8_ceu_scale_t scale
CFLCR + CFSZR scale-down.
bool interlace
CAIFR.IFS = 1 if true.
ra8_ceu_data_bus_t data_bus
CAMCR.DTIF.
ra8_ceu_polarity_t hsync_polarity
CAMCR.HDPOL.
ra8_ceu_output_format_t output_format
CDOCR.CDS YCbCr 422/420.
ra8_ceu_burst_mode_t burst_mode
CAPCR.MTCM bus burst size.
uint16_t y_start_px
CAMOR.VOFST start offset.
ra8_ceu_edge_t hsync
CAMCR.HDSEL (HD).
ra8_ceu_edge_t field
CAMCR.FLDSEL (FLD interlace).
ra8_ceu_edge_t data
CAMCR.DSEL (data lines).
ra8_ceu_edge_t vsync
CAMCR.VDSEL (VD).
uint16_t h_mantissa
CFLCR.HMANT[3:0].
uint16_t v_output_clip
CFSZR.VFCLP[11:0].
uint16_t v_mantissa
CFLCR.VMANT[3:0].
uint16_t h_fraction
CFLCR.HFRAC[11:0].
uint16_t v_fraction
CFLCR.VFRAC[11:0].
uint16_t h_output_clip
CFSZR.HFCLP[11:0].