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Capture Engine Unit (CEU) register layout for the RA8D2.
ra8_ceu_input_order_t
CAMCR.DTARY image-capture input-byte order.
@ k_ra8_ceu_input_y0_cb0_y1_cr0
Y0 Cb0 Y1 Cr0.
@ k_ra8_ceu_input_cb0_y0_cr0_y1
Cb0 Y0 Cr0 Y1.
@ k_ra8_ceu_input_cr0_y0_cb0_y1
Cr0 Y0 Cb0 Y1.
@ k_ra8_ceu_input_y0_cr0_y1_cb0
Y0 Cr0 Y1 Cb0.
ra8_ceu_burst_mode_t
CAPCR.MTCM[1:0] bus-burst transfer size.
@ k_ra8_ceu_burst_32
32-byte bus bursts.
@ k_ra8_ceu_burst_128
128-byte bus bursts.
@ k_ra8_ceu_burst_64
64-byte bus bursts.
@ k_ra8_ceu_burst_256
256-byte bus bursts.
ra8_ceu_capture_mode_t
CAPCR.CTNCP single-shot vs continuous capture.
@ k_ra8_ceu_capture_single
CE auto-clears after CPE.
@ k_ra8_ceu_capture_continuous
CE stays asserted across frames.
ra8_ceu_capture_format_t
CAMCR.JPG capture-format select.
@ k_ra8_ceu_fmt_data_synchronous
Raw synchronous data fetch.
@ k_ra8_ceu_fmt_image_capture
YCbCr image capture mode.
@ k_ra8_ceu_fmt_data_enable
JPEG / data-enable fetch.
ra8_ceu_interlace_t
CAIFR.IFS – progressive vs interlace input.
@ k_ra8_ceu_interlace
Top + bottom field stream.
@ k_ra8_ceu_progressive
Single-field-per-frame stream.
ra8_ceu_field_select_t
CAIFR.FCI – first captured field for interlace input.
@ k_ra8_ceu_field_immediate
Capture starts at next VD.
@ k_ra8_ceu_field_bottom
Wait for bottom field.
@ k_ra8_ceu_field_top
Wait for top field.
void(* ra8_ceu_event_fn_t)(void *ctx, uint32_t event_mask)
Callback fired by ra8_ceu_dispatch for every CETCR event.
ra8_ceu_polarity_t
CAMCR.HDPOL / VDPOL / FLDPOL polarity select.
@ k_ra8_ceu_pol_high_active
Sync signal is active high.
@ k_ra8_ceu_pol_low_active
Sync signal is active low.
ra8_ceu_data_bus_t
CAMCR.DTIF data-bus width select.
@ k_ra8_ceu_bus_16_bit
VIO_D[15:0] used.
@ k_ra8_ceu_bus_8_bit
VIO_D[7:0] used.
ra8_ceu_edge_t
CAMCR.DSEL / HDSEL / VDSEL / FLDSEL latch-edge select.
@ k_ra8_ceu_edge_falling
Sample on falling VIO_CLK edge.
@ k_ra8_ceu_edge_rising
Sample on rising VIO_CLK edge.
ra8_ceu_output_format_t
CDOCR.CDS output-format select.
@ k_ra8_ceu_output_ycbcr_420
4:2:2 in -> 4:2:0 in memory.
@ k_ra8_ceu_output_ycbcr_422
Pass-through (no conversion).
ra8_ceu_plane_t
CRCNTR plane-A / plane-B selector.
@ k_ra8_ceu_plane_a
Use Plane A registers (default).
@ k_ra8_ceu_plane_b
Use Plane B (shadow) registers.
ra8_ceu_fields_capture_t
CAIFR.CIM – both fields vs single field of an interlace pair.
@ k_ra8_ceu_fields_one
Capture only the FCI-selected field.
@ k_ra8_ceu_fields_both
Capture top + bottom fields.
Error Code Definitions for ra8-firmware.
Address bundle programmed into the CDAYR / CDACR family.
uint8_t * c_bottom
CDBCR – C bottom-field C address.
uint32_t bundle_size_bytes
CBDSR bundle write size (bytes/lines).
uint8_t * c_bottom_2
CDBCR2 – bundle-2 C bottom.
uint8_t * y_bottom_2
CDBYR2 – bundle-2 Y bottom.
uint8_t * y_top_2
CDAYR2 – bundle-2 Y top.
uint8_t * y_top
CDAYR – Y / top-field address.
uint8_t * c_top
CDACR – C / top-field C address.
uint8_t * y_bottom
CDBYR – Y bottom-field address.
uint8_t * c_top_2
CDACR2 – bundle-2 C top.
CDOCR.COBS / COWS / COLS byte-swap control bundle.
bool swap_16_bit
COWS: word-swap inside 32-bit dwords.
bool swap_8_bit
COBS: byte-swap inside 16-bit words.
bool swap_32_bit
COLS: dword-swap inside 64-bit qwords.
Full configuration descriptor for ra8_ceu_init.
uint8_t bytes_per_pixel
Used to derive scaled stride.
ra8_ceu_polarity_t field_polarity
CAMCR.FLDPOL.
ra8_ceu_capture_format_t capture_format
CAMCR.JPG.
uint16_t dst_stride
Destination stride bytes (CDWDR).
uint16_t y_capture_lines
CAPWR.VWDTH capture line count.
uint16_t width_px
Captured image width (CMCYR.HCYL).
bool one_field_only
CAIFR.CIM = 1 if true.
ra8_ceu_polarity_t vsync_polarity
CAMCR.VDPOL.
ra8_ceu_byte_swap_t byte_swap
CDOCR.COBS/COWS/COLS.
bool low_pass_filter
CLFCR.LPF = 1 if true.
ra8_ceu_input_order_t input_order
CAMCR.DTARY (image mode).
bool bundle_write
CDOCR.CBE = 1 if true.
ra8_ceu_capture_mode_t capture_mode
CAPCR.CTNCP single/continuous.
uint8_t frame_drop
CAPCR.FDRP[7:0].
uint16_t height_px
Captured image height (CMCYR.VCYL).
ra8_ceu_edge_info_t edge
CAMCR.DSEL/HDSEL/VDSEL/FLDSEL.
uint16_t x_capture_px
CAPWR.HWDTH capture width cycles.
ra8_ceu_field_select_t first_field
CAIFR.FCI.
uint16_t x_start_px
CAMOR.HOFST start offset.
ra8_ceu_scale_t scale
CFLCR + CFSZR scale-down.
bool interlace
CAIFR.IFS = 1 if true.
ra8_ceu_data_bus_t data_bus
CAMCR.DTIF.
ra8_ceu_polarity_t hsync_polarity
CAMCR.HDPOL.
ra8_ceu_output_format_t output_format
CDOCR.CDS YCbCr 422/420.
ra8_ceu_burst_mode_t burst_mode
CAPCR.MTCM bus burst size.
uint32_t image_area_size
For data-enable firewall window.
uint32_t interrupts
CEIER bitmask (k_ra8_ceu_evt_*).
uint16_t y_start_px
CAMOR.VOFST start offset.
CAMCR.DSEL / HDSEL / VDSEL / FLDSEL latch-edge bundle.
ra8_ceu_edge_t hsync
CAMCR.HDSEL (HD).
ra8_ceu_edge_t field
CAMCR.FLDSEL (FLD interlace).
ra8_ceu_edge_t data
CAMCR.DSEL (data lines).
ra8_ceu_edge_t vsync
CAMCR.VDSEL (VD).
CFLCR scale-down + CFSZR clip-size programming bundle.
uint16_t h_mantissa
CFLCR.HMANT[3:0].
uint16_t v_output_clip
CFSZR.VFCLP[11:0].
uint16_t v_mantissa
CFLCR.VMANT[3:0].
uint16_t h_fraction
CFLCR.HFRAC[11:0].
uint16_t v_fraction
CFLCR.VFRAC[11:0].
uint16_t h_output_clip
CFSZR.HFCLP[11:0].
Snapshot of the CEU live-status registers.
uint32_t events
CETCR raw value (event flags).
bool top_field
CSTSR.CPFLD == 1.
bool capturing
CSTSR.CPTON.
uint32_t data_size
CDSSR last-write byte count.
bool reset_in_flight
CAPSR.CPKIL.
ra8_ceu_plane_t active_plane
CSTSR.CRST register plane.