RIIC (IIC) controller + PI4IOE5V6408 I/O-expander + OV5640 SCCB model. More...

#include <stdint.h>
#include <stdio.h>
#include "board_console.h"
#include "board_periph_block.h"
#include "board_periph_riic_devices_internal.h"
#include "emu_host_io_internal.h"

Include dependency graph for board_periph_riic.c:

Data Structures
struct	riic_state_t
	One RIIC channel: register shadow + a controller transfer machine. More...

Enumerations
enum	riic_console_t : uint32_t { k_riic_console_line_cap = 48U }
	Console-tap line buffer capacity for a RIIC transaction summary. More...
enum	riic_map_t : uint64_t { k_riic_base = 0x4025E000UL , k_riic_stride = 0x100UL , k_riic_count = 3UL , k_riic_span = 0x100UL * 3UL , k_riic_off_iccr1 = 0x00UL , k_riic_off_iccr2 = 0x01UL , k_riic_off_icmr3 = 0x04UL , k_riic_off_icser = 0x06UL , k_riic_off_icsr1 = 0x08UL , k_riic_off_icsr2 = 0x09UL , k_riic_off_sarl0 = 0x0AUL , k_riic_off_sarl1 = 0x0CUL , k_riic_off_sarl2 = 0x0EUL , k_riic_off_icdrt = 0x12UL , k_riic_off_icdrr = 0x13UL , k_riic_reg_bytes = 0x16UL }
	RIIC block geometry (ra8_i2c_regs.h, byte-wide register file). More...
enum	riic_iccr2_bit_t : uint32_t { k_riic_iccr2_st = 0x02U , k_riic_iccr2_rs = 0x04U , k_riic_iccr2_sp = 0x08U , k_riic_iccr2_trs = 0x20U , k_riic_iccr2_mst = 0x40U , k_riic_iccr2_bbsy = 0x80U }
	ICCR2 (control 2) bits the model acts on (ra8_i2c_regs.h). More...
enum	riic_icsr2_bit_t : uint32_t { k_riic_icsr2_tmof = 0x01U , k_riic_icsr2_al = 0x02U , k_riic_icsr2_start = 0x04U , k_riic_icsr2_stop = 0x08U , k_riic_icsr2_nackf = 0x10U , k_riic_icsr2_rdrf = 0x20U , k_riic_icsr2_tend = 0x40U , k_riic_icsr2_tdre = 0x80U }
	ICSR2 (status 2) flags the driver polls / clears (ra8_i2c_regs.h). More...
enum	riic_icsr1_bit_t : uint32_t { k_riic_icsr1_aas0 = 0x01U }
	ICSR1 (status 1) own-address match flags (ra8_i2c_regs.h). More...
enum	riic_icser_bit_t : uint32_t { k_riic_icser_sar0e = 0x01U , k_riic_icser_sar1e = 0x02U , k_riic_icser_sar2e = 0x04U , k_riic_icser_slots = 0x07U }
	ICSER (status enable) own-address slot-enable bits (ra8_i2c_regs.h). More...
enum	riic_tgt_phase_t : uint8_t { k_riic_tgt_idle = 0U , k_riic_tgt_write = 1U , k_riic_tgt_read = 2U , k_riic_tgt_done = 3U }
	RIIC target (peripheral) role: phases + synthetic external controller. More...
enum	riic_tgt_stim_t : uint8_t { k_riic_tgt_payload0 = 0xDEU , k_riic_tgt_payload1 = 0xADU , k_riic_tgt_payload_len = 2U , k_riic_tgt_cap = 8U , k_riic_tgt_cycles = 4U }
	Target-mode synthetic-controller payload + script size. More...
enum	riic_addr_t : uint32_t { k_riic_addr_shift = 1U , k_riic_addr_rnw = 0x01U , k_riic_addr_mask7 = 0x7FU , k_riic_byte_mask = 0xFFU , k_riic_dev_rx_max = 64U }
	I2C address-byte layout on the wire (addr<<1 \| R/W). More...

Functions
static void	internal_riic_open_transfer (riic_state_t *s)
	Begin a transaction (START or repeated-START): arm the address phase.
static void	internal_riic_close_transfer (riic_state_t *s)
	Close a transaction (STOP): release the bus and notify the device.
static void	internal_riic_address_phase (riic_state_t *s, uint8_t address_byte)
	Consume the address byte after a (re)START: select + ACK a device.
static void	internal_riic_icdrt_write (riic_state_t *s, uint32_t value)
	Handle a write to ICDRT (address byte, then controller TX payload).
static uint32_t	internal_riic_icdrr_read (riic_state_t *s)
	Serve one ICDRR read from the staged device response.
static void	internal_riic_iccr2_write (riic_state_t *s, uint64_t off, uint32_t value)
	Dispatch an ICCR2 write -> START / repeated-START / STOP.
static void	internal_riic_target_begin_write (riic_state_t *s)
	Arm the write phase: present the address-match + receive-ready state.
static void	internal_riic_target_begin_read (riic_state_t *s)
	Arm the read phase: present transmit-ready + transmit-end for the echo.
static void	internal_riic_target_complete_read (riic_state_t *s)
	Close one cycle: verify the echo, then loop the script or quiesce the bus.
static void	internal_riic_target_open (riic_state_t *s, uint32_t icser)
	(Dis)arm target mode on an ICSER write; latch the firmware's own address.
static uint32_t	internal_riic_target_icsr1 (const riic_state_t *s)
	ICSR1 read in target mode: assert the own-address match while active.
static uint32_t	internal_riic_target_iccr2 (const riic_state_t *s)
	ICCR2 read in target mode: assert TRS only while the controller reads.
static uint32_t	internal_riic_target_icdrr (riic_state_t *s)
	ICDRR read in target mode: serve the address byte, then the payload.
static void	internal_riic_target_icdrt (riic_state_t *s, uint8_t byte)
	ICDRT write in target mode: capture the firmware's echo byte.
static void	internal_riic_target_icsr2_write (riic_state_t *s, uint32_t value)
	ICSR2 W0C write in target mode: advance the write->read->done script.
static uint64_t	internal_riic_target_reg_read (riic_state_t *s, uint64_t off)
	Register read while target mode is armed (own-address responder path).
static uint64_t	internal_riic_reg_read (riic_state_t *s, uint64_t off)
	Read a register from one modelled RIIC channel.
static void	internal_riic_reg_write (riic_state_t *s, uint64_t off, uint32_t value)
	Write a register on one modelled RIIC channel.
static uint64_t	internal_riic_read (uc_engine *uc, uint64_t addr, unsigned size)
	MMIO read inside the RIIC window: route to the addressed channel.
static void	internal_riic_write (uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
	MMIO write inside the RIIC window: route to the addressed channel.
static void	internal_riic_reset (void)
	Clear the RIIC channels + expander state and (re)populate the bus.
static void	internal_riic_report (void)
	Print the PI4IOE line and any target-role responder activity.
static void	internal_board_periph_riic_register (void)
	Self-register the RIIC block before main runs (decentralized).

Variables
static const uint8_t	s_k_riic_tgt_payload [k_riic_tgt_payload_len]
	The synthetic controller's write payload (echoed back on read).
static riic_state_t	s_riic [k_riic_count]
	The three modelled RIIC controller channels.
static const board_periph_block_t	s_k_riic_block
	This block's descriptor (static lifetime; the core keeps the pointer).

Detailed Description

RIIC (IIC) controller + PI4IOE5V6408 I/O-expander + OV5640 SCCB model.

Models the RA8D2 RIIC peripheral – the classic Renesas I2C Bus Interface (HUM Ch 39), distinct from the I3C unified IP modelled in board_periph_i2c.c – that the ra8_i2c.c polling driver drives, plus the on-board PI4IOE5V6408 I/O port expander (U15) that answers on the modelled bus. So the i2c_loopback example's real ra8_i2c_init / ra8_i2c_write / ra8_i2c_scan path against U15 at 7-bit address 0x43 round-trips (the scan ACKs, the U15 register writes ACK) without a function-level stub.

Four cooperating pieces live here, mirroring board_periph_i2c.c:

The RIIC controller transfer state machine (START / RESTART / address / write / read / STOP) the driver clocks through ICCR2 / ICDRT / ICDRR / ICSR2.
A small I2C bus device registry mapping a 7-bit address to read / write / stop callbacks.
The PI4IOE5V6408 device: an auto-incrementing register pointer the controller writes first, then a payload (or a read of the addressed register), so the expander ACKs every probe and register write.
The OV5640 camera SCCB device (channel 1, 7-bit 0x3C): a 16-bit big-endian register pointer whose chip-ID registers (0x300A / 0x300B) answer 0x56 / 0x40 so camera_capture's VERIFY-FIRST sensor probe reads 0x5640 and reaches its CEU capture path (board_periph_ceu.c); config writes ACK and the firmware's post-configuration verifier registers read back their last written values. The register/value path is synthetic (no analog sensor) – a run-headless enabler, not a claim the board's camera streams.

Self-registers its descriptor (address range + read / write / reset / report) with the board_periph core from a file-scope constructor.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file board_periph_riic.c.

Enumeration Type Documentation

◆ riic_addr_t

enum riic_addr_t : uint32_t

I2C address-byte layout on the wire (addr<<1 | R/W).

Enumerator
k_riic_addr_shift	7-bit address occupies bits [7:1].
k_riic_addr_rnw	LSB: 1 == read, 0 == write.
k_riic_addr_mask7	7-bit target-address mask.
k_riic_byte_mask	One data byte.
k_riic_dev_rx_max	Per-read device response staging cap.

Definition at line 156 of file board_periph_riic.c.

◆ riic_console_t

enum riic_console_t : uint32_t

Console-tap line buffer capacity for a RIIC transaction summary.

Enumerator
k_riic_console_line_cap	Max chars in a "RIIC addr=.. .." line.

Definition at line 49 of file board_periph_riic.c.

◆ riic_iccr2_bit_t

enum riic_iccr2_bit_t : uint32_t

ICCR2 (control 2) bits the model acts on (ra8_i2c_regs.h).

Enumerator
k_riic_iccr2_st	ST: issue START (bit 1).
k_riic_iccr2_rs	RS: issue repeated-START (bit 2).
k_riic_iccr2_sp	SP: issue STOP (bit 3).
k_riic_iccr2_trs	TRS: transmit/receive mode (bit 5).
k_riic_iccr2_mst	MST: controller/peripheral (bit 6).
k_riic_iccr2_bbsy	BBSY: bus-busy flag, RO (bit 7).

Definition at line 84 of file board_periph_riic.c.

◆ riic_icser_bit_t

enum riic_icser_bit_t : uint32_t

ICSER (status enable) own-address slot-enable bits (ra8_i2c_regs.h).

Enumerator
k_riic_icser_sar0e	SAR0E: own-address slot 0 enable (bit 0).
k_riic_icser_sar1e	SAR1E: own-address slot 1 enable (bit 1).
k_riic_icser_sar2e	SAR2E: own-address slot 2 enable (bit 2).
k_riic_icser_slots	Any own-address slot enabled (SARyE).

Definition at line 111 of file board_periph_riic.c.

◆ riic_icsr1_bit_t

enum riic_icsr1_bit_t : uint32_t

ICSR1 (status 1) own-address match flags (ra8_i2c_regs.h).

Enumerator
k_riic_icsr1_aas0	AAS0: own-address slot 0 matched (bit 0).

Definition at line 106 of file board_periph_riic.c.

◆ riic_icsr2_bit_t

enum riic_icsr2_bit_t : uint32_t

ICSR2 (status 2) flags the driver polls / clears (ra8_i2c_regs.h).

Enumerator
k_riic_icsr2_tmof	TMOF: timeout detected (bit 0).
k_riic_icsr2_al	AL: arbitration lost (bit 1).
k_riic_icsr2_start	START: start-condition detected (bit 2).
k_riic_icsr2_stop	STOP: stop-condition detected (bit 3).
k_riic_icsr2_nackf	NACKF: NACK detected (bit 4).
k_riic_icsr2_rdrf	RDRF: receive data full (bit 5).
k_riic_icsr2_tend	TEND: transmit end (bit 6).
k_riic_icsr2_tdre	TDRE: transmit data empty (bit 7).

Definition at line 94 of file board_periph_riic.c.

◆ riic_map_t

enum riic_map_t : uint64_t

RIIC block geometry (ra8_i2c_regs.h, byte-wide register file).

The RA8D2 has three RIIC channels at 0x4025E000 + 0x100 * n. The U15 I/O expander and the system I2C bus live on channel 1 (P512 SCL1 / P511 SDA1), which the i2c_loopback example and ra8_board_io_expander_apply_project_sw4_defaults drive. Every RIIC register is a single byte; the polling driver (libs/ra8_hal/src/ra8_i2c.c) only touches the registers named here. Offsets match the r_i2c_regs_t struct in ra8_i2c_regs.h.

Enumerator
k_riic_base	IIC0 base (channel 0).
k_riic_stride	Bytes per RIIC channel.
k_riic_count	IIC0 / IIC1 / IIC2.
k_riic_span	All three channel windows.
k_riic_off_iccr1	ICCR1 control 1 (ICE / IICRST).
k_riic_off_iccr2	ICCR2 control 2 (ST/RS/SP/BBSY).
k_riic_off_icmr3	ICMR3 mode 3 (ACKWP/ACKBT/WAIT).
k_riic_off_icser	ICSER own-address enable (SARyE).
k_riic_off_icsr1	ICSR1 status 1 (AASy own-addr).
k_riic_off_icsr2	ICSR2 status 2 (TDRE/TEND/...).
k_riic_off_sarl0	SARL0 own-address low, slot 0.
k_riic_off_sarl1	SARL1 own-address low, slot 1.
k_riic_off_sarl2	SARL2 own-address low, slot 2.
k_riic_off_icdrt	ICDRT transmit data register.
k_riic_off_icdrr	ICDRR receive data register.
k_riic_reg_bytes	Shadow byte count for one channel.

Definition at line 64 of file board_periph_riic.c.

◆ riic_tgt_phase_t

enum riic_tgt_phase_t : uint8_t

RIIC target (peripheral) role: phases + synthetic external controller.

The RA8D2 answers as an I2C target once the ra8_i2c target driver programmes an own address (SARLy) and enables its slot (ICSER.SARyE) – the i2c_peripheral_responder example. On the bench a remote controller drives the bus; headless, ra8_emulator IS that controller. The stimulus drives a fixed write-then-read script: it writes a known payload to the target (the driver's ra8_i2c_peripheral_receive path drains it), then reads the target back (the _transmit path echoes it), for k_riic_tgt_cycles cycles, and verifies the echo matches. The addressing byte position (dummy ICDRR read), RDRF/STOP receive handshake, and TDRE/TEND transmit handshake mirror HUM Ch 39.3.5 / 39.3.6, so the genuine target driver runs unmodified.

Enumerator
k_riic_tgt_idle	No own address armed; target model inert.
k_riic_tgt_write	Controller is writing the payload (RDRF/STOP).
k_riic_tgt_read	Controller is reading the echo (TDRE/TEND).
k_riic_tgt_done	Script complete; the bus is quiet (no match).

Definition at line 133 of file board_periph_riic.c.

◆ riic_tgt_stim_t

enum riic_tgt_stim_t : uint8_t

Target-mode synthetic-controller payload + script size.

Enumerator
k_riic_tgt_payload0	First byte the synthetic controller writes.
k_riic_tgt_payload1	Second byte the synthetic controller writes.
k_riic_tgt_payload_len	Bytes per write (and expected echo length).
k_riic_tgt_cap	Echo-capture buffer bound.
k_riic_tgt_cycles	Write+read cycles the stimulus drives.

Definition at line 141 of file board_periph_riic.c.

Function Documentation

◆ internal_board_periph_riic_register()

void internal_board_periph_riic_register ( void )

static

Self-register the RIIC block before main runs (decentralized).

Definition at line 802 of file board_periph_riic.c.

References board_periph_register_block(), RA8_INTERNAL, and s_k_riic_block.

◆ internal_riic_address_phase()

void internal_riic_address_phase	(	riic_state_t *	s,
		uint8_t	address_byte )

static

Consume the address byte after a (re)START: select + ACK a device.

Consume the address byte after a (re)start: select + ack a device; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	address_byte	Address byte input used by the operation.

Precondition: Arguments satisfy the ranges documented for RIIC address phase.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 280 of file board_periph_riic.c.

References riic_state_t::acked, riic_state_t::addr_done, riic_device_t::ctx, riic_state_t::icsr2, k_riic_addr_mask7, k_riic_addr_rnw, k_riic_addr_shift, k_riic_dev_rx_max, k_riic_icsr2_nackf, k_riic_icsr2_rdrf, k_riic_icsr2_tdre, k_riic_icsr2_tend, priv_riic_device_find(), RA8_INTERNAL, riic_device_t::read, riic_state_t::reading, riic_state_t::rx, riic_state_t::rx_len, riic_state_t::rx_pos, riic_state_t::rx_primed, and riic_state_t::target_7b.

Referenced by internal_riic_icdrt_write().

◆ internal_riic_close_transfer()

void internal_riic_close_transfer ( riic_state_t * s )

static

Close a transaction (STOP): release the bus and notify the device.

Close a transaction (stop): release the bus and notify the device; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out] s Module state instance processed by the operation.

Precondition: Arguments satisfy the ranges documented for RIIC close transfer.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 242 of file board_periph_riic.c.

References riic_state_t::acked, riic_state_t::addr_done, board_console_push(), riic_state_t::busy, riic_device_t::ctx, riic_state_t::icsr2, k_board_console_ch_i2c, k_riic_console_line_cap, k_riic_icsr2_stop, priv_riic_device_find(), RA8_INTERNAL, riic_state_t::reading, riic_state_t::rx_len, riic_device_t::stop, and riic_state_t::target_7b.

Referenced by internal_riic_iccr2_write().

◆ internal_riic_iccr2_write()

void internal_riic_iccr2_write	(	riic_state_t *	s,
		uint64_t	off,
		uint32_t	value )

static

Dispatch an ICCR2 write -> START / repeated-START / STOP.

Dispatch an iccr2 write -> start / repeated-start / stop; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	off	Register or byte offset addressed by the operation.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for RIIC iccr2 write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 374 of file board_periph_riic.c.

References internal_riic_close_transfer(), internal_riic_open_transfer(), k_riic_iccr2_rs, k_riic_iccr2_sp, k_riic_iccr2_st, RA8_INTERNAL, and riic_state_t::reg.

Referenced by internal_riic_reg_write().

◆ internal_riic_icdrr_read()

uint32_t internal_riic_icdrr_read ( riic_state_t * s )

static

Serve one ICDRR read from the staged device response.

Serve one icdrr read from the staged device response; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out] s Module state instance processed by the operation.

Returns: The RIIC icdrr read result produced by the board periph RIIC model.

Return values

value The operation-specific RIIC icdrr read value.

Precondition: Arguments satisfy the ranges documented for RIIC icdrr read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 346 of file board_periph_riic.c.

References riic_state_t::icsr2, k_riic_icsr2_rdrf, RA8_INTERNAL, riic_state_t::rx, riic_state_t::rx_len, riic_state_t::rx_pos, and riic_state_t::rx_primed.

Referenced by internal_riic_reg_read().

◆ internal_riic_icdrt_write()

void internal_riic_icdrt_write	(	riic_state_t *	s,
		uint32_t	value )

static

Handle a write to ICDRT (address byte, then controller TX payload).

Handle a write to icdrt (address byte, then controller tx payload); this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for RIIC icdrt write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 317 of file board_periph_riic.c.

References riic_state_t::acked, riic_state_t::addr_done, riic_device_t::ctx, riic_state_t::icsr2, internal_riic_address_phase(), k_riic_byte_mask, k_riic_icsr2_tdre, k_riic_icsr2_tend, priv_riic_device_find(), RA8_INTERNAL, riic_state_t::target_7b, and riic_device_t::write.

Referenced by internal_riic_reg_write().

◆ internal_riic_open_transfer()

void internal_riic_open_transfer ( riic_state_t * s )

static

Begin a transaction (START or repeated-START): arm the address phase.

Begin a transaction (start or repeated-start): arm the address phase; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out] s Module state instance processed by the operation.

Precondition: Arguments satisfy the ranges documented for RIIC open transfer.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 219 of file board_periph_riic.c.

References riic_state_t::acked, riic_state_t::addr_done, riic_state_t::busy, riic_state_t::icsr2, k_riic_icsr2_tdre, RA8_INTERNAL, riic_state_t::reading, riic_state_t::rx_len, riic_state_t::rx_pos, and riic_state_t::rx_primed.

Referenced by internal_riic_iccr2_write().

◆ internal_riic_read()

uint64_t internal_riic_read	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size )

static

MMIO read inside the RIIC window: route to the addressed channel.

MMIO read inside the riic window: route to the addressed channel; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.

Returns: The RIIC read result produced by the board periph RIIC model.

Return values

value The operation-specific RIIC read value.

Precondition: Arguments satisfy the ranges documented for RIIC read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 713 of file board_periph_riic.c.

References internal_riic_reg_read(), k_riic_base, k_riic_reg_bytes, k_riic_stride, RA8_INTERNAL, and s_riic.

◆ internal_riic_reg_read()

uint64_t internal_riic_reg_read	(	riic_state_t *	s,
		uint64_t	off )

static

Read a register from one modelled RIIC channel.

Read a register from one modelled riic channel; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	off	Register or byte offset addressed by the operation.

Returns: The RIIC reg read result produced by the board periph RIIC model.

Return values

value The operation-specific RIIC reg read value.

Precondition: Arguments satisfy the ranges documented for RIIC reg read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 640 of file board_periph_riic.c.

References riic_state_t::busy, riic_state_t::icsr2, internal_riic_icdrr_read(), internal_riic_target_reg_read(), k_riic_iccr2_bbsy, k_riic_off_iccr2, k_riic_off_icdrr, k_riic_off_icsr2, RA8_INTERNAL, riic_state_t::reg, and riic_state_t::tgt_armed.

Referenced by internal_riic_read().

◆ internal_riic_reg_write()

void internal_riic_reg_write	(	riic_state_t *	s,
		uint64_t	off,
		uint32_t	value )

static

Write a register on one modelled RIIC channel.

Write a register on one modelled riic channel; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	off	Register or byte offset addressed by the operation.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for RIIC reg write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 673 of file board_periph_riic.c.

References riic_state_t::icsr2, internal_riic_iccr2_write(), internal_riic_icdrt_write(), internal_riic_target_icdrt(), internal_riic_target_icsr2_write(), internal_riic_target_open(), k_riic_byte_mask, k_riic_off_iccr2, k_riic_off_icdrt, k_riic_off_icser, k_riic_off_icsr2, RA8_INTERNAL, riic_state_t::reg, and riic_state_t::tgt_armed.

Referenced by internal_riic_write().

◆ internal_riic_report()

void internal_riic_report ( void )

static

Print the PI4IOE line and any target-role responder activity.

Print the pi4ioe line and any target-role responder activity; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Precondition: Arguments satisfy the ranges documented for RIIC report.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 774 of file board_periph_riic.c.

References k_riic_count, priv_emu_io_errf(), priv_riic_devices_report(), RA8_INTERNAL, and s_riic.

◆ internal_riic_reset()

void internal_riic_reset ( void )

static

Clear the RIIC channels + expander state and (re)populate the bus.

Clear the riic channels + expander state and (re)populate the bus; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Precondition: Arguments satisfy the ranges documented for RIIC reset.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 758 of file board_periph_riic.c.

References k_riic_count, priv_riic_devices_reset(), RA8_INTERNAL, and s_riic.

◆ internal_riic_target_begin_read()

void internal_riic_target_begin_read ( riic_state_t * s )

static

Arm the read phase: present transmit-ready + transmit-end for the echo.

Arm the read phase: present transmit-ready + transmit-end for the echo; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out] s Module state instance processed by the operation.

Precondition: Arguments satisfy the ranges documented for RIIC target begin read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 419 of file board_periph_riic.c.

References k_riic_icsr2_tdre, k_riic_icsr2_tend, k_riic_tgt_read, RA8_INTERNAL, riic_state_t::tgt_icsr2, riic_state_t::tgt_phase, and riic_state_t::tgt_rd_len.

Referenced by internal_riic_target_icsr2_write().

◆ internal_riic_target_begin_write()

void internal_riic_target_begin_write ( riic_state_t * s )

static

Arm the write phase: present the address-match + receive-ready state.

Arm the write phase: present the address-match + receive-ready state; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out] s Module state instance processed by the operation.

Precondition: Arguments satisfy the ranges documented for RIIC target begin write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 403 of file board_periph_riic.c.

References k_riic_icsr2_rdrf, k_riic_tgt_write, RA8_INTERNAL, riic_state_t::tgt_icsr2, riic_state_t::tgt_phase, and riic_state_t::tgt_wr_pos.

Referenced by internal_riic_target_complete_read(), and internal_riic_target_open().

◆ internal_riic_target_complete_read()

void internal_riic_target_complete_read ( riic_state_t * s )

static

Close one cycle: verify the echo, then loop the script or quiesce the bus.

Close one cycle: verify the echo, then loop the script or quiesce the bus; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out] s Module state instance processed by the operation.

Precondition: Arguments satisfy the ranges documented for RIIC target complete read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 435 of file board_periph_riic.c.

References internal_riic_target_begin_write(), k_riic_tgt_cycles, k_riic_tgt_done, k_riic_tgt_payload_len, RA8_INTERNAL, s_k_riic_tgt_payload, riic_state_t::tgt_cycles, riic_state_t::tgt_echo_bad, riic_state_t::tgt_icsr2, riic_state_t::tgt_phase, riic_state_t::tgt_rd, and riic_state_t::tgt_rd_len.

Referenced by internal_riic_target_icsr2_write().

◆ internal_riic_target_iccr2()

uint32_t internal_riic_target_iccr2 ( const riic_state_t * s )

static

ICCR2 read in target mode: assert TRS only while the controller reads.

Iccr2 read in target mode: assert trs only while the controller reads; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in] s Module state instance processed by the operation.

Returns: The RIIC target iccr2 result produced by the board periph RIIC model.

Return values

value The operation-specific RIIC target iccr2 value.

Precondition: Arguments satisfy the ranges documented for RIIC target iccr2.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 516 of file board_periph_riic.c.

References k_riic_iccr2_trs, k_riic_off_iccr2, k_riic_tgt_read, RA8_INTERNAL, riic_state_t::reg, and riic_state_t::tgt_phase.

Referenced by internal_riic_target_reg_read().

◆ internal_riic_target_icdrr()

uint32_t internal_riic_target_icdrr ( riic_state_t * s )

static

ICDRR read in target mode: serve the address byte, then the payload.

Icdrr read in target mode: serve the address byte, then the payload; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out] s Module state instance processed by the operation.

Returns: The RIIC target icdrr result produced by the board periph RIIC model.

Return values

value The operation-specific RIIC target icdrr value.

Precondition: Arguments satisfy the ranges documented for RIIC target icdrr.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 536 of file board_periph_riic.c.

References k_riic_addr_shift, k_riic_icsr2_rdrf, k_riic_icsr2_stop, k_riic_tgt_payload_len, k_riic_tgt_write, RA8_INTERNAL, s_k_riic_tgt_payload, riic_state_t::tgt_icsr2, riic_state_t::tgt_own_addr, riic_state_t::tgt_phase, and riic_state_t::tgt_wr_pos.

Referenced by internal_riic_target_reg_read().

◆ internal_riic_target_icdrt()

void internal_riic_target_icdrt	(	riic_state_t *	s,
		uint8_t	byte )

static

ICDRT write in target mode: capture the firmware's echo byte.

Icdrt write in target mode: capture the firmware's echo byte; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	byte	One data byte received from or sent to the emulated interface.

Precondition: Arguments satisfy the ranges documented for RIIC target icdrt.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 567 of file board_periph_riic.c.

References k_riic_tgt_cap, k_riic_tgt_read, RA8_INTERNAL, riic_state_t::tgt_phase, riic_state_t::tgt_rd, and riic_state_t::tgt_rd_len.

Referenced by internal_riic_reg_write().

◆ internal_riic_target_icsr1()

uint32_t internal_riic_target_icsr1 ( const riic_state_t * s )

static

ICSR1 read in target mode: assert the own-address match while active.

Icsr1 read in target mode: assert the own-address match while active; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in] s Module state instance processed by the operation.

Returns: The RIIC target icsr1 result produced by the board periph RIIC model.

Return values

value The operation-specific RIIC target icsr1 value.

Precondition: Arguments satisfy the ranges documented for RIIC target icsr1.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 494 of file board_periph_riic.c.

References k_riic_icsr1_aas0, k_riic_tgt_read, k_riic_tgt_write, RA8_INTERNAL, and riic_state_t::tgt_phase.

Referenced by internal_riic_target_reg_read().

◆ internal_riic_target_icsr2_write()

void internal_riic_target_icsr2_write	(	riic_state_t *	s,
		uint32_t	value )

static

ICSR2 W0C write in target mode: advance the write->read->done script.

Icsr2 w0c write in target mode: advance the write->read->done script; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for RIIC target icsr2 write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 589 of file board_periph_riic.c.

References internal_riic_target_begin_read(), internal_riic_target_complete_read(), k_riic_tgt_read, k_riic_tgt_write, RA8_INTERNAL, riic_state_t::tgt_icsr2, and riic_state_t::tgt_phase.

Referenced by internal_riic_reg_write().

◆ internal_riic_target_open()

void internal_riic_target_open	(	riic_state_t *	s,
		uint32_t	icser )

static

(Dis)arm target mode on an ICSER write; latch the firmware's own address.

(dis)arm target mode on an icser write; latch the firmware's own address; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	icser	Icser input used by the operation.

Precondition: Arguments satisfy the ranges documented for RIIC target open.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 465 of file board_periph_riic.c.

References internal_riic_target_begin_write(), k_riic_addr_shift, k_riic_icser_sar1e, k_riic_icser_sar2e, k_riic_icser_slots, k_riic_off_sarl0, k_riic_off_sarl1, k_riic_off_sarl2, k_riic_tgt_idle, RA8_INTERNAL, riic_state_t::reg, riic_state_t::tgt_armed, riic_state_t::tgt_own_addr, and riic_state_t::tgt_phase.

Referenced by internal_riic_reg_write().

◆ internal_riic_target_reg_read()

uint64_t internal_riic_target_reg_read	(	riic_state_t *	s,
		uint64_t	off )

static

Register read while target mode is armed (own-address responder path).

Register read while target mode is armed (own-address responder path); this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	s	Module state instance processed by the operation.
[in]	off	Register or byte offset addressed by the operation.

Returns: The RIIC target reg read result produced by the board periph RIIC model.

Return values

value The operation-specific RIIC target reg read value.

Precondition: Arguments satisfy the ranges documented for RIIC target reg read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 611 of file board_periph_riic.c.

References internal_riic_target_iccr2(), internal_riic_target_icdrr(), internal_riic_target_icsr1(), k_riic_off_iccr2, k_riic_off_icdrr, k_riic_off_icsr1, k_riic_off_icsr2, RA8_INTERNAL, riic_state_t::reg, and riic_state_t::tgt_icsr2.

Referenced by internal_riic_reg_read().

◆ internal_riic_write()

void internal_riic_write	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size,
		uint64_t	value )

static

MMIO write inside the RIIC window: route to the addressed channel.

MMIO write inside the riic window: route to the addressed channel; this step is contained within the board periph RIIC model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for RIIC write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph RIIC model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 738 of file board_periph_riic.c.

References internal_riic_reg_write(), k_riic_base, k_riic_reg_bytes, k_riic_stride, and s_riic.

Variable Documentation

◆ s_k_riic_block

const board_periph_block_t s_k_riic_block

static

Initial value:

                                                 = {
  .base   = (uint64_t)k_riic_base,
  .span   = (uint64_t)k_riic_span,
  .order  = (uint32_t)k_block_order_i2c,
  .read   = internal_riic_read,
  .write  = internal_riic_write,
  .tick   = nullptr,
  .reset  = internal_riic_reset,
  .report = internal_riic_report,
  .name   = "RIIC+PI4IOE",
}

This block's descriptor (static lifetime; the core keeps the pointer).

Definition at line 789 of file board_periph_riic.c.

Referenced by internal_board_periph_riic_register().

◆ s_k_riic_tgt_payload

const uint8_t s_k_riic_tgt_payload[k_riic_tgt_payload_len]

static

Initial value:

                                          = {
  (uint8_t)k_riic_tgt_payload0,
  (uint8_t)k_riic_tgt_payload1,
}

The synthetic controller's write payload (echoed back on read).

Definition at line 150 of file board_periph_riic.c.

Referenced by internal_riic_target_complete_read(), and internal_riic_target_icdrr().

◆ s_riic

riic_state_t s_riic[k_riic_count]

static

The three modelled RIIC controller channels.

Definition at line 202 of file board_periph_riic.c.

Referenced by internal_riic_read(), internal_riic_report(), internal_riic_reset(), and internal_riic_write().

Data Structures

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ riic_addr_t

◆ riic_console_t

◆ riic_iccr2_bit_t

◆ riic_icser_bit_t

◆ riic_icsr1_bit_t

◆ riic_icsr2_bit_t

◆ riic_map_t

◆ riic_tgt_phase_t

◆ riic_tgt_stim_t

Function Documentation

◆ internal_board_periph_riic_register()

◆ internal_riic_address_phase()

◆ internal_riic_close_transfer()

◆ internal_riic_iccr2_write()

◆ internal_riic_icdrr_read()

◆ internal_riic_icdrt_write()

◆ internal_riic_open_transfer()

◆ internal_riic_read()

◆ internal_riic_reg_read()

◆ internal_riic_reg_write()

◆ internal_riic_report()

◆ internal_riic_reset()

◆ internal_riic_target_begin_read()

◆ internal_riic_target_begin_write()

◆ internal_riic_target_complete_read()

◆ internal_riic_target_iccr2()

◆ internal_riic_target_icdrr()

◆ internal_riic_target_icdrt()

◆ internal_riic_target_icsr1()

◆ internal_riic_target_icsr2_write()

◆ internal_riic_target_open()

◆ internal_riic_target_reg_read()

◆ internal_riic_write()

Variable Documentation

◆ s_k_riic_block

◆ s_k_riic_tgt_payload

◆ s_riic