board_periph_riic.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_console.h"
#include "board_periph_block.h"
#include "board_periph_riic_devices_internal.h"
#include "emu_host_io_internal.h"

typedef enum : uint32_t {
  k_riic_console_line_cap = 48U, 
} riic_console_t;

typedef enum : uint64_t {
  k_riic_base      = 0x4025E000UL,  
  k_riic_stride    = 0x100UL,       
  k_riic_count     = 3UL,           
  k_riic_span      = 0x100UL * 3UL, 
  k_riic_off_iccr1 = 0x00UL,        
  k_riic_off_iccr2 = 0x01UL,        
  k_riic_off_icmr3 = 0x04UL,        
  k_riic_off_icser = 0x06UL,        
  k_riic_off_icsr1 = 0x08UL,        
  k_riic_off_icsr2 = 0x09UL,        
  k_riic_off_sarl0 = 0x0AUL,        
  k_riic_off_sarl1 = 0x0CUL,        
  k_riic_off_sarl2 = 0x0EUL,        
  k_riic_off_icdrt = 0x12UL,        
  k_riic_off_icdrr = 0x13UL,        
  k_riic_reg_bytes = 0x16UL,        
} riic_map_t;

typedef enum : uint32_t {
  k_riic_iccr2_st   = 0x02U, 
  k_riic_iccr2_rs   = 0x04U, 
  k_riic_iccr2_sp   = 0x08U, 
  k_riic_iccr2_trs  = 0x20U, 
  k_riic_iccr2_mst  = 0x40U, 
  k_riic_iccr2_bbsy = 0x80U, 
} riic_iccr2_bit_t;

typedef enum : uint32_t {
  k_riic_icsr2_tmof  = 0x01U, 
  k_riic_icsr2_al    = 0x02U, 
  k_riic_icsr2_start = 0x04U, 
  k_riic_icsr2_stop  = 0x08U, 
  k_riic_icsr2_nackf = 0x10U, 
  k_riic_icsr2_rdrf  = 0x20U, 
  k_riic_icsr2_tend  = 0x40U, 
  k_riic_icsr2_tdre  = 0x80U, 
} riic_icsr2_bit_t;

typedef enum : uint32_t {
  k_riic_icsr1_aas0 = 0x01U, 
} riic_icsr1_bit_t;

typedef enum : uint32_t {
  k_riic_icser_sar0e = 0x01U, 
  k_riic_icser_sar1e = 0x02U, 
  k_riic_icser_sar2e = 0x04U, 
  k_riic_icser_slots = 0x07U, 
} riic_icser_bit_t;

typedef enum : uint8_t {
  k_riic_tgt_idle  = 0U, 
  k_riic_tgt_write = 1U, 
  k_riic_tgt_read  = 2U, 
  k_riic_tgt_done  = 3U, 
} riic_tgt_phase_t;

typedef enum : uint8_t {
  k_riic_tgt_payload0    = 0xDEU, 
  k_riic_tgt_payload1    = 0xADU, 
  k_riic_tgt_payload_len = 2U,    
  k_riic_tgt_cap         = 8U,    
  k_riic_tgt_cycles      = 4U,    
} riic_tgt_stim_t;

static const uint8_t s_k_riic_tgt_payload[k_riic_tgt_payload_len] = {
  (uint8_t)k_riic_tgt_payload0,
  (uint8_t)k_riic_tgt_payload1,
};

typedef enum : uint32_t {
  k_riic_addr_shift = 1U,    
  k_riic_addr_rnw   = 0x01U, 
  k_riic_addr_mask7 = 0x7FU, 
  k_riic_byte_mask  = 0xFFU, 
  k_riic_dev_rx_max = 64U,   
} riic_addr_t;

typedef struct {
  uint8_t  reg[k_riic_reg_bytes]; 
  uint32_t icsr2;                 
  bool     busy;                  
  bool     addr_done;             
  bool     acked;                 
  bool     reading;               
  uint8_t  target_7b;             
  uint8_t  rx[k_riic_dev_rx_max]; 
  uint32_t rx_len;                
  uint32_t rx_pos;                
  bool     rx_primed;             
  /* Target (peripheral) role: this model is the synthetic external controller. */
  bool     tgt_armed;              
  uint8_t  tgt_own_addr;           
  uint8_t  tgt_phase;              
  uint32_t tgt_icsr2;              
  uint32_t tgt_wr_pos;             
  uint32_t tgt_rd_len;             
  uint32_t tgt_cycles;             
  bool     tgt_echo_bad;           
  uint8_t  tgt_rd[k_riic_tgt_cap]; 
} riic_state_t;

static riic_state_t s_riic[k_riic_count];
 
/* =============================================================================
 * RIIC controller model -- the transfer state machine the ra8_i2c.c polling
 * driver drives (START / RESTART / addr / write / read / STOP).
 * =============================================================================
 */

RA8_INTERNAL static void internal_riic_open_transfer(riic_state_t* s)
{
  s->busy      = true;
  s->addr_done = false;
  s->acked     = false;
  s->reading   = false;
  s->rx_len    = 0U;
  s->rx_pos    = 0U;
  s->rx_primed = false;
  /* Transmit buffer is empty so the driver can write the address byte; clear
   * the stale condition / fault flags so the new phase reports its own. */
  s->icsr2 = (uint32_t)k_riic_icsr2_tdre;
}

RA8_INTERNAL static void internal_riic_close_transfer(riic_state_t* s)
{
  if (s->acked) {
    riic_device_t* dev = priv_riic_device_find(s->target_7b);
    if (dev != nullptr) {
      if (dev->stop != nullptr) {
        dev->stop(dev->ctx);
      }
    }
    /* Console I2C tab: one line per completed (ACKed) RIIC transaction at STOP
     * (RIIC shares the I2C tab with the IIC_B model). */
    char ln[k_riic_console_line_cap];
    if (s->reading) {
      (void)snprintf(ln,
                     sizeof(ln),
                     "RIIC addr=0x%02X R %uB",
                     (unsigned)s->target_7b,
                     (unsigned)s->rx_len);
    } else {
      (void)snprintf(ln, sizeof(ln), "RIIC addr=0x%02X W", (unsigned)s->target_7b);
    }
    board_console_push(k_board_console_ch_i2c, ln);
  }
  s->busy      = false;
  s->addr_done = false;
  s->icsr2     = (uint32_t)k_riic_icsr2_stop;
}

RA8_INTERNAL static void internal_riic_address_phase(riic_state_t* s, uint8_t address_byte)
{
  s->target_7b =
    (uint8_t)((uint32_t)address_byte >> (uint32_t)k_riic_addr_shift) & (uint8_t)k_riic_addr_mask7;
  s->reading   = ((uint32_t)address_byte & (uint32_t)k_riic_addr_rnw) != 0U;
  s->addr_done = true;
 
  riic_device_t* dev = priv_riic_device_find(s->target_7b);
  if (dev == nullptr) {
    /* No device at this address: NACK it (scan reports ack=0). */
    s->acked = false;
    s->icsr2 |=
      ((uint32_t)k_riic_icsr2_nackf | (uint32_t)k_riic_icsr2_tend | (uint32_t)k_riic_icsr2_tdre);
    return;
  }
  s->acked = true;
  /* Address ACKed: TEND lets the scan / write proceed, TDRE re-arms TX. */
  s->icsr2 |= ((uint32_t)k_riic_icsr2_tend | (uint32_t)k_riic_icsr2_tdre);
  if (s->reading) {
    /* Pre-fetch the device's response for this read so ICDRR reads serve it. */
    s->rx_len    = dev->read(dev->ctx, s->rx, (uint32_t)k_riic_dev_rx_max);
    s->rx_pos    = 0U;
    s->rx_primed = false;
    s->icsr2 |= (uint32_t)k_riic_icsr2_rdrf; /* RX data ready */
  }
}

RA8_INTERNAL static void internal_riic_icdrt_write(riic_state_t* s, uint32_t value)
{
  const uint8_t byte = (uint8_t)(value & (uint32_t)k_riic_byte_mask);
  if (!s->addr_done) {
    internal_riic_address_phase(s, byte);
    return;
  }
  if (!s->acked) {
    return; /* NACKed address: swallow further writes until STOP */
  }
  riic_device_t* dev = priv_riic_device_find(s->target_7b);
  if ((dev != nullptr) && (dev->write != nullptr)) {
    dev->write(dev->ctx, byte);
  }
  /* Buffer empty again and the byte was accepted: TDRE + TEND for the next. */
  s->icsr2 |= ((uint32_t)k_riic_icsr2_tdre | (uint32_t)k_riic_icsr2_tend);
}

RA8_INTERNAL static uint32_t internal_riic_icdrr_read(riic_state_t* s)
{
  if (!s->rx_primed) {
    /* The controller-receive flow does one dummy ICDRR read to start the clock
     * before the first real byte (HUM Ch 39.3.4). */
    s->rx_primed = true;
    return 0U;
  }
  uint8_t b = 0U;
  if (s->rx_pos < s->rx_len) {
    b = s->rx[s->rx_pos];
    s->rx_pos++;
  }
  s->icsr2 |= (uint32_t)k_riic_icsr2_rdrf; /* keep RX-ready for the next byte */
  return (uint32_t)b;
}

RA8_INTERNAL static void internal_riic_iccr2_write(riic_state_t* s, uint64_t off, uint32_t value)
{
  if ((value & ((uint32_t)k_riic_iccr2_st | (uint32_t)k_riic_iccr2_rs)) != 0U) {
    internal_riic_open_transfer(s);
    /* ST / RS auto-clear once the condition is issued; the driver spins on RS
     * reading 0 after a repeated-START, so drop both request bits. */
    s->reg[off] = (uint8_t)(value & ~((uint32_t)k_riic_iccr2_st | (uint32_t)k_riic_iccr2_rs));
  } else if ((value & (uint32_t)k_riic_iccr2_sp) != 0U) {
    internal_riic_close_transfer(s);
    s->reg[off] = (uint8_t)(value & ~(uint32_t)k_riic_iccr2_sp);
  }
}
 
/* =============================================================================
 * RIIC target (peripheral) model -- ra8_emulator is the synthetic external
 * controller, driving a write-then-read script at the firmware's own address so
 * the real ra8_i2c_peripheral_* driver (receive / transmit / dispatch) runs.
 * =============================================================================
 */

RA8_INTERNAL static void internal_riic_target_begin_write(riic_state_t* s)
{
  s->tgt_phase  = (uint8_t)k_riic_tgt_write;
  s->tgt_wr_pos = 0U;
  s->tgt_icsr2  = (uint32_t)k_riic_icsr2_rdrf; /* address + first data byte ready */
}

RA8_INTERNAL static void internal_riic_target_begin_read(riic_state_t* s)
{
  s->tgt_phase  = (uint8_t)k_riic_tgt_read;
  s->tgt_rd_len = 0U;
  s->tgt_icsr2  = (uint32_t)k_riic_icsr2_tdre | (uint32_t)k_riic_icsr2_tend;
}

RA8_INTERNAL static void internal_riic_target_complete_read(riic_state_t* s)
{
  bool ok = (s->tgt_rd_len == (uint32_t)k_riic_tgt_payload_len);
  for (uint32_t i = 0U; i < (uint32_t)k_riic_tgt_payload_len; i++) {
    if (s->tgt_rd[i] != s_k_riic_tgt_payload[i]) {
      ok = false;
    }
  }
  if (!ok) {
    s->tgt_echo_bad = true;
  }
  s->tgt_cycles++;
  if (s->tgt_cycles < (uint32_t)k_riic_tgt_cycles) {
    internal_riic_target_begin_write(s);
  } else {
    s->tgt_phase = (uint8_t)k_riic_tgt_done;
    s->tgt_icsr2 = 0U; /* no match, no STOP: dispatch reports no event forever. */
  }
}

RA8_INTERNAL static void internal_riic_target_open(riic_state_t* s, uint32_t icser)
{
  if ((icser & (uint32_t)k_riic_icser_slots) == 0U) {
    s->tgt_armed = false;
    s->tgt_phase = (uint8_t)k_riic_tgt_idle;
    return;
  }
  uint8_t sarl = s->reg[k_riic_off_sarl0];
  if ((icser & (uint32_t)k_riic_icser_sar1e) != 0U) {
    sarl = s->reg[k_riic_off_sarl1];
  } else if ((icser & (uint32_t)k_riic_icser_sar2e) != 0U) {
    sarl = s->reg[k_riic_off_sarl2];
  }
  s->tgt_own_addr = (uint8_t)((uint32_t)sarl >> (uint32_t)k_riic_addr_shift);
  s->tgt_armed    = true;
  internal_riic_target_begin_write(s);
}

RA8_INTERNAL static uint32_t internal_riic_target_icsr1(const riic_state_t* s)
{
  if (s->tgt_phase == (uint8_t)k_riic_tgt_write) {
    return (uint32_t)k_riic_icsr1_aas0;
  }
  if (s->tgt_phase == (uint8_t)k_riic_tgt_read) {
    return (uint32_t)k_riic_icsr1_aas0;
  }
  return 0U;
}

RA8_INTERNAL static uint32_t internal_riic_target_iccr2(const riic_state_t* s)
{
  uint32_t v = (uint32_t)s->reg[k_riic_off_iccr2] & ~(uint32_t)k_riic_iccr2_trs;
  if (s->tgt_phase == (uint8_t)k_riic_tgt_read) {
    v |= (uint32_t)k_riic_iccr2_trs;
  }
  return v;
}

RA8_INTERNAL static uint32_t internal_riic_target_icdrr(riic_state_t* s)
{
  if (s->tgt_phase != (uint8_t)k_riic_tgt_write) {
    return 0U; /* read-phase SCL-release dummy read / idle: no receive data. */
  }
  uint8_t b = 0U;
  if (s->tgt_wr_pos == 0U) {
    /* Step 1: the matched address byte the driver dummy-reads to discard. */
    b = (uint8_t)((uint32_t)s->tgt_own_addr << (uint32_t)k_riic_addr_shift);
  } else if (s->tgt_wr_pos <= (uint32_t)k_riic_tgt_payload_len) {
    b = s_k_riic_tgt_payload[s->tgt_wr_pos - 1U];
  }
  s->tgt_wr_pos++;
  if (s->tgt_wr_pos > (uint32_t)k_riic_tgt_payload_len) {
    s->tgt_icsr2 = (uint32_t)k_riic_icsr2_stop; /* all served: STOP, drop RDRF. */
  } else {
    s->tgt_icsr2 = (uint32_t)k_riic_icsr2_rdrf;
  }
  return (uint32_t)b;
}

RA8_INTERNAL static void internal_riic_target_icdrt(riic_state_t* s, uint8_t byte)
{
  if (s->tgt_phase != (uint8_t)k_riic_tgt_read) {
    return;
  }
  if (s->tgt_rd_len < (uint32_t)k_riic_tgt_cap) {
    s->tgt_rd[s->tgt_rd_len] = byte;
  }
  s->tgt_rd_len++;
  /* TDRE|TEND stay asserted (begin_read) so fill_tx keeps pushing to completion. */
}

RA8_INTERNAL static void internal_riic_target_icsr2_write(riic_state_t* s, uint32_t value)
{
  s->tgt_icsr2 &= value; /* condition flags are write-0-to-clear. */
  if (s->tgt_phase == (uint8_t)k_riic_tgt_write) {
    internal_riic_target_begin_read(s); /* receive() cleared STOP -> controller now reads. */
  } else if (s->tgt_phase == (uint8_t)k_riic_tgt_read) {
    internal_riic_target_complete_read(s); /* finish_tx cleared NACKF/STOP -> cycle done. */
  }
}

RA8_INTERNAL static uint64_t internal_riic_target_reg_read(riic_state_t* s, uint64_t off)
{
  if (off == (uint64_t)k_riic_off_icsr1) {
    return internal_riic_target_icsr1(s);
  }
  if (off == (uint64_t)k_riic_off_icsr2) {
    return s->tgt_icsr2;
  }
  if (off == (uint64_t)k_riic_off_iccr2) {
    return internal_riic_target_iccr2(s);
  }
  if (off == (uint64_t)k_riic_off_icdrr) {
    return internal_riic_target_icdrr(s);
  }
  return s->reg[off]; /* reflect every other register */
}

RA8_INTERNAL static uint64_t internal_riic_reg_read(riic_state_t* s, uint64_t off)
{
  if (s->tgt_armed) {
    return internal_riic_target_reg_read(s, off);
  }
  if (off == (uint64_t)k_riic_off_icsr2) {
    return s->icsr2;
  }
  if (off == (uint64_t)k_riic_off_iccr2) {
    /* BBSY tracks an open transaction; the request bits already read back 0. */
    uint32_t v = s->reg[off] & ~(uint32_t)k_riic_iccr2_bbsy;
    if (s->busy) {
      v |= (uint32_t)k_riic_iccr2_bbsy;
    }
    return v;
  }
  if (off == (uint64_t)k_riic_off_icdrr) {
    return internal_riic_icdrr_read(s);
  }
  return s->reg[off]; /* reflect every other register */
}

RA8_INTERNAL static void internal_riic_reg_write(riic_state_t* s, uint64_t off, uint32_t value)
{
  s->reg[off] = (uint8_t)(value & (uint32_t)k_riic_byte_mask);
  if (off == (uint64_t)k_riic_off_icser) {
    /* ICSER arms / disarms the own-address responder; it is the target trigger. */
    internal_riic_target_open(s, value);
    return;
  }
  if (s->tgt_armed) {
    if (off == (uint64_t)k_riic_off_icdrt) {
      internal_riic_target_icdrt(s, (uint8_t)(value & (uint32_t)k_riic_byte_mask));
    } else if (off == (uint64_t)k_riic_off_icsr2) {
      internal_riic_target_icsr2_write(s, value);
    }
    return;
  }
  if (off == (uint64_t)k_riic_off_iccr2) {
    internal_riic_iccr2_write(s, off, value);
  } else if (off == (uint64_t)k_riic_off_icdrt) {
    internal_riic_icdrt_write(s, value);
  } else if (off == (uint64_t)k_riic_off_icsr2) {
    /* Condition / fault flags are write-0-to-clear: keep only the model's
     * internal flags whose bit is still written as 1 by the driver's RMW. */
    s->icsr2 &= value;
  }
}

RA8_INTERNAL static uint64_t internal_riic_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint32_t ch  = (uint32_t)((addr - (uint64_t)k_riic_base) / (uint64_t)k_riic_stride);
  const uint64_t off = (addr - (uint64_t)k_riic_base) % (uint64_t)k_riic_stride;
  if (off >= (uint64_t)k_riic_reg_bytes) {
    return 0U; /* outside the modelled register file */
  }
  return internal_riic_reg_read(&s_riic[ch], off);
}

RA8_INTERNAL static void
internal_riic_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  (void)size;
  const uint32_t ch  = (uint32_t)((addr - (uint64_t)k_riic_base) / (uint64_t)k_riic_stride);
  const uint64_t off = (addr - (uint64_t)k_riic_base) % (uint64_t)k_riic_stride;
  if (off >= (uint64_t)k_riic_reg_bytes) {
    return; /* outside the modelled register file */
  }
  internal_riic_reg_write(&s_riic[ch], off, (uint32_t)value);
}

RA8_INTERNAL static void internal_riic_reset(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_riic_count; i++) {
    s_riic[i] = (riic_state_t){};
  }
  priv_riic_devices_reset();
}

RA8_INTERNAL static void internal_riic_report(void)
{
  priv_riic_devices_report();
  for (uint32_t ch = 0U; ch < (uint32_t)k_riic_count; ch++) {
    if (s_riic[ch].tgt_cycles > 0U) {
      (void)priv_emu_io_errf("  RIIC target   : own 0x%02X serviced %u controller write+read "
                             "cycle(s), echo=%s\n",
                             (unsigned)s_riic[ch].tgt_own_addr,
                             (unsigned)s_riic[ch].tgt_cycles,
                             s_riic[ch].tgt_echo_bad ? "MISMATCH" : "OK");
    }
  }
}

static const board_periph_block_t s_k_riic_block = {
  .base   = (uint64_t)k_riic_base,
  .span   = (uint64_t)k_riic_span,
  .order  = (uint32_t)k_block_order_i2c,
  .read   = internal_riic_read,
  .write  = internal_riic_write,
  .tick   = nullptr,
  .reset  = internal_riic_reset,
  .report = internal_riic_report,
  .name   = "RIIC+PI4IOE",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_board_periph_riic_register(void)
{
  board_periph_register_block(&s_k_riic_block);
}