ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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riic_state_t Struct Reference

One RIIC channel: register shadow + a controller transfer machine. More...

Data Fields

uint8_t reg [k_riic_reg_bytes]
 Reflect-on-read register shadow.
uint32_t icsr2
 ICSR2 flags (TDRE/TEND/RDRF/NACKF).
bool busy
 True between START and STOP.
bool addr_done
 Address phase of the (re)START done.
bool acked
 The addressed target ACKed.
bool reading
 Current transfer direction is read.
uint8_t target_7b
 7-bit address selected this transfer.
uint8_t rx [k_riic_dev_rx_max]
 Staged device response for a read.
uint32_t rx_len
 Valid bytes in rx.
uint32_t rx_pos
 Next byte index served from rx.
bool rx_primed
 The dummy first ICDRR read was consumed.
bool tgt_armed
 Own address enabled (ICSER.SARyE set).
uint8_t tgt_own_addr
 Firmware's 7-bit own address (SARLy>>1).
uint8_t tgt_phase
 riic_tgt_phase_t of the current script.
uint32_t tgt_icsr2
 Target-role ICSR2 flags (RDRF/STOP/...).
uint32_t tgt_wr_pos
 ICDRR serves consumed this write (0=addr).
uint32_t tgt_rd_len
 Bytes the firmware transmitted this read.
uint32_t tgt_cycles
 Completed write+read cycles.
bool tgt_echo_bad
 A firmware echo did not match the write.
uint8_t tgt_rd [k_riic_tgt_cap]
 Captured echo bytes (bounds-checked).

Detailed Description

One RIIC channel: register shadow + a controller transfer machine.

The model owns the registers the polling driver actually touches; the rest of the window reflects writes through reg. busy spans START..STOP (ICCR2.BBSY reports it), addr_done latches once the address byte after a (re)START has selected a device, reading records the transfer direction, target_7b records the selection, icsr2 carries the TDRE / TEND / RDRF / NACKF flags the driver waits on, and the rx staging buffer holds the bytes the addressed device produced for the current read (drained one per ICDRR read, after the FSP-style dummy first read).

Definition at line 177 of file board_periph_riic.c.

Field Documentation

◆ acked

bool riic_state_t::acked

The addressed target ACKed.

Definition at line 182 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_close_transfer(), internal_riic_icdrt_write(), and internal_riic_open_transfer().

◆ addr_done

bool riic_state_t::addr_done

Address phase of the (re)START done.

Definition at line 181 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_close_transfer(), internal_riic_icdrt_write(), and internal_riic_open_transfer().

◆ busy

bool riic_state_t::busy

True between START and STOP.

Definition at line 180 of file board_periph_riic.c.

Referenced by internal_riic_close_transfer(), internal_riic_open_transfer(), and internal_riic_reg_read().

◆ icsr2

uint32_t riic_state_t::icsr2

ICSR2 flags (TDRE/TEND/RDRF/NACKF).

Definition at line 179 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_close_transfer(), internal_riic_icdrr_read(), internal_riic_icdrt_write(), internal_riic_open_transfer(), internal_riic_reg_read(), and internal_riic_reg_write().

◆ reading

bool riic_state_t::reading

Current transfer direction is read.

Definition at line 183 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_close_transfer(), and internal_riic_open_transfer().

◆ reg

uint8_t riic_state_t::reg[k_riic_reg_bytes]

Reflect-on-read register shadow.

Definition at line 178 of file board_periph_riic.c.

Referenced by internal_riic_iccr2_write(), internal_riic_reg_read(), internal_riic_reg_write(), internal_riic_target_iccr2(), internal_riic_target_open(), and internal_riic_target_reg_read().

◆ rx

uint8_t riic_state_t::rx[k_riic_dev_rx_max]

Staged device response for a read.

Definition at line 185 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), and internal_riic_icdrr_read().

◆ rx_len

uint32_t riic_state_t::rx_len

Valid bytes in rx.

Definition at line 186 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_close_transfer(), internal_riic_icdrr_read(), and internal_riic_open_transfer().

◆ rx_pos

uint32_t riic_state_t::rx_pos

Next byte index served from rx.

Definition at line 187 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_icdrr_read(), and internal_riic_open_transfer().

◆ rx_primed

bool riic_state_t::rx_primed

The dummy first ICDRR read was consumed.

Definition at line 188 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_icdrr_read(), and internal_riic_open_transfer().

◆ target_7b

uint8_t riic_state_t::target_7b

7-bit address selected this transfer.

Definition at line 184 of file board_periph_riic.c.

Referenced by internal_riic_address_phase(), internal_riic_close_transfer(), and internal_riic_icdrt_write().

◆ tgt_armed

bool riic_state_t::tgt_armed

Own address enabled (ICSER.SARyE set).

Definition at line 190 of file board_periph_riic.c.

Referenced by internal_riic_reg_read(), internal_riic_reg_write(), and internal_riic_target_open().

◆ tgt_cycles

uint32_t riic_state_t::tgt_cycles

Completed write+read cycles.

Definition at line 196 of file board_periph_riic.c.

Referenced by internal_riic_target_complete_read().

◆ tgt_echo_bad

bool riic_state_t::tgt_echo_bad

A firmware echo did not match the write.

Definition at line 197 of file board_periph_riic.c.

Referenced by internal_riic_target_complete_read().

◆ tgt_icsr2

uint32_t riic_state_t::tgt_icsr2

Target-role ICSR2 flags (RDRF/STOP/...).

Definition at line 193 of file board_periph_riic.c.

Referenced by internal_riic_target_begin_read(), internal_riic_target_begin_write(), internal_riic_target_complete_read(), internal_riic_target_icdrr(), internal_riic_target_icsr2_write(), and internal_riic_target_reg_read().

◆ tgt_own_addr

uint8_t riic_state_t::tgt_own_addr

Firmware's 7-bit own address (SARLy>>1).

Definition at line 191 of file board_periph_riic.c.

Referenced by internal_riic_target_icdrr(), and internal_riic_target_open().

◆ tgt_phase

uint8_t riic_state_t::tgt_phase

riic_tgt_phase_t of the current script.

Definition at line 192 of file board_periph_riic.c.

Referenced by internal_riic_target_begin_read(), internal_riic_target_begin_write(), internal_riic_target_complete_read(), internal_riic_target_iccr2(), internal_riic_target_icdrr(), internal_riic_target_icdrt(), internal_riic_target_icsr1(), internal_riic_target_icsr2_write(), and internal_riic_target_open().

◆ tgt_rd

uint8_t riic_state_t::tgt_rd[k_riic_tgt_cap]

Captured echo bytes (bounds-checked).

Definition at line 198 of file board_periph_riic.c.

Referenced by internal_riic_target_complete_read(), and internal_riic_target_icdrt().

◆ tgt_rd_len

uint32_t riic_state_t::tgt_rd_len

Bytes the firmware transmitted this read.

Definition at line 195 of file board_periph_riic.c.

Referenced by internal_riic_target_begin_read(), internal_riic_target_complete_read(), and internal_riic_target_icdrt().

◆ tgt_wr_pos

uint32_t riic_state_t::tgt_wr_pos

ICDRR serves consumed this write (0=addr).

Definition at line 194 of file board_periph_riic.c.

Referenced by internal_riic_target_begin_write(), and internal_riic_target_icdrr().

The documentation for this struct was generated from the following file: