ux_dcd_ra8_usb_isr.c

Go to the documentation of this file.

 
#define UX_SOURCE_CODE
 
#include <stdint.h>
#include <string.h>
 
#include "ra8_check.h"
#include "ra8_elc_regs.h"
#include "ra8_isr.h"
#include "ra8_log.h"
#include "ra8_usb_regs.h"
#include "tx_api.h"
#include "ux_api.h"
#include "ux_dcd_ra8_usb.h"
#include "ux_dcd_ra8_usb_internal.h"
#include "ux_device_stack.h"
#include "ux_system.h"
#include "ux_utility.h"

volatile uint32_t g_isr_invocations = 0U;

volatile uint16_t g_isr_intsts0_or = 0U;

volatile uint32_t g_isr_dvst_count = 0U;

volatile uint32_t g_isr_ctrt_count = 0U;

volatile uint32_t g_isr_valid_count = 0U;

volatile uint32_t g_isr_brdy_count = 0U;

volatile uint32_t g_isr_bemp_count = 0U;

volatile uint32_t g_isr_nrdy_count = 0U;

volatile uint32_t g_isr_sofr_count = 0U;
 
volatile uint32_t g_dcd_irq_spurious_mask_count = 0U;
 
/* -------------------------------------------------------------------------- */
/* USBFS interrupt-storm guard */
/*                                                                            */
/* The USBFS controller re-asserts its NVIC line for RSME / SOFR / status- */
/* only conditions independent of INTENB0. While the host hammers a NAK'ing */
/* pipe (e.g. the MSC bulk-OUT before the storage class thread has armed the */
/* CBW receive) these event-less entries re-fire ~1e5/s and -- via Cortex-M */
/* exception tail-chaining -- consume 100% CPU, so RTOS thread mode never runs */
/* and the USBX class thread is permanently starved (GitHub issue #6). */
/*                                                                            */
/* internal_usbfs_isr counts consecutive event-less entries; once that run */
/* crosses k_ra8_usb_storm_mask_run a real storm is in progress, and */
/* priv_usbfs_irq_mask() disables the USB IRQ at the NVIC -- handing the */
/* CPU to thread mode. Recovery is the per-app 1 ms SysTick handler: it calls */
/* ux_dcd_ra8_usb_irq_reenable(), which zeroes the run counter and re-enables */
/* the line. The run counter is thus a per-millisecond rate gauge -- a genuine */
/* storm (~1e3 event-less entries/ms) trips it well within a tick; normal idle */
/* SOFR (~1/ms) never does, so the guard is behaviour-neutral for the working */
/* CDC / HID apps. SysTick is the recovery clock (not a ThreadX TX_TIMER) */
/* because it is an exception handler -- it keeps running even while the storm */
/* has thread mode, and the ThreadX timer subsystem, starved. */
/* -------------------------------------------------------------------------- */

typedef enum : uint32_t {
  k_ra8_usb_storm_mask_run = 8U, 
} ra8_usb_storm_cfg_t;
 
/* -------------------------------------------------------------------------- */
/* IRQ glue */
/* -------------------------------------------------------------------------- */

RA8_INTERNAL static void internal_isr_bump_counts(uint16_t intsts0)
{
  if ((intsts0 & (uint16_t)(1U << k_ra8_int0_bit_dvst)) != 0U) {
    g_isr_dvst_count++;
  }
  if ((intsts0 & (uint16_t)(1U << k_ra8_int0_bit_ctrt)) != 0U) {
    g_isr_ctrt_count++;
  }
  if ((intsts0 & (uint16_t)k_ra8_intsts0_mask_valid) != 0U) {
    g_isr_valid_count++;
  }
  if ((intsts0 & (uint16_t)(1U << k_ra8_int0_bit_brdy)) != 0U) {
    g_isr_brdy_count++;
  }
  if ((intsts0 & (uint16_t)(1U << k_ra8_int0_bit_bemp)) != 0U) {
    g_isr_bemp_count++;
  }
  if ((intsts0 & (uint16_t)(1U << k_ra8_int0_bit_nrdy)) != 0U) {
    g_isr_nrdy_count++;
  }
  if ((intsts0 & (uint16_t)(1U << k_ra8_int0_bit_sofr)) != 0U) {
    g_isr_sofr_count++;
  }
}

RA8_INTERNAL static void internal_usbfs_isr(void* ctx)
{
  (void)ctx;
  g_isr_invocations++;
 
  /* HUM Ch 36.2.14 "INTSTS0 : Interrupt Status Register 0", p 1986.
   * event_msk is the real-event set: INTENB0 (BRDY/NRDY/BEMP/CTRT/
   * DVST/VBSE) plus VALID. RSME / SOFR / status bits are excluded --
   * they re-assert the NVIC line on their own and are what storms. */
  const uint16_t intsts0   = ra8_usb_intsts0_snapshot(k_ra8_usb_speed_fs);
  const uint16_t event_msk = (uint16_t)((1U << k_ra8_int0_bit_brdy) | (1U << k_ra8_int0_bit_nrdy) |
                                        (1U << k_ra8_int0_bit_bemp) | (1U << k_ra8_int0_bit_ctrt) |
                                        (1U << k_ra8_int0_bit_dvst) | (1U << k_ra8_int0_bit_vbse) |
                                        (uint16_t)k_ra8_intsts0_mask_valid);
 
  g_isr_intsts0_or |= intsts0;
 
  if ((intsts0 & event_msk) == 0U) {
    g_isr_spurious_run++;
    if (g_isr_spurious_run >= (uint32_t)k_ra8_usb_storm_mask_run) {
      priv_usbfs_irq_mask();
      g_dcd_irq_spurious_mask_count++;
    }
  } else {
    g_isr_spurious_run = 0U;
  }
 
  internal_isr_bump_counts(intsts0);
  ra8_usb_dispatch(k_ra8_usb_speed_fs);
}

RA8_INTERNAL static void internal_ack_spurious(ra8_usb_speed_t speed, uint16_t intsts0)
{
  const uint16_t stuck_mask = (uint16_t)((1U << k_ra8_int0_bit_rsme) | (1U << k_ra8_int0_bit_sofr));
  if ((intsts0 & stuck_mask) != 0U) {
    (void)ra8_usb_clear_status(speed, (uint16_t)(intsts0 & stuck_mask));
  }
  /* The HS controller latches bus-change/attach/detach in INTSTS1 even
   * with INTENB1 fully masked; a held latch keeps the shared NVIC line
   * asserted with INTSTS0 clean (observed live: 440k spurious ISR
   * entries/s with INTSTS1.BCHG stuck). W0C-ack those bits here. */
  if (speed == k_ra8_usb_speed_hs) {
    volatile r_usb_regs_t* const reg = ra8_usb_hs();
    if (reg != nullptr) {
      const uint16_t int1_mask =
        (uint16_t)((1U << k_ra8_int1_bit_bchg) | (1U << k_ra8_int1_bit_dtch) |
                   (1U << k_ra8_int1_bit_attch));
      reg->INTSTS1 = (uint16_t)~int1_mask;
    }
  }
  g_dcd_irq_spurious_mask_count++;
}

RA8_INTERNAL static void internal_usbhs_isr(void* ctx)
{
  (void)ctx;
  g_isr_invocations++;
 
  /* HUM Ch 36.2.14 "INTSTS0 : Interrupt Status Register 0", p 1986.
   *
   * Snapshot INTSTS0 first and gate on event bits (8..15 + VALID in
   * bit 3). DVSQ[6:4] and VBSTS[7] are status-only and must NEVER be
   * treated as events; a snapshot of 0x0090 (DVSQ=Default + VBSTS=1)
   * means "no event pending, just status-bits asserted" and the ISR
   * must return without touching INTSTS0 to avoid an interrupt storm.
   * The event_msk below matches the bits enabled in INTENB0; RSME /
   * SOFR are intentionally excluded because the USBR resume-detect
   * signal can re-assert the NVIC line independent of INTENB0. */
  const uint16_t intsts0   = ra8_usb_intsts0_snapshot(k_ra8_usb_speed_hs);
  const uint16_t event_msk = (uint16_t)((1U << k_ra8_int0_bit_brdy) | (1U << k_ra8_int0_bit_nrdy) |
                                        (1U << k_ra8_int0_bit_bemp) | (1U << k_ra8_int0_bit_ctrt) |
                                        (1U << k_ra8_int0_bit_dvst) | (1U << k_ra8_int0_bit_vbse) |
                                        (uint16_t)k_ra8_intsts0_mask_valid);
 
  g_isr_intsts0_or |= intsts0;
 
  if ((intsts0 & event_msk) == 0U) {
    internal_ack_spurious(k_ra8_usb_speed_hs, intsts0);
    /* Same storm guard as the FS ISR: a sustained run of event-less
     * entries means a level condition the acks above cannot clear is
     * holding the NVIC line. Mask it; the per-app 1 ms SysTick handler
     * re-enables via ux_dcd_ra8_usb_irq_reenable, so real USB events
     * resume within one tick. Without this the HS line stormed at
     * ~440k entries/s and starved thread mode completely (the USBX
     * storage thread never got a single timeslice). */
    g_isr_spurious_run++;
    if (g_isr_spurious_run >= (uint32_t)k_ra8_usb_storm_mask_run) {
      priv_usbfs_irq_mask();
    }
    return;
  }
  g_isr_spurious_run = 0U;
 
  internal_isr_bump_counts(intsts0);
 
  /* ::ra8_usb_dispatch performs the W0C ack with the
   * ``INTSTS0 = ~(snapshot & ack_bits)`` pattern (HUM Ch 37.2.18 Note
   * 3 p 2082): writes 0 only to event bits that were observed set, 1
   * to all other bits (no-op under W0C). VALID is intentionally NOT
   * acked here -- the SETUP drain in ::ux_dcd_ra8_usb_irq /
   * ::ra8_usb_read_setup_unconditional clears VALID after copying
   * USBREQ/USBVAL/USBINDX/USBLENG. */
  ra8_usb_dispatch(k_ra8_usb_speed_hs);
}

ra8_elc_event_t priv_pick_event(ra8_usb_speed_t speed)
{
  return (speed == k_ra8_usb_speed_hs) ? k_ra8_elc_event_usbhs_int_resume
                                       : k_ra8_elc_event_usbfs_int;
}

ra8_isr_handler_t priv_pick_isr(ra8_usb_speed_t speed)
{
  return (speed == k_ra8_usb_speed_hs) ? internal_usbhs_isr : internal_usbfs_isr;
}

void priv_event_cb(void* ctx, ra8_usb_speed_t speed, uint16_t status_mask)
{
  (void)ctx;
  ux_dcd_ra8_usb_irq(speed, status_mask);
}