ux_dcd_ra8_usb_irq.c

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#define UX_SOURCE_CODE
 
#include <stdint.h>
#include <string.h>
 
#include "ra8_check.h"
#include "ra8_elc_regs.h"
#include "ra8_isr.h"
#include "ra8_log.h"
#include "ra8_usb_regs.h"
#include "tx_api.h"
#include "ux_api.h"
#include "ux_dcd_ra8_usb.h"
#include "ux_dcd_ra8_usb_internal.h"
#include "ux_device_stack.h"
#include "ux_system.h"
#include "ux_utility.h"

volatile uint32_t g_ctrt_irq_count = 0U;

volatile uint16_t g_intsts0_last_dispatch = 0U;

typedef enum : uint8_t {
  k_ra8_usb_dcd_intsts0_hist_n = 8U, 
} ra8_usb_dcd_intsts0_hist_t;

volatile uint32_t g_intsts0_valid_count = 0U;

volatile uint32_t g_intsts0_ctrt_count = 0U;

volatile uint16_t g_intsts0_snapshot[(uint32_t)k_ra8_usb_dcd_intsts0_hist_n] = {};

volatile uint32_t g_intsts0_snapshot_count = 0U;

volatile uint8_t g_ctsq_history[(uint32_t)k_ra8_usb_dcd_intsts0_hist_n] = {};

volatile uint16_t g_intsts0_observed_or = 0U;

volatile uint8_t g_dvsq_history[(uint32_t)k_ra8_usb_dcd_intsts0_hist_n] = {};
 
/* Auto-echo support: lets the bridge mirror data from one OUT pipe to one
 * IN pipe directly inside the ISR, without involving USBX worker threads.
 * Diagnostic counters expose what the path is doing; auto_echo_buf is
 * static and reused across BRDY events. Set ::g_dcd_auto_echo_enable to 1
 * via ::ux_dcd_ra8_usb_auto_echo_enable() to opt in. */
typedef enum : uint16_t {
  k_ux_dcd_ra8_usb_auto_echo_max = 512U, 
} ux_dcd_ra8_usb_auto_echo_cfg_t;
 
volatile uint32_t g_dcd_auto_echo_drain_ok = 0U;
 
volatile uint32_t g_dcd_auto_echo_drain_skip = 0U;
 
volatile uint32_t g_dcd_auto_echo_tx_ok = 0U;
 
volatile uint32_t g_dcd_auto_echo_tx_err = 0U;
 
volatile uint16_t g_dcd_auto_echo_last_len = 0U;
 
static uint8_t s_dcd_auto_echo_buf[k_ux_dcd_ra8_usb_auto_echo_max];

RA8_INTERNAL static void internal_irq_record_snapshot(uint16_t intsts0)
{
  const uint16_t ctrt_bit  = (uint16_t)(1U << (uint8_t)k_ra8_int0_bit_ctrt);
  const uint16_t dvst_bit  = (uint16_t)(1U << (uint8_t)k_ra8_int0_bit_dvst);
  const uint16_t valid_bit = (uint16_t)k_ra8_intsts0_mask_valid;
 
  if ((intsts0 & valid_bit) != 0U) {
    g_intsts0_valid_count++;
    /* VALID = "USB Request Reception Flag" (HUM Ch 37.2.18 p 2081);
     * fold into the canonical SETUP-arrival counter. */
    g_setup_token_observed++;
  }
  if ((intsts0 & ctrt_bit) != 0U) {
    g_intsts0_ctrt_count++;
  }
  const uint16_t interesting_mask = (uint16_t)(ctrt_bit | valid_bit | dvst_bit);
  if ((intsts0 & interesting_mask) != 0U) {
    const uint8_t slot =
      (uint8_t)(g_intsts0_snapshot_count % (uint32_t)k_ra8_usb_dcd_intsts0_hist_n);
    g_intsts0_snapshot[slot] = intsts0;
    g_ctsq_history[slot]     = (uint8_t)(intsts0 & (uint16_t)k_ra8_intsts0_mask_ctsq);
    /* DVSQ field is bits 6:4 (HUM Ch 36.2.16 p 1986). */
    g_dvsq_history[slot] =
      (uint8_t)((intsts0 & (uint16_t)k_ra8_intsts0_mask_dvsq) >> (uint8_t)k_ra8_int0_dvsq_shift);
    g_intsts0_snapshot_count++;
  }
}

RA8_INTERNAL static void internal_irq_auto_echo(uint8_t i)
{
  if (g_dcd_auto_echo_enable != 0U && i == g_dcd_auto_echo_out_pipe &&
      g_dcd.pipes[i].dir_in == 0U) {
    uint16_t        len = (uint16_t)k_ux_dcd_ra8_usb_auto_echo_max;
    const ra8_err_t qo =
      ra8_usb_queue_out(g_dcd.speed, i, s_dcd_auto_echo_buf, &len, /* rearm */ true);
    if (qo == k_ra8_ok && len > 0U) {
      g_dcd_auto_echo_drain_ok++;
      g_dcd_auto_echo_last_len = len;
      const uint16_t out_mps   = g_dcd.pipes[i].max_pkt;
      if (ra8_usb_queue_in(g_dcd.speed, g_dcd_auto_echo_in_pipe, s_dcd_auto_echo_buf, len) ==
          k_ra8_ok) {
        g_dcd_auto_echo_tx_ok++;
        /* If the data packet was exactly MPS, follow with a ZLP so the
         * host URB completes; otherwise the host waits for a short
         * packet that never arrives. */
        if (out_mps != 0U && (len % out_mps) == 0U) {
          (void)ra8_usb_queue_in(g_dcd.speed, g_dcd_auto_echo_in_pipe, s_dcd_auto_echo_buf, 0U);
        }
      } else {
        g_dcd_auto_echo_tx_err++;
      }
    } else {
      g_dcd_auto_echo_drain_skip++;
      (void)ra8_usb_rearm_out_pipe(g_dcd.speed, i);
    }
  }
}

RA8_INTERNAL static bool internal_irq_stage_next_in(UX_SLAVE_TRANSFER* tr, uint8_t i)
{
  const uint16_t total = (uint16_t)tr->ux_slave_transfer_request_requested_length;
  const uint16_t sent  = (uint16_t)tr->ux_slave_transfer_request_actual_length;
  const uint16_t mps   = g_dcd.pipes[i].max_pkt;
  const uint16_t rem   = (uint16_t)(total - sent);
  const uint16_t chunk = (rem > mps) ? mps : rem;
  if (ra8_usb_queue_in(g_dcd.speed, i, &tr->ux_slave_transfer_request_data_pointer[sent], chunk) !=
      k_ra8_ok) {
    g_diag.in_stage_fail++;
    return false;
  }
  tr->ux_slave_transfer_request_actual_length = (ULONG)((uint32_t)sent + (uint32_t)chunk);
  return true;
}

RA8_INTERNAL static bool
internal_irq_recover_in_nak(UX_SLAVE_TRANSFER* tr, uint8_t i, volatile r_usb_regs_t* reg)
{
  const uint16_t pipe_bit = (uint16_t)(1U << i);
  const uint16_t total    = (uint16_t)tr->ux_slave_transfer_request_requested_length;
  const uint16_t sent     = (uint16_t)tr->ux_slave_transfer_request_actual_length;
  const uint16_t ctr      = reg->PIPECTR[i - 1U];
  if ((ctr & (uint16_t)k_ra8_pipectr_pid_mask) != (uint16_t)k_ra8_pid_nak) {
    return false;
  }
  if ((ctr & (uint16_t)k_ra8_pipectr_inbufm) != 0U) {
    g_diag.in_rearm_nak++;
    (void)ra8_usb_rearm_out_pipe(g_dcd.speed, i);
    return true; /* BEMP follows once the re-armed bank drains */
  }
  if ((reg->BEMPSTS & pipe_bit) == 0U) {
    if (sent < total) {
      g_diag.in_restage_nak++;
      (void)internal_irq_stage_next_in(tr, i);
      return true;
    }
  }
  return false;
}

RA8_INTERNAL static void internal_irq_complete_in(UX_SLAVE_TRANSFER* tr, uint8_t i)
{
  volatile r_usb_regs_t* reg = (g_dcd.speed == k_ra8_usb_speed_hs) ? ra8_usb_hs() : ra8_usb_fs();
  if (reg == nullptr) { /* GCOVR_EXCL_BR_LINE -- speed always maps   */
    return;             /* GCOVR_EXCL_LINE -- valid speed proves reg */
  }
  const uint16_t pipe_bit = (uint16_t)(1U << i);
  const uint16_t total    = (uint16_t)tr->ux_slave_transfer_request_requested_length;
  const uint16_t sent     = (uint16_t)tr->ux_slave_transfer_request_actual_length;
 
  if (internal_irq_recover_in_nak(tr, i, reg)) {
    return;
  }
 
  /* Wait for BEMPSTS: it confirms the host has drained the bank just
   * transmitted. Acting before that would let the next BOT stage (or
   * the next data packet) be pushed over data the host has not read --
   * a race that corrupts the transport and surfaces host-side as
   * DID_ERROR. If BEMP has not fired, leave the transfer stashed and
   * retry on the next IRQ walk. HUM Ch 36.2.15 BEMPSTS (W0C). */
  if ((reg->BEMPSTS & pipe_bit) == 0U) {
    return;
  }
 
  /* Multi-packet streaming. ra8_usb_queue_in moves at most one MPS
   * bank, so a transfer longer than MPS is sent one bank per host
   * drain: push the next bank until the whole requested length is
   * out, only then post completion. ``actual_length`` is the running
   * queued-byte count seeded by internal_submit_pipe. The BEMPSTS ack
   * is transactional: it lands only after the next chunk is staged, so
   * a staging failure keeps the event pending and retries on the next
   * walk instead of stranding the transfer. */
  if (sent < total) {
    if (internal_irq_stage_next_in(tr, i)) {
      reg->BEMPSTS = (uint16_t)(~pipe_bit);
    }
    return;
  }
  reg->BEMPSTS = (uint16_t)(~pipe_bit);
 
  /* Multi-packet trailing ZLP: stage it only when USBX's force_zlp
   * flag asks for one (host expects more than the MPS-aligned
   * payload), and complete the transfer on the ZLP's own BEMP. BOT
   * data phases never set the flag (the class sends exactly the
   * host-requested length), so the CSW always follows the data. */
  if (tr->ux_slave_transfer_request_force_zlp == (ULONG)UX_TRUE) {
    tr->ux_slave_transfer_request_force_zlp = (ULONG)UX_FALSE;
    (void)ra8_usb_queue_in(g_dcd.speed, i, tr->ux_slave_transfer_request_data_pointer, 0U);
    return;
  }
  priv_trace_event((uint8_t)k_dcd_trace_kind_in, (uint8_t)k_dcd_trace_no_code, total);
  tr->ux_slave_transfer_request_completion_code = UX_SUCCESS;
  g_dcd.pipes[i].xfer                           = nullptr;
#ifndef UX_DEVICE_STANDALONE
  (void)tx_semaphore_put(&tr->ux_slave_transfer_request_semaphore);
#endif
}

RA8_INTERNAL static void internal_irq_finish_out(UX_SLAVE_TRANSFER* tr, uint8_t i, uint16_t now)
{
  (void)ra8_usb_park_out_pipe(g_dcd.speed, i);
  uint8_t  trace_op  = (uint8_t)k_dcd_trace_no_code;
  uint16_t trace_len = now;
  if (now == (uint16_t)k_dcd_trace_cbw_len) {
    const uint8_t* cdb = &tr->ux_slave_transfer_request_data_pointer[k_dcd_trace_cbw_op_off];
    trace_op           = cdb[0];
    /* For CBWs, carry CDB bytes 1..2 instead of the length so VPD
     * INQUIRY requests (EVPD flag + page code) are visible. For
     * READ(10)/WRITE(10) carry the low 16 LBA bits instead. */
    uint8_t hi = cdb[1];
    uint8_t lo = cdb[2];
    if (cdb[0] == (uint8_t)k_dcd_trace_op_read10) {
      hi = cdb[k_dcd_trace_cdb_lba_hi];
      lo = cdb[k_dcd_trace_cdb_lba_lo];
    }
    if (cdb[0] == (uint8_t)k_dcd_trace_op_write10) {
      hi = cdb[k_dcd_trace_cdb_lba_hi];
      lo = cdb[k_dcd_trace_cdb_lba_lo];
    }
    trace_len = (uint16_t)(((uint16_t)hi << (uint16_t)k_dcd_trace_byte_shift) | (uint16_t)lo);
  }
  priv_trace_event((uint8_t)k_dcd_trace_kind_out, trace_op, trace_len);
  tr->ux_slave_transfer_request_completion_code = UX_SUCCESS;
  g_dcd.pipes[i].xfer                           = nullptr;
#ifndef UX_DEVICE_STANDALONE
  (void)tx_semaphore_put(&tr->ux_slave_transfer_request_semaphore);
#endif
}

RA8_INTERNAL static void internal_irq_complete_out(UX_SLAVE_TRANSFER* tr, uint8_t i)
{
  /* Multi-packet streaming. ra8_usb_queue_out drains at most one MPS
   * bank, so an OUT transfer longer than MPS (e.g. the 512-byte SCSI
   * WRITE data phase) is received one bank per host packet:
   * accumulate into the caller buffer at the running offset, re-arm
   * the pipe for the next bank, and complete only once the whole
   * requested length is in -- or the host ends early with a short
   * (< MPS) packet, which terminates the OUT data phase (this is also
   * how a 31-byte CBW into a 64-byte request completes). */
  const uint16_t total = (uint16_t)tr->ux_slave_transfer_request_requested_length;
  const uint16_t mps   = g_dcd.pipes[i].max_pkt;
  /* Drain every OUT bank the controller currently holds (DBLB presents
   * up to two back-to-back) before re-arming, so a single BRDY services
   * as many banks as are ready. One MPS bank per ra8_usb_queue_out call;
   * stop on completion, a short packet, or when no bank is ready. */
  for (uint32_t pass = 0U; pass < (uint32_t)k_dcd_out_drain_max; pass++) {
    const uint16_t got  = (uint16_t)tr->ux_slave_transfer_request_actual_length;
    uint16_t       want = (uint16_t)(total - got);
    if (want > mps) {
      want = mps;
    }
    uint16_t        len    = want;
    const ra8_err_t qo_err = ra8_usb_queue_out(g_dcd.speed,
                                               i,
                                               &tr->ux_slave_transfer_request_data_pointer[got],
                                               &len,
                                               /* rearm */ false);
    if (qo_err != k_ra8_ok) {
      if (i == 2U) {
        g_diag.irq_walk_pipe2_no_data++;
      }
      break;
    }
    if (i == 2U) {
      g_diag.irq_walk_pipe2_complete++;
    }
    const uint16_t now                          = (uint16_t)(got + len);
    tr->ux_slave_transfer_request_actual_length = (ULONG)now;
    if (now >= total) {
      internal_irq_finish_out(tr, i, now);
      return;
    }
    if (len < mps) {
      internal_irq_finish_out(tr, i, now); /* short packet ends the phase */
      return;
    }
  }
  /* More packets expected -- re-arm for the next host OUT token(s). */
  (void)ra8_usb_rearm_out_pipe(g_dcd.speed, i);
}

RA8_INTERNAL static void internal_irq_drain_orphan_out(uint8_t i)
{
  if (g_dcd.pipes[i].dir_in != 0U) {
    return; /* IN pipe -- the host does not write to it */
  }
  if (g_dcd.pipes[i].ep_addr == 0U) {
    return; /* pipe not configured by the class layer */
  }
  if (g_dcd_auto_echo_enable != 0U) {
    if (i == g_dcd_auto_echo_out_pipe) {
      return; /* CDC auto-echo drains this pipe itself */
    }
  }
  if (g_orphan_len != 0U) {
    return; /* one-deep holding buffer already occupied */
  }
  uint16_t len = (uint16_t)k_ra8_usb_orphan_bytes;
  if (ra8_usb_queue_out(g_dcd.speed, i, g_orphan_buf, &len, /* rearm */ false) == k_ra8_ok) {
    if (len != 0U) {
      g_orphan_pipe = i;
      g_orphan_len  = len;
      priv_trace_event((uint8_t)k_dcd_trace_kind_ocap, g_orphan_buf[0], len);
      /* queue_out W0C-cleared BRDYSTS and re-armed PID=BUF; pull it
       * back to NAK so a second packet cannot land before the next
       * transfer is submitted. A full-speed bulk packet takes ~45 us
       * on the wire -- far longer than this queue_out -> park gap --
       * so the controller cannot accept one in between. */
      (void)ra8_usb_park_out_pipe(g_dcd.speed, i);
    }
  }
}

RA8_INTERNAL static void internal_irq_walk_pipe(uint8_t i)
{
  g_diag.irq_walk_total++;
  UX_SLAVE_TRANSFER* tr = g_dcd.pipes[i].xfer;
  if (tr == nullptr) {
    internal_irq_auto_echo(i);
    internal_irq_drain_orphan_out(i);
    return;
  }
  if (i == 2U) {
    g_diag.irq_walk_pipe2_seen++;
  }
  if (g_dcd.pipes[i].dir_in != 0U) {
    internal_irq_complete_in(tr, i);
    return;
  }
  internal_irq_complete_out(tr, i);
}

void ux_dcd_ra8_usb_irq(ra8_usb_speed_t speed, uint16_t intsts0)
{
  if (g_dcd.state == k_ux_dcd_ra8_usb_state_uninit) {
    return;
  }
 
  g_intsts0_last_dispatch = intsts0;
  g_intsts0_observed_or   = (uint16_t)(g_intsts0_observed_or | intsts0);
 
  internal_irq_record_snapshot(intsts0);
 
  const uint16_t ctrt_bit   = (uint16_t)(1U << (uint8_t)k_ra8_int0_bit_ctrt);
  const uint16_t dvst_bit   = (uint16_t)(1U << (uint8_t)k_ra8_int0_bit_dvst);
  const uint16_t valid_bit  = (uint16_t)k_ra8_intsts0_mask_valid;
  const bool     have_ctrt  = (intsts0 & ctrt_bit) != 0U;
  const bool     have_valid = (intsts0 & valid_bit) != 0U;
  const bool     have_dvst  = (intsts0 & dvst_bit) != 0U;
 
  /* DVST FIRST -- bus reset / suspend / resume must be processed
   * BEFORE the SETUP drain. internal_handle_dvst calls
   * ra8_usb_device_busreset_rearm on Default-state which RESETS
   * DCPCFG/DCPMAXP/DCPCTR. Draining first would have the response
   * wiped, leaving the chip NAK'ing host IN tokens. */
  if (have_dvst) {
    priv_irq_dvst_prelude(speed, intsts0);
  }
 
  /* Deferred control-OUT data stage (e.g. DFU_DNLOAD) BEFORE the CTRT block:
   * if the host's OUT data has landed in the DCP bank, drain it and run
   * chapter-9 now so the payload is consumed before the CTSQ=wrss edge in
   * priv_handle_ctrt drives the status-stage CCPL. */
  priv_handle_ctrl_out_data(speed);
 
  /* SETUP / chapter-9 path runs AFTER DVST so the busreset_rearm
   * has already restored DCP defaults. */
  if (have_ctrt) {
    g_ctrt_irq_count++;
    priv_handle_ctrt(speed, intsts0);
  }
  /* VALID-without-CTRT fallback (HUM Ch 36.2.14 p 1985): the polled
   * worker can race the controller between the VALID and CTRT edges;
   * ra8_usb_dispatch preserves VALID on W0C ack so we can still drain. */
  else if (have_valid) {
    priv_handle_ctrt(speed, intsts0);
  }
 
  /* Walk every pipe with a queued OUT transfer. ra8_usb_queue_out
   * returns k_ra8_err_no_data if BRDY hasn't fired for that pipe;
   * we just retry on the next IRQ in that case. */
  for (uint8_t i = 1U; i < (uint8_t)k_ux_dcd_ra8_usb_max_pipes; i++) {
    internal_irq_walk_pipe(i);
  }
}