ra8_ospi_regs.h File Reference

xSPI / Octo-SPI controller register layout for the Renesas RA8D2 More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_ospi_regs.h:

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Go to the source code of this file.

Data Structures
struct	r_xspi_regs_t
	xSPI per-instance register window. More...

Enumerations
enum	ra8_xspi_addr_t : uintptr_t {   k_ra8_xspi0_base_addr = 0x40268000UL ,   k_ra8_xspi1_base_addr = 0x40268400UL ,   k_ra8_dotf_base_addr = 0x40268800UL ,   k_ra8_xspi_stride = 0x400UL }
	xSPI / DOTF window base addresses on the peripheral bus. More...
enum	ra8_xspi_limits_t : uint8_t {   k_ra8_xspi_instance_count = 2U ,   k_ra8_xspi_cdbuf_slots = 4U ,   k_ra8_xspi_cdbuf_words = 16U ,   k_ra8_xspi_r4_words = 9U ,   k_ra8_xspi_ccctlcs_words = 16U ,   k_ra8_xspi_r5_words = 4U }
	Fixed xSPI limits (instance counts, slot counts). More...
enum	ra8_xspi_size_t : uint16_t { k_ra8_xspi_regs_size = 0x019CU }
enum	ra8_xspi_xfer_limits_t : uint32_t {   k_ra8_xspi_max_xfer = 4096U ,   k_ra8_xspi_page_len = 256U ,   k_ra8_xspi_sector_len = 4096U }
	Limits for direct-command flash transfers. More...
enum	ra8_xspi_lio_mode_t : uint16_t {   k_ra8_xspi_lio_1s1s1s = 0x000U ,   k_ra8_xspi_lio_1s2s2s = 0x048U ,   k_ra8_xspi_lio_1s4s4s = 0x090U ,   k_ra8_xspi_lio_1s8s8s = 0x110U ,   k_ra8_xspi_lio_8d8d8d = 0x3FFU }
	Protocol mode values written to LIOCFGCS[n].PRTMD. More...
enum	ra8_xspi_liocfgcs_pos_t : uint8_t {   k_ra8_xspi_liocfgcs_pos_prtmd = 0U ,   k_ra8_xspi_liocfgcs_pos_latemd = 10U ,   k_ra8_xspi_liocfgcs_pos_ddren = 11U }
	Bit positions in LIOCFGCS[n] (link I/O config per target). More...
enum	ra8_xspi_liocfgcs_mask_t : uint32_t { k_ra8_xspi_liocfgcs_mask_ddren = 1UL << 11U }
	Pre-shifted bit masks for LIOCFGCS[n] enable bits. More...
enum	ra8_xspi_cmcfgcs_layout_t : uint8_t {   k_ra8_xspi_cmcfgcs_word_mode = 0U ,   k_ra8_xspi_cmcfgcs_word_read_cmd = 1U ,   k_ra8_xspi_cmcfgcs_word_write_cmd = 2U ,   k_ra8_xspi_cmcfgcs_word_addr = 3U ,   k_ra8_xspi_cmcfgcs_words_per_slot = 4U }
	Word indices inside one CMCFGCS[n] slot (4 u32 each). More...
enum	ra8_xspi_cmcfgcs_pos_t : uint8_t {   k_ra8_xspi_cmcfgcs_pos_cmd = 16U ,   k_ra8_xspi_cmcfgcs_pos_addr_size = 0U }
	Bit positions inside the CMCFGCS read-cmd word. More...
enum	ra8_xspi_wrapcfg_pos_t : uint8_t {   k_ra8_xspi_wrapcfg_pos_dssft_cs0 = 8U ,   k_ra8_xspi_wrapcfg_pos_dssft_cs1 = 24U }
	Bit positions inside WRAPCFG (DQS shift per target). More...
enum	ra8_xspi_wrapcfg_mask_t : uint32_t { k_ra8_xspi_wrapcfg_dssft_mask = 0x1FUL }
enum	ra8_xspi_calib_t : uint8_t {   k_ra8_xspi_ccctl0_pos_caen = 0U ,   k_ra8_xspi_ccctlcs_words_per_cs = 8U }
	Reserved-bit positions in CCCTLCS[n].CCCTL0 (calibration). More...
enum	ra8_xspi_calib_mask_t : uint32_t { k_ra8_xspi_ccctl0_mask_caen = 1UL << 0U }
enum	ra8_xspi_cdbuf_slot_word_t : uint8_t {   k_ra8_xspi_cdbuf_word_cdt = 0U ,   k_ra8_xspi_cdbuf_word_cda = 1U ,   k_ra8_xspi_cdbuf_word_cdd0 = 2U ,   k_ra8_xspi_cdbuf_word_cdd1 = 3U ,   k_ra8_xspi_cdbuf_words_per_slot = 4U }
	Per-slot word indices inside one CDBUF slot (4 u32 each). More...
enum	ra8_xspi_cdt_pos_t : uint8_t {   k_ra8_xspi_cdt_pos_cmdsize = 0U ,   k_ra8_xspi_cdt_pos_addsize = 2U ,   k_ra8_xspi_cdt_pos_datasize = 5U ,   k_ra8_xspi_cdt_pos_late = 9U ,   k_ra8_xspi_cdt_pos_trtype = 15U ,   k_ra8_xspi_cdt_pos_cmd = 16U }
	Bit positions inside the CDBUF[n].CDT (Command Type) word. More...
enum	ra8_xspi_cdt_addsize_t : uint8_t {   k_ra8_xspi_cdt_addsize_0 = 0U ,   k_ra8_xspi_cdt_addsize_3 = 3U ,   k_ra8_xspi_cdt_addsize_4 = 4U }
	Encoded address-byte counts for CDT.ADDSIZE. More...
enum	ra8_xspi_cdt_field_mask_t : uint32_t {   k_ra8_xspi_cdt_mask_cmdsize = 0x3UL ,   k_ra8_xspi_cdt_mask_addsize = 0x7UL ,   k_ra8_xspi_cdt_mask_datasize = 0xFUL ,   k_ra8_xspi_cdt_mask_trtype = 0x1UL ,   k_ra8_xspi_cdt_mask_cmd = 0xFFFFUL }
	Width-limited masks for the sub-fields packed into CDT. More...
enum	ra8_xspi_cdt_cmdsize_t : uint8_t {   k_ra8_xspi_cdt_cmdsize_0 = 0U ,   k_ra8_xspi_cdt_cmdsize_1 = 1U ,   k_ra8_xspi_cdt_cmdsize_2 = 2U }
	Encoded command-byte counts for CDT.CMDSIZE. More...
enum	ra8_xspi_cdt_trtype_t : uint8_t {   k_ra8_xspi_cdt_trtype_read = 0U ,   k_ra8_xspi_cdt_trtype_write = 1U }
	CDT.TRTYPE direction selector. More...
enum	ra8_xspi_bmctl0_t : uint32_t {   k_ra8_xspi_bmctl0_disabled = 0x00UL ,   k_ra8_xspi_bmctl0_read_only = 0x55UL ,   k_ra8_xspi_bmctl0_write_only = 0xAAUL ,   k_ra8_xspi_bmctl0_read_write = 0xFFUL }
	Pre-shifted masks for BMCTL0 (system-bus access enable). More...
enum	ra8_xspi_bmctl1_t : uint32_t {   k_ra8_xspi_bmctl1_pbufclr_mask = 0x03UL << 10U ,   k_ra8_xspi_bmctl1_mwrpush_mask = 0x03UL << 8U }
	Pre-shifted control masks for BMCTL1 (write-only). More...
enum	ra8_xspi_cmctlch_t : uint32_t {   k_ra8_xspi_cmctlch_xipen_pos = 16U ,   k_ra8_xspi_cmctlch_xipen_mask = 1UL << 16U ,   k_ra8_xspi_cmctlch_xipencode_pos = 0U ,   k_ra8_xspi_cmctlch_xipexcode_pos = 8U }
	Pre-shifted bit masks for CMCTLCH[n] (XiP control). More...
enum	ra8_xspi_cdctl0_bit_t : uint8_t {   k_ra8_xspi_cdctl0_bit_trreq = 0U ,   k_ra8_xspi_cdctl0_bit_cssel = 3U }
	Bit positions in CDCTL0 (command manual control 0). More...
enum	ra8_xspi_cdctl0_mask_t : uint32_t {   k_ra8_xspi_cdctl0_mask_trreq = 1UL << 0U ,   k_ra8_xspi_cdctl0_mask_cssel = 1UL << 3U }
	Pre-shifted masks for CDCTL0 control bits. More...
enum	ra8_xspi_lioctl_mask_t : uint32_t {   k_ra8_xspi_lioctl_mask_wpcs = 1UL << 0U ,   k_ra8_xspi_lioctl_mask_rstcs = 1UL << 16U }
	Pre-shifted masks for LIOCTL (link I/O control: WP / RST drive). More...
enum	ra8_xspi_ints_bit_t : uint8_t {   k_ra8_xspi_ints_bit_cmdcmp = 0U ,   k_ra8_xspi_ints_bit_patcmp = 1U ,   k_ra8_xspi_ints_bit_inicmp = 2U }
	Bit positions in the INTS interrupt-status register. More...
enum	ra8_xspi_ints_mask_t : uint32_t {   k_ra8_xspi_ints_mask_cmdcmp = 1UL << 0U ,   k_ra8_xspi_ints_mask_patcmp = 1UL << 1U ,   k_ra8_xspi_ints_mask_inicmp = 1UL << 2U ,   k_ra8_xspi_ints_mask_all = 0xFFFFFFFFUL }
	Pre-shifted masks for the INTS and INTC registers. More...
enum	ra8_xspi_inte_mask_t : uint32_t { k_ra8_xspi_inte_mask_cmdcmp = 1UL << 0U }
	Pre-shifted masks for the INTE interrupt-enable register. More...
enum	ra8_xspi_comstt_bit_t : uint8_t {   k_ra8_xspi_comstt_bit_memacc_ch0 = 0U ,   k_ra8_xspi_comstt_bit_memacc_ch1 = 1U ,   k_ra8_xspi_comstt_bit_pbufne_ch0 = 4U ,   k_ra8_xspi_comstt_bit_pbufne_ch1 = 5U ,   k_ra8_xspi_comstt_bit_ecs_cs0 = 16U ,   k_ra8_xspi_comstt_bit_int_cs0 = 17U ,   k_ra8_xspi_comstt_bit_ecs_cs1 = 20U ,   k_ra8_xspi_comstt_bit_int_cs1 = 21U }
	Bit positions in the COMSTT (common status) register. More...

Functions
static volatile r_xspi_regs_t *	ra8_xspi (uint8_t instance)
	Get pointer to xSPI instance N (0..1).

Detailed Description

xSPI / Octo-SPI controller register layout for the Renesas RA8D2

The RA8D2 xSPI controller drives the on-board 64 MiB Octo-SPI NOR flash on the EK-RA8D2 and supports OPI / Octa-DDR / HyperBus via two instances:

• XSPI0 at 0x40268000
• XSPI1 at 0x40268400

The DOTF (Decryption On The Fly) block at 0x40268800 sits immediately after them for encrypted XiP execution and is addressed separately.

Layout source

This header mirrors R_XSPI0_Type in the Renesas FSP CMSIS header R7KA8D2KF_core0.h (lines 26943..27312), which itself is generated from the RA8D2 Hardware User's Manual chapter 44 "Octal Serial Peripheral Interface (OSPI)" (p 2986..3047). Total struct size is 412 bytes (0x19C) per instance. Sub-blocks CMCFGCS[2] (0x10 each), CDBUF[4] (0x10 each), and CCCTLCS[2] (0x20 each) are flattened here to uint32_t arrays so the driver can index individual 32-bit words without pulling in FSP's bit-field sub-structures.

Register map (per instance)

Offset	Name	Width	Purpose
0x000	WRAPCFG	32	Wrapper configuration (CK/DS shift)
0x004	COMCFG	32	Channel arbitration + INT output enable
0x008	BMCFGCH[2]	32 x 2	Bridge map config per channel
0x010	CMCFGCS[2]	4 x 32 x 2	Command map configuration per target
0x030	_r0	32 x 8	Reserved
0x050	LIOCFGCS[2]	32 x 2	Link I/O config (protocol / latency)
0x058	ABMCFG	32	AXI bridge map configuration
0x05C	_r1	32	Reserved
0x060	BMCTL0	32	Bridge map control 0
0x064	BMCTL1	32	Bridge map control 1 (write-only push)
0x068	CMCTLCH[2]	32 x 2	Command map control (XiP)
0x070	CDCTL0	32	Command manual control 0 (TRREQ / CSSEL)
0x074	CDCTL1	32	Command manual control 1
0x078	CDCTL2	32	Command manual control 2
0x07C	_r2	32	Reserved
0x080	CDBUF[16]	32 x 16	Command manual buffer (4 slots x 4 words)
0x0C0	_r3	32 x 16	Reserved
0x100	LPCTL0	32	Link pattern control 0
0x104	LPCTL1	32	Link pattern control 1
0x108	LIOCTL	32	Link I/O control (WP/RST drive)
0x10C	_r4	32 x 9	Reserved
0x130	CCCTLCS[16]	32 x 16	Calibration config per target (2 x 8)
0x170	_r5	32 x 4	Reserved
0x180	VERSTT	32	Version (read-only)
0x184	COMSTT	32	Common status (MEMACC / PBUFNE / ECS)
0x188	CASTTCS[2]	32 x 2	Calibration status per target
0x190	INTS	32	Interrupt status (CMDCMP in bit 0)
0x194	INTC	32	Interrupt clear (write-1-to-clear)
0x198	INTE	32	Interrupt enable

Manual-command flow

Driver code issues a direct flash command by filling one CDBUF slot (opcode into CDBUF[N*4+0], address into CDBUF[N*4+1], write data into CDBUF[N*4+2..3]), then setting CDCTL0.TRREQ to kick the transfer and polling INTS.CMDCMP for completion. INTC.CMDCMPC clears the pending status.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_ospi_regs.h.

Enumeration Type Documentation

ra8_xspi_addr_t

enum ra8_xspi_addr_t : uintptr_t

xSPI / DOTF window base addresses on the peripheral bus.

Enumerator
k_ra8_xspi0_base_addr	XSPI0 register window.
k_ra8_xspi1_base_addr	XSPI1 register window.
k_ra8_dotf_base_addr	DOTF (decryption-on-the-fly).
k_ra8_xspi_stride	Spacing between XSPIn windows.

Definition at line 91 of file ra8_ospi_regs.h.

ra8_xspi_bmctl0_t

enum ra8_xspi_bmctl0_t : uint32_t

Pre-shifted masks for BMCTL0 (system-bus access enable).

BMCTL0 enables AHB read/write traffic from each system-bus channel to each target. Two bits per (channel, target) pair: 01 = read-only, 10 = write-only, 11 = read/write. FSP names the conventional patterns READ_ONLY=0x55 / READ_WRITE=0xFF.

Enumerator
k_ra8_xspi_bmctl0_disabled	All AHB access disabled.
k_ra8_xspi_bmctl0_read_only	01 per pair: read-only.
k_ra8_xspi_bmctl0_write_only	10 per pair: write-only.
k_ra8_xspi_bmctl0_read_write	11 per pair: read/write.

Definition at line 404 of file ra8_ospi_regs.h.

ra8_xspi_bmctl1_t

enum ra8_xspi_bmctl1_t : uint32_t

Pre-shifted control masks for BMCTL1 (write-only).

Enumerator
k_ra8_xspi_bmctl1_pbufclr_mask	Clear prefetch ch0+ch1.
k_ra8_xspi_bmctl1_mwrpush_mask	Push combine ch0+ch1.

Definition at line 415 of file ra8_ospi_regs.h.

ra8_xspi_calib_mask_t

enum ra8_xspi_calib_mask_t : uint32_t

Enumerator
k_ra8_xspi_ccctl0_mask_caen	CAEN enable mask.

Definition at line 304 of file ra8_ospi_regs.h.

ra8_xspi_calib_t

enum ra8_xspi_calib_t : uint8_t

Reserved-bit positions in CCCTLCS[n].CCCTL0 (calibration).

The CCCTLCS bank holds the auto-calibration descriptor per target. For project use we only need the enable bit; CCCTL0_b.CAEN lives at bit 0 (HUM Ch 44 p 2986). The full 8-word descriptor is filled in by ra8_xspi_calibrate_dqs() from FSP-style defaults.

Enumerator
k_ra8_xspi_ccctl0_pos_caen	CAEN[0] auto-calibration enable.
k_ra8_xspi_ccctlcs_words_per_cs	8 u32 per chip-select bank.

Definition at line 299 of file ra8_ospi_regs.h.

ra8_xspi_cdbuf_slot_word_t

enum ra8_xspi_cdbuf_slot_word_t : uint8_t

Per-slot word indices inside one CDBUF slot (4 u32 each).

Each manual-command slot in CDBUF is 16 bytes laid out as four 32-bit words: CDT (type / opcode), CDA (address), CDD0 (data0..3), CDD1 (data4..7). FSP names these CDBUF[n].CDT/CDA/CDD0/CDD1. The flat CDBUF[16] array in r_xspi_regs_t indexes these as slot * 4 + word.

Enumerator
k_ra8_xspi_cdbuf_word_cdt	+0x00 CDT – cmd/size/type word.
k_ra8_xspi_cdbuf_word_cda	+0x04 CDA – address word.
k_ra8_xspi_cdbuf_word_cdd0	+0x08 CDD0 – data bytes 0..3.
k_ra8_xspi_cdbuf_word_cdd1	+0x0C CDD1 – data bytes 4..7.
k_ra8_xspi_cdbuf_words_per_slot	Each CDBUF slot is 4 u32 wide.

Definition at line 319 of file ra8_ospi_regs.h.

ra8_xspi_cdctl0_bit_t

enum ra8_xspi_cdctl0_bit_t : uint8_t

Bit positions in CDCTL0 (command manual control 0).

Writing TRREQ to 1 kicks a manual-command transfer out of CDBUF. The controller self-clears the bit once the transfer finishes. CSSEL selects which chip-select (target 0 / target 1) the command targets.

Enumerator
k_ra8_xspi_cdctl0_bit_trreq	Transaction request.
k_ra8_xspi_cdctl0_bit_cssel	Chip-select select (0 = CS0).

Definition at line 441 of file ra8_ospi_regs.h.

ra8_xspi_cdctl0_mask_t

enum ra8_xspi_cdctl0_mask_t : uint32_t

Pre-shifted masks for CDCTL0 control bits.

Enumerator
k_ra8_xspi_cdctl0_mask_trreq	TRREQ (kick off xfer).
k_ra8_xspi_cdctl0_mask_cssel	CSSEL (target select).

Definition at line 450 of file ra8_ospi_regs.h.

ra8_xspi_cdt_addsize_t

enum ra8_xspi_cdt_addsize_t : uint8_t

Encoded address-byte counts for CDT.ADDSIZE.

Enumerator
k_ra8_xspi_cdt_addsize_0	No address phase (e.g. WREN, RDID).
k_ra8_xspi_cdt_addsize_3	3-byte address (24-bit JEDEC).
k_ra8_xspi_cdt_addsize_4	4-byte address (32-bit JEDEC).

Definition at line 350 of file ra8_ospi_regs.h.

ra8_xspi_cdt_cmdsize_t

enum ra8_xspi_cdt_cmdsize_t : uint8_t

Encoded command-byte counts for CDT.CMDSIZE.

Enumerator
k_ra8_xspi_cdt_cmdsize_0	No command byte (rare).
k_ra8_xspi_cdt_cmdsize_1	1-byte command (standard SPI).
k_ra8_xspi_cdt_cmdsize_2	2-byte command (DDR / OPI).

Definition at line 379 of file ra8_ospi_regs.h.

ra8_xspi_cdt_field_mask_t

enum ra8_xspi_cdt_field_mask_t : uint32_t

Width-limited masks for the sub-fields packed into CDT.

Each mask covers exactly the bit-count of its target field per the FSP CMSIS bit-field layout (HUM Ch 44 p 2986): CMDSIZE is 2 bits, ADDSIZE is 3 bits, DATASIZE is 4 bits, TRTYPE is 1 bit. The masks exist so the CDT-encoder can clamp caller-provided values without relying on raw hexadecimal magic numbers.

Enumerator
k_ra8_xspi_cdt_mask_cmdsize	CMDSIZE field is 2 bits.
k_ra8_xspi_cdt_mask_addsize	ADDSIZE field is 3 bits.
k_ra8_xspi_cdt_mask_datasize	DATASIZE field is 4 bits.
k_ra8_xspi_cdt_mask_trtype	TRTYPE field is 1 bit.
k_ra8_xspi_cdt_mask_cmd	CMD[31..16] is a 16-bit field.

Definition at line 367 of file ra8_ospi_regs.h.

ra8_xspi_cdt_pos_t

enum ra8_xspi_cdt_pos_t : uint8_t

Bit positions inside the CDBUF[n].CDT (Command Type) word.

Mirrors FSP R_XSPI0_CDBUF_CDT_* positions per HUM Ch 44 p 2986. The Command Manual engine reads CMDSIZE/ADDSIZE/DATASIZE/LATE/TRTYPE out of CDT to drive the SPI bus phases; the actual JEDEC opcode goes in the high half (CMD at bits [31..16]).

Enumerator
k_ra8_xspi_cdt_pos_cmdsize	CMDSIZE[1..0] command bytes.
k_ra8_xspi_cdt_pos_addsize	ADDSIZE[4..2] address bytes.
k_ra8_xspi_cdt_pos_datasize	DATASIZE[8..5] data bytes.
k_ra8_xspi_cdt_pos_late	LATE[13..9] latency cycles.
k_ra8_xspi_cdt_pos_trtype	TRTYPE[15] 0=read 1=write.
k_ra8_xspi_cdt_pos_cmd	CMD[31..16] JEDEC opcode.

Definition at line 337 of file ra8_ospi_regs.h.

ra8_xspi_cdt_trtype_t

enum ra8_xspi_cdt_trtype_t : uint8_t

CDT.TRTYPE direction selector.

Enumerator
k_ra8_xspi_cdt_trtype_read	Read transaction (host samples).
k_ra8_xspi_cdt_trtype_write	Write transaction (host drives).

Definition at line 389 of file ra8_ospi_regs.h.

ra8_xspi_cmcfgcs_layout_t

enum ra8_xspi_cmcfgcs_layout_t : uint8_t

Word indices inside one CMCFGCS[n] slot (4 u32 each).

CMCFGCS is a 2-target x 4-word block in r_xspi_regs_t::CMCFGCS. Slot n lives at CMCFGCS[n * 4 + word]. The layout mirrors FSP R_XSPI0_CMCFGCS_b (HUM Ch 44 p 2986): word 0 holds the mapping mode, word 1 the read command + dummy cycles, word 2 the write command, word 3 the address-byte width.

Enumerator
k_ra8_xspi_cmcfgcs_word_mode	+0x00 mapping mode word.
k_ra8_xspi_cmcfgcs_word_read_cmd	+0x04 read-cmd + dummy cycles.
k_ra8_xspi_cmcfgcs_word_write_cmd	+0x08 write-cmd + dummy.
k_ra8_xspi_cmcfgcs_word_addr	+0x0C address-byte width.
k_ra8_xspi_cmcfgcs_words_per_slot	Each slot is 4 u32 wide.

Definition at line 253 of file ra8_ospi_regs.h.

ra8_xspi_cmcfgcs_pos_t

enum ra8_xspi_cmcfgcs_pos_t : uint8_t

Bit positions inside the CMCFGCS read-cmd word.

Enumerator
k_ra8_xspi_cmcfgcs_pos_cmd	CMD[31..16] read opcode.
k_ra8_xspi_cmcfgcs_pos_addr_size	ADDSIZE[2..0] addr bytes.

Definition at line 265 of file ra8_ospi_regs.h.

ra8_xspi_cmctlch_t

enum ra8_xspi_cmctlch_t : uint32_t

Pre-shifted bit masks for CMCTLCH[n] (XiP control).

Enumerator
k_ra8_xspi_cmctlch_xipen_pos	XIPEN bit position.
k_ra8_xspi_cmctlch_xipen_mask	XIPEN[16] enable.
k_ra8_xspi_cmctlch_xipencode_pos	XIPENCODE[7..0] enter.
k_ra8_xspi_cmctlch_xipexcode_pos	XIPEXCODE[15..8] exit.

Definition at line 424 of file ra8_ospi_regs.h.

ra8_xspi_comstt_bit_t

enum ra8_xspi_comstt_bit_t : uint8_t

Bit positions in the COMSTT (common status) register.

Unlike the earlier scaffold this register no longer reports TRBUSY / done – instead it reports per-channel memory access activity, prefetch buffer state and per-target ECS/INT/RSTO monitors. Command completion now lives on INTS.CMDCMP.

Enumerator
k_ra8_xspi_comstt_bit_memacc_ch0	Mem access ongoing for ch0.
k_ra8_xspi_comstt_bit_memacc_ch1	Mem access ongoing for ch1.
k_ra8_xspi_comstt_bit_pbufne_ch0	Prefetch buf not-empty ch0.
k_ra8_xspi_comstt_bit_pbufne_ch1	Prefetch buf not-empty ch1.
k_ra8_xspi_comstt_bit_ecs_cs0	ECS monitor for target 0.
k_ra8_xspi_comstt_bit_int_cs0	INT monitor for target 0.
k_ra8_xspi_comstt_bit_ecs_cs1	ECS monitor for target 1.
k_ra8_xspi_comstt_bit_int_cs1	INT monitor for target 1.

Definition at line 521 of file ra8_ospi_regs.h.

ra8_xspi_inte_mask_t

enum ra8_xspi_inte_mask_t : uint32_t

Pre-shifted masks for the INTE interrupt-enable register.

Enumerator
k_ra8_xspi_inte_mask_cmdcmp	CMDCMPE – enable CMDCMP IRQ.

Definition at line 507 of file ra8_ospi_regs.h.

ra8_xspi_ints_bit_t

enum ra8_xspi_ints_bit_t : uint8_t

Bit positions in the INTS interrupt-status register.

Enumerator
k_ra8_xspi_ints_bit_cmdcmp	Command-complete flag.
k_ra8_xspi_ints_bit_patcmp	Pattern-complete flag.
k_ra8_xspi_ints_bit_inicmp	Initial-sequence-complete flag.

Definition at line 481 of file ra8_ospi_regs.h.

ra8_xspi_ints_mask_t

enum ra8_xspi_ints_mask_t : uint32_t

Pre-shifted masks for the INTS and INTC registers.

The same bit positions drive INTS (read flag), INTC (W1C clear) and INTE (enable) registers, so one mask enum covers all three.

Enumerator
k_ra8_xspi_ints_mask_cmdcmp	CMDCMP – command complete.
k_ra8_xspi_ints_mask_patcmp	PATCMP – pattern complete.
k_ra8_xspi_ints_mask_inicmp	INICMP – initial seq done.
k_ra8_xspi_ints_mask_all	Clear every pending flag.

Definition at line 496 of file ra8_ospi_regs.h.

ra8_xspi_limits_t

enum ra8_xspi_limits_t : uint8_t

Fixed xSPI limits (instance counts, slot counts).

Enumerator
k_ra8_xspi_instance_count	XSPI0 and XSPI1.
k_ra8_xspi_cdbuf_slots	CDBUF has 4 x 16-byte manual slots.
k_ra8_xspi_cdbuf_words	Flattened CDBUF view (4 slots x 4 u32).
k_ra8_xspi_r4_words	Reserved 36-byte gap at +0x10C.
k_ra8_xspi_ccctlcs_words	CCCTLCS is 2 targets x 8 u32 each.
k_ra8_xspi_r5_words	Reserved 16-byte gap at +0x170.

Definition at line 102 of file ra8_ospi_regs.h.

ra8_xspi_lio_mode_t

enum ra8_xspi_lio_mode_t : uint16_t

Protocol mode values written to LIOCFGCS[n].PRTMD.

PRTMD is a 10-bit field per FSP R_XSPI0_LIOCFGCS_b.PRTMD (HUM Ch 44 "Octal Serial Peripheral Interface (OSPI)" p 2986), so this enum is widened to uint16_t to fit the full 10-bit range required by 8D/4S protocol encodings (e.g. SPI_FLASH_PROTOCOL_8D_8D_8D = 0x3FF). The convenience names preserved here are the simple-driver bring-up shortcuts; raw 10-bit FSP-style protocol words can also be cast in directly.

Enumerator
k_ra8_xspi_lio_1s1s1s	1S-1S-1S extended SPI.
k_ra8_xspi_lio_1s2s2s	1S-2S-2S dual IO.
k_ra8_xspi_lio_1s4s4s	1S-4S-4S quad IO.
k_ra8_xspi_lio_1s8s8s	1S-8S-8S octal IO.
k_ra8_xspi_lio_8d8d8d	8D-8D-8D octal DDR (OPI).

Definition at line 211 of file ra8_ospi_regs.h.

ra8_xspi_liocfgcs_mask_t

enum ra8_xspi_liocfgcs_mask_t : uint32_t

Pre-shifted bit masks for LIOCFGCS[n] enable bits.

Enumerator
k_ra8_xspi_liocfgcs_mask_ddren	DDR / DTR enable bit.

Definition at line 238 of file ra8_ospi_regs.h.

ra8_xspi_liocfgcs_pos_t

enum ra8_xspi_liocfgcs_pos_t : uint8_t

Bit positions in LIOCFGCS[n] (link I/O config per target).

Mirrors FSP R_XSPI0_LIOCFGCS_b field positions so the driver encodes protocol + latency bits at the correct offsets when programming a link-IO mode.

Enumerator
k_ra8_xspi_liocfgcs_pos_prtmd	PRTMD[9..0] protocol mode.
k_ra8_xspi_liocfgcs_pos_latemd	LATEMD[10] latency mode.
k_ra8_xspi_liocfgcs_pos_ddren	DDREN[11] DDR enable.

Definition at line 228 of file ra8_ospi_regs.h.

ra8_xspi_lioctl_mask_t

enum ra8_xspi_lioctl_mask_t : uint32_t

Pre-shifted masks for LIOCTL (link I/O control: WP / RST drive).

LIOCTL drives the per-instance write-protect and reset output pins that fan out to the selected chip-select's flash. Mirrors FSP CMSIS R_XSPI0_LIOCTL_* (HUM Ch 44 p 2986): WPCS at bit 0 drives the active-low write-protect strap, RSTCS at bit 16 drives the active-low hardware-reset strap. Both reset to 1 (deasserted). The vendor EK-RA8D2 bring-up (ospi_b_ep.c ospi_b_init and ospi_flash_issi_is25lx512.c reset_ospi_device) pulses RSTCS low-then-high AFTER the controller protocol/timing config to return the IS25LX512M to a known SPI protocol state before the first JEDEC command; without it a device left in OPI/DOPI by a prior loader never answers a 1S RDID and the bus floats to 0x00FFFFFF.

Enumerator
k_ra8_xspi_lioctl_mask_wpcs	WPCS – write-protect drive.
k_ra8_xspi_lioctl_mask_rstcs	RSTCS – hardware-reset drive.

Definition at line 472 of file ra8_ospi_regs.h.

ra8_xspi_size_t

enum ra8_xspi_size_t : uint16_t

Enumerator
k_ra8_xspi_regs_size	FSP R_XSPI0_Type size (412 bytes).

Definition at line 111 of file ra8_ospi_regs.h.

ra8_xspi_wrapcfg_mask_t

enum ra8_xspi_wrapcfg_mask_t : uint32_t

Enumerator
k_ra8_xspi_wrapcfg_dssft_mask	5-bit DQS shift code mask.

Definition at line 285 of file ra8_ospi_regs.h.

ra8_xspi_wrapcfg_pos_t

enum ra8_xspi_wrapcfg_pos_t : uint8_t

Bit positions inside WRAPCFG (DQS shift per target).

DSSFTCS0[12..8] and DSSFTCS1[28..24] are 5-bit calibration codes (HUM Ch 44 p 2986). FSP's R_OSPI_B_AutoCalibrate sweeps these to find the optimum sample window; this driver exposes the shift slots directly so callers can write a known-good offset.

Enumerator
k_ra8_xspi_wrapcfg_pos_dssft_cs0	DSSFTCS0[12..8].
k_ra8_xspi_wrapcfg_pos_dssft_cs1	DSSFTCS1[28..24].

Definition at line 280 of file ra8_ospi_regs.h.

ra8_xspi_xfer_limits_t

enum ra8_xspi_xfer_limits_t : uint32_t

Limits for direct-command flash transfers.

Enumerator
k_ra8_xspi_max_xfer	Maximum bytes per flash read/program call.
k_ra8_xspi_page_len	Page size of standard NOR flash parts.
k_ra8_xspi_sector_len	Sector size for opcode 0x20 / 0x21.

Definition at line 119 of file ra8_ospi_regs.h.

Function Documentation

ra8_xspi()

volatile r_xspi_regs_t * ra8_xspi ( uint8_t instance )

inlinestatic

Get pointer to xSPI instance N (0..1).

Parameters

[in]

instance

xSPI instance index (0 or 1).

Returns

Pointer to the register window, or nullptr if instance >= k_ra8_xspi_instance_count.

Note

Thread-safe; returns a constant address per instance.

Since

0.1.0

Definition at line 189 of file ra8_ospi_regs.h.

References k_ra8_xspi0_base_addr, k_ra8_xspi_instance_count, and k_ra8_xspi_stride.

Referenced by ra8_xspi_calibrate_dqs(), ra8_xspi_clear_status(), ra8_xspi_deinit(), ra8_xspi_direct_command(), ra8_xspi_dispatch(), ra8_xspi_flash_erase_sector(), ra8_xspi_flash_program(), ra8_xspi_flash_read(), ra8_xspi_flash_read_id(), ra8_xspi_flash_read_status(), ra8_xspi_get_status(), ra8_xspi_init(), ra8_xspi_resume(), ra8_xspi_set_dtr_mode(), ra8_xspi_set_xip_mode(), ra8_xspi_software_reset(), ra8_xspi_suspend(), ra8_xspi_xip_enter(), and ra8_xspi_xip_exit().