ra8_ospi_regs.h

Go to the documentation of this file.

 
#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_xspi0_base_addr = 0x40268000UL, 
  k_ra8_xspi1_base_addr = 0x40268400UL, 
  k_ra8_dotf_base_addr  = 0x40268800UL, 
  k_ra8_xspi_stride     = 0x400UL,      
} ra8_xspi_addr_t;

typedef enum : uint8_t {
  k_ra8_xspi_instance_count = 2U,  
  k_ra8_xspi_cdbuf_slots    = 4U,  
  k_ra8_xspi_cdbuf_words    = 16U, 
  k_ra8_xspi_r4_words       = 9U,  
  k_ra8_xspi_ccctlcs_words  = 16U, 
  k_ra8_xspi_r5_words       = 4U,  
} ra8_xspi_limits_t;
 
typedef enum : uint16_t {
  k_ra8_xspi_regs_size = 0x019CU, 
} ra8_xspi_size_t;

typedef enum : uint32_t {
  k_ra8_xspi_max_xfer   = 4096U, 
  k_ra8_xspi_page_len   = 256U,  
  k_ra8_xspi_sector_len = 4096U, 
} ra8_xspi_xfer_limits_t;

typedef struct {
  volatile uint32_t WRAPCFG;                           
  volatile uint32_t COMCFG;                            
  volatile uint32_t BMCFGCH[2];                        
  volatile uint32_t CMCFGCS[8];                        
  volatile uint32_t _r0[8];                            
  volatile uint32_t LIOCFGCS[2];                       
  volatile uint32_t ABMCFG;                            
  volatile uint32_t _r1;                               
  volatile uint32_t BMCTL0;                            
  volatile uint32_t BMCTL1;                            
  volatile uint32_t CMCTLCH[2];                        
  volatile uint32_t CDCTL0;                            
  volatile uint32_t CDCTL1;                            
  volatile uint32_t CDCTL2;                            
  volatile uint32_t _r2;                               
  volatile uint32_t CDBUF[16];                         
  volatile uint32_t _r3[16];                           
  volatile uint32_t LPCTL0;                            
  volatile uint32_t LPCTL1;                            
  volatile uint32_t LIOCTL;                            
  volatile uint32_t _r4[k_ra8_xspi_r4_words];          
  volatile uint32_t CCCTLCS[k_ra8_xspi_ccctlcs_words]; 
  volatile uint32_t _r5[k_ra8_xspi_r5_words];          
  volatile uint32_t VERSTT;                            
  volatile uint32_t COMSTT;                            
  volatile uint32_t CASTTCS[2];                        
  volatile uint32_t INTS;                              
  volatile uint32_t INTC;                              
  volatile uint32_t INTE;                              
} r_xspi_regs_t;
 
static_assert(sizeof(r_xspi_regs_t) == (uint32_t)k_ra8_xspi_regs_size,
              "r_xspi_regs_t must match FSP R_XSPI0_Type size (412 bytes)");

RA8_HW_REGISTER_ACCESS
static inline volatile r_xspi_regs_t* ra8_xspi(uint8_t instance)
{
  if (instance >= k_ra8_xspi_instance_count) {
    return nullptr;
  }
  return (volatile r_xspi_regs_t*)(k_ra8_xspi0_base_addr +
                                   ((uintptr_t)instance * k_ra8_xspi_stride));
}

typedef enum : uint16_t {
  k_ra8_xspi_lio_1s1s1s = 0x000U, 
  k_ra8_xspi_lio_1s2s2s = 0x048U, 
  k_ra8_xspi_lio_1s4s4s = 0x090U, 
  k_ra8_xspi_lio_1s8s8s = 0x110U, 
  k_ra8_xspi_lio_8d8d8d = 0x3FFU, 
} ra8_xspi_lio_mode_t;

typedef enum : uint8_t {
  k_ra8_xspi_liocfgcs_pos_prtmd  = 0U,  
  k_ra8_xspi_liocfgcs_pos_latemd = 10U, 
  k_ra8_xspi_liocfgcs_pos_ddren  = 11U, 
} ra8_xspi_liocfgcs_pos_t;

typedef enum : uint32_t {
  k_ra8_xspi_liocfgcs_mask_ddren = 1UL << 11U, 
} ra8_xspi_liocfgcs_mask_t;

typedef enum : uint8_t {
  k_ra8_xspi_cmcfgcs_word_mode      = 0U, 
  k_ra8_xspi_cmcfgcs_word_read_cmd  = 1U, 
  k_ra8_xspi_cmcfgcs_word_write_cmd = 2U, 
  k_ra8_xspi_cmcfgcs_word_addr      = 3U, 
  k_ra8_xspi_cmcfgcs_words_per_slot = 4U, 
} ra8_xspi_cmcfgcs_layout_t;

typedef enum : uint8_t {
  k_ra8_xspi_cmcfgcs_pos_cmd       = 16U, 
  k_ra8_xspi_cmcfgcs_pos_addr_size = 0U,  
} ra8_xspi_cmcfgcs_pos_t;

typedef enum : uint8_t {
  k_ra8_xspi_wrapcfg_pos_dssft_cs0 = 8U,  
  k_ra8_xspi_wrapcfg_pos_dssft_cs1 = 24U, 
} ra8_xspi_wrapcfg_pos_t;
 
typedef enum : uint32_t {
  k_ra8_xspi_wrapcfg_dssft_mask = 0x1FUL, 
} ra8_xspi_wrapcfg_mask_t;

typedef enum : uint8_t {
  k_ra8_xspi_ccctl0_pos_caen      = 0U, 
  k_ra8_xspi_ccctlcs_words_per_cs = 8U, 
} ra8_xspi_calib_t;
 
typedef enum : uint32_t {
  k_ra8_xspi_ccctl0_mask_caen = 1UL << 0U, 
} ra8_xspi_calib_mask_t;

typedef enum : uint8_t {
  k_ra8_xspi_cdbuf_word_cdt       = 0U, 
  k_ra8_xspi_cdbuf_word_cda       = 1U, 
  k_ra8_xspi_cdbuf_word_cdd0      = 2U, 
  k_ra8_xspi_cdbuf_word_cdd1      = 3U, 
  k_ra8_xspi_cdbuf_words_per_slot = 4U, 
} ra8_xspi_cdbuf_slot_word_t;

typedef enum : uint8_t {
  k_ra8_xspi_cdt_pos_cmdsize  = 0U,  
  k_ra8_xspi_cdt_pos_addsize  = 2U,  
  k_ra8_xspi_cdt_pos_datasize = 5U,  
  k_ra8_xspi_cdt_pos_late     = 9U,  
  k_ra8_xspi_cdt_pos_trtype   = 15U, 
  k_ra8_xspi_cdt_pos_cmd      = 16U, 
} ra8_xspi_cdt_pos_t;

typedef enum : uint8_t {
  k_ra8_xspi_cdt_addsize_0 = 0U, 
  k_ra8_xspi_cdt_addsize_3 = 3U, 
  k_ra8_xspi_cdt_addsize_4 = 4U, 
} ra8_xspi_cdt_addsize_t;

typedef enum : uint32_t {
  k_ra8_xspi_cdt_mask_cmdsize  = 0x3UL,    
  k_ra8_xspi_cdt_mask_addsize  = 0x7UL,    
  k_ra8_xspi_cdt_mask_datasize = 0xFUL,    
  k_ra8_xspi_cdt_mask_trtype   = 0x1UL,    
  k_ra8_xspi_cdt_mask_cmd      = 0xFFFFUL, 
} ra8_xspi_cdt_field_mask_t;

typedef enum : uint8_t {
  k_ra8_xspi_cdt_cmdsize_0 = 0U, 
  k_ra8_xspi_cdt_cmdsize_1 = 1U, 
  k_ra8_xspi_cdt_cmdsize_2 = 2U, 
} ra8_xspi_cdt_cmdsize_t;

typedef enum : uint8_t {
  k_ra8_xspi_cdt_trtype_read  = 0U, 
  k_ra8_xspi_cdt_trtype_write = 1U, 
} ra8_xspi_cdt_trtype_t;

typedef enum : uint32_t {
  k_ra8_xspi_bmctl0_disabled   = 0x00UL, 
  k_ra8_xspi_bmctl0_read_only  = 0x55UL, 
  k_ra8_xspi_bmctl0_write_only = 0xAAUL, 
  k_ra8_xspi_bmctl0_read_write = 0xFFUL, 
} ra8_xspi_bmctl0_t;

typedef enum : uint32_t {
  k_ra8_xspi_bmctl1_pbufclr_mask = 0x03UL << 10U, 
  k_ra8_xspi_bmctl1_mwrpush_mask = 0x03UL << 8U,  
} ra8_xspi_bmctl1_t;

typedef enum : uint32_t {
  k_ra8_xspi_cmctlch_xipen_pos     = 16U,        
  k_ra8_xspi_cmctlch_xipen_mask    = 1UL << 16U, 
  k_ra8_xspi_cmctlch_xipencode_pos = 0U,         
  k_ra8_xspi_cmctlch_xipexcode_pos = 8U,         
} ra8_xspi_cmctlch_t;

typedef enum : uint8_t {
  k_ra8_xspi_cdctl0_bit_trreq = 0U, 
  k_ra8_xspi_cdctl0_bit_cssel = 3U, 
} ra8_xspi_cdctl0_bit_t;

typedef enum : uint32_t {
  k_ra8_xspi_cdctl0_mask_trreq = 1UL << 0U, 
  k_ra8_xspi_cdctl0_mask_cssel = 1UL << 3U, 
} ra8_xspi_cdctl0_mask_t;

typedef enum : uint32_t {
  k_ra8_xspi_lioctl_mask_wpcs  = 1UL << 0U,  
  k_ra8_xspi_lioctl_mask_rstcs = 1UL << 16U, 
} ra8_xspi_lioctl_mask_t;

typedef enum : uint8_t {
  k_ra8_xspi_ints_bit_cmdcmp = 0U, 
  k_ra8_xspi_ints_bit_patcmp = 1U, 
  k_ra8_xspi_ints_bit_inicmp = 2U, 
} ra8_xspi_ints_bit_t;

typedef enum : uint32_t {
  k_ra8_xspi_ints_mask_cmdcmp = 1UL << 0U,    
  k_ra8_xspi_ints_mask_patcmp = 1UL << 1U,    
  k_ra8_xspi_ints_mask_inicmp = 1UL << 2U,    
  k_ra8_xspi_ints_mask_all    = 0xFFFFFFFFUL, 
} ra8_xspi_ints_mask_t;

typedef enum : uint32_t {
  k_ra8_xspi_inte_mask_cmdcmp = 1UL << 0U, 
} ra8_xspi_inte_mask_t;

typedef enum : uint8_t {
  k_ra8_xspi_comstt_bit_memacc_ch0 = 0U,  
  k_ra8_xspi_comstt_bit_memacc_ch1 = 1U,  
  k_ra8_xspi_comstt_bit_pbufne_ch0 = 4U,  
  k_ra8_xspi_comstt_bit_pbufne_ch1 = 5U,  
  k_ra8_xspi_comstt_bit_ecs_cs0    = 16U, 
  k_ra8_xspi_comstt_bit_int_cs0    = 17U, 
  k_ra8_xspi_comstt_bit_ecs_cs1    = 20U, 
  k_ra8_xspi_comstt_bit_int_cs1    = 21U, 
} ra8_xspi_comstt_bit_t;
 
#ifdef __cplusplus
}
#endif