ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_iwdt_regs.h File Reference
Hardware Abstraction Layer » Timers & watchdogs

Independent Watchdog Timer (IWDT) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"
Include dependency graph for ra8_iwdt_regs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct  r_iwdt_regs_t
 Memory-mapped layout of the IWDT block. More...

Enumerations

enum  ra8_iwdt_addr_t : uintptr_t { k_ra8_iwdt_base_addr = 0x40202200UL }
 Base address of the RA8D2 IWDT instance. More...
enum  ra8_iwdt_refresh_t : uint8_t {
  k_ra8_iwdt_refresh_a = 0x00U ,
  k_ra8_iwdt_refresh_b = 0xFFU
}
 Two-byte unlock pattern written to IWDTRR to refresh. More...
enum  ra8_iwdt_iwdtcr_layout_t : uint16_t {
  k_ra8_iwdt_mask_tops = 0x0003U ,
  k_ra8_iwdt_mask_cks = 0x000FU ,
  k_ra8_iwdt_mask_rpes = 0x0003U ,
  k_ra8_iwdt_mask_rpss = 0x0003U ,
  k_ra8_iwdt_shift_tops = 0U ,
  k_ra8_iwdt_shift_cks = 4U ,
  k_ra8_iwdt_shift_rpes = 8U ,
  k_ra8_iwdt_shift_rpss = 12U
}
 Bit-field layout of the IWDTCR (control) register. More...
enum  ra8_iwdt_iwdtsr_layout_t : uint16_t {
  k_ra8_iwdt_sr_cnt_mask = 0x3FFFU ,
  k_ra8_iwdt_sr_undff = 0x4000U ,
  k_ra8_iwdt_sr_refef = 0x8000U ,
  k_ra8_iwdt_sr_status_shift = 14U
}
 Bit definitions of the IWDTSR (status) register. More...
enum  ra8_iwdt_iwdtrcr_layout_t : uint8_t { k_ra8_iwdt_rcr_rstirqs = 0x80U }
 Bit definitions of the IWDTRCR (reset control) register. More...
enum  ra8_iwdt_iwdtcstpr_layout_t : uint8_t { k_ra8_iwdt_cstpr_slcstp = 0x80U }
 Bit definitions of the IWDTCSTPR (count-stop control) register. More...
enum  ra8_iwdt_ofs0_layout_t : uint32_t {
  k_ra8_iwdt_ofs0_shift_strt = 1U ,
  k_ra8_iwdt_ofs0_shift_tops = 2U ,
  k_ra8_iwdt_ofs0_shift_cks = 4U ,
  k_ra8_iwdt_ofs0_mask_strt = 0x00000002UL ,
  k_ra8_iwdt_ofs0_mask_tops = 0x00000003UL ,
  k_ra8_iwdt_ofs0_mask_cks = 0x0000000FUL ,
  k_ra8_iwdt_ofs0_mask_nmi = 0x00001000UL
}
 Bit positions and field widths of the IWDT view of OFS0. More...

Functions

static volatile r_iwdt_regs_t * ra8_iwdt (void)
 Get pointer to the IWDT register block.
static void ra8_iwdt_refresh (void)
 Refresh the IWDT counter using the two-byte unlock sequence.

Detailed Description

Independent Watchdog Timer (IWDT) register layout for the RA8D2.

The IWDT is a free-running 14-bit down-counter clocked from the IWDT-dedicated low-speed oscillator (IWDTCLK, ~15 kHz on RA8D2), completely independent of the CPU clock tree – so it survives MOCO / HOCO failure. Once started it cannot be stopped by software; the only way to prevent a reset is to refresh it before the counter reaches zero by writing the two-byte sequence 0x00 then 0xFF to IWDTRR.

Most of the IWDT configuration (period, window, reset-vs-NMI, sleep-stop, clock divider) lives in the OFS0 option-setting register, which is read out of MRAM at boot. These fields are NOT runtime-configurable like WDT in register-start mode – the IWDT has only auto-start mode on this part. The IWDTCR / IWDTRCR / IWDTCSTPR registers exist in the memory map (and FSP exposes them) but they are write-locked once OFS0 has booted the timer.

Offset Reg Width RW Purpose
0x00 IWDTRR 8 RW Refresh register
0x01 (rsv) 8 - Reserved
0x02 IWDTCR 16 RW Control (TOPS/CKS/RPES/RPSS)
0x04 IWDTSR 16 RW Status (CNTVAL+UNDFF+REFEF)
0x06 IWDTRCR 8 RW Reset Control (RSTIRQS)
0x07 (rsv) 8 - Reserved
0x08 IWDTCSTPR 8 RW Count-Stop Control (SLCSTP)
0x09 (rsv) 8 - Reserved
0x0A (rsv) 16 - Reserved (pads to 0x0C)

Block size = 12 (0x0C). Layout matches FSP R_IWDT_Type in R7KA8D2KF_core0.h exactly.

Copyright
Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_iwdt_regs.h.

Enumeration Type Documentation

◆ ra8_iwdt_addr_t

enum ra8_iwdt_addr_t : uintptr_t

Base address of the RA8D2 IWDT instance.

The RA8D2 carries a single IWDT (no per-core duplicate the way WDT0 / WDT1 are split across M85 / M33). The base address comes from FSP R7KA8D2KF_core0.h R_IWDT_BASE = 0x40202200.

See also
HUM Ch 28 "Independent Watchdog Timer (IWDT)" p 1271.
Enumerator
k_ra8_iwdt_base_addr 

IWDT register block base.

Definition at line 63 of file ra8_iwdt_regs.h.

◆ ra8_iwdt_iwdtcr_layout_t

enum ra8_iwdt_iwdtcr_layout_t : uint16_t

Bit-field layout of the IWDTCR (control) register.

HUM Ch 28.2.3 "IWDTCR : IWDT Control Register" p 1276 + FSP r_iwdt.c IWDT_PRV_IWDTCR_*_BIT/MASK macros:

  • TOPS[1:0] bits 1:0 – timeout period select
  • CKS[3:0] bits 7:4 – clock divider select
  • RPES[1:0] bits 9:8 – refresh window end position
  • RPSS[1:0] bits 13:12 – refresh window start position

Masks below are the field width (post-shift); shifts are bit positions. The IWDTCR register only takes effect in register-start mode – on the RA8D2 only auto-start is supported, so OFS0 is the effective control surface. The fields exist for symmetry with WDT.

Enumerator
k_ra8_iwdt_mask_tops 

TOPS field width (2 bits).

k_ra8_iwdt_mask_cks 

CKS field width (4 bits).

k_ra8_iwdt_mask_rpes 

RPES field width (2 bits).

k_ra8_iwdt_mask_rpss 

RPSS field width (2 bits).

k_ra8_iwdt_shift_tops 

TOPS occupies bits 1:0.

k_ra8_iwdt_shift_cks 

CKS occupies bits 7:4.

k_ra8_iwdt_shift_rpes 

RPES occupies bits 9:8.

k_ra8_iwdt_shift_rpss 

RPSS occupies bits 13:12.

Definition at line 100 of file ra8_iwdt_regs.h.

◆ ra8_iwdt_iwdtcstpr_layout_t

enum ra8_iwdt_iwdtcstpr_layout_t : uint8_t

Bit definitions of the IWDTCSTPR (count-stop control) register.

HUM Ch 28.2.5 "IWDTCSTPR : IWDT Count Stop Control Register" p 1278 – only SLCSTP (bit 7) is implemented. Mirrors FSP IWDT_PRV_IWDTCSTPR_STOP_CONTROL_BIT.

Enumerator
k_ra8_iwdt_cstpr_slcstp 

SLCSTP = bit 7 (1 = halt counter in Sleep).

Definition at line 155 of file ra8_iwdt_regs.h.

◆ ra8_iwdt_iwdtrcr_layout_t

enum ra8_iwdt_iwdtrcr_layout_t : uint8_t

Bit definitions of the IWDTRCR (reset control) register.

HUM Ch 28.2.4 "IWDTRCR : IWDT Reset Control Register" p 1277 – only RSTIRQS (bit 7) is implemented. Mirrors FSP IWDT_PRV_IWDTRCR_RESET_CONTROL_BIT.

Enumerator
k_ra8_iwdt_rcr_rstirqs 

RSTIRQS = bit 7 (1 = reset, 0 = NMI / IRQ).

Definition at line 142 of file ra8_iwdt_regs.h.

◆ ra8_iwdt_iwdtsr_layout_t

enum ra8_iwdt_iwdtsr_layout_t : uint16_t

Bit definitions of the IWDTSR (status) register.

HUM Ch 28.2.2 "IWDTSR : IWDT Status Register" p 1274 + FSP IWDT_PRV_IWDTSR_COUNTER_MASK / IWDT_PRV_STATUS_START_BIT:

  • CNTVAL[13:0] bits 13:0 – live down-counter value (RO)
  • UNDFF bit 14 – underflow flag (W0C)
  • REFEF bit 15 – refresh-error flag (W0C)

Per the HUM both flag bits are write-zero-to-clear AFTER at least one IWDTCLK cycle has elapsed since the flag was set; FSP polls in a do/while loop until the read-back confirms the bits are gone.

Enumerator
k_ra8_iwdt_sr_cnt_mask 

CNTVAL[13:0] mask.

k_ra8_iwdt_sr_undff 

UNDFF bit 14 (underflow flag).

k_ra8_iwdt_sr_refef 

REFEF bit 15 (refresh-error).

k_ra8_iwdt_sr_status_shift 

Shift to extract UNDFF/REFEF pair.

Definition at line 126 of file ra8_iwdt_regs.h.

◆ ra8_iwdt_ofs0_layout_t

enum ra8_iwdt_ofs0_layout_t : uint32_t

Bit positions and field widths of the IWDT view of OFS0.

HUM Ch 7 + FSP r_iwdt.c IWDT_PRV_OFS0_*_BIT/MASK:

  • IWDTSTRT bit 1 – 0 = auto-start, 1 = stopped (RA8D2 supports auto-start only)
  • IWDTTOPS bits 3:2 – timeout period
  • IWDTCKS bits 7:4 – clock divider
  • IWDTRPES bits 9:8 – refresh window end (mirrors WDT)
  • IWDTRPSS bits 13:12 – refresh window start (mirrors WDT)
  • IWDTRSTIRQS bit 12 – ALSO bit 12 in some doc revisions; FSP defines NMI request mask = 0x1000 (bit 12). Use this enum value (k_ra8_iwdt_ofs0_mask_nmi) to test whether NMI vs reset is selected for IWDT underflow.
  • IWDTSTPCTL bit 14 – 1 = halt counter in Sleep, 0 = run

Note: The HUM uses IWDT field-name prefixes; FSP uses bare names. We document the HUM names; the macros are identical to the WDT layout in ra8_wdt_regs.h because OFS0 packs them in the same relative positions inside the lower 16 bits.

Enumerator
k_ra8_iwdt_ofs0_shift_strt 

IWDTSTRT bit.

k_ra8_iwdt_ofs0_shift_tops 

IWDTTOPS shift (bits 3:2).

k_ra8_iwdt_ofs0_shift_cks 

IWDTCKS shift (bits 7:4).

k_ra8_iwdt_ofs0_mask_strt 

IWDTSTRT (bit 1) full mask.

k_ra8_iwdt_ofs0_mask_tops 

IWDTTOPS field width.

k_ra8_iwdt_ofs0_mask_cks 

IWDTCKS field width.

k_ra8_iwdt_ofs0_mask_nmi 

NMI request select bit 12.

Definition at line 184 of file ra8_iwdt_regs.h.

◆ ra8_iwdt_refresh_t

enum ra8_iwdt_refresh_t : uint8_t

Two-byte unlock pattern written to IWDTRR to refresh.

Per HUM Ch 28.2.1 "IWDTRR : IWDT Refresh Register" p 1273, the only legal way to reload the down-counter is to write 0x00 followed by 0xFF; any other sequence is silently dropped. A SINGLE write does not refresh – the FSP r_iwdt_refresh and our ra8_iwdt_refresh both perform both writes.

Enumerator
k_ra8_iwdt_refresh_a 

First byte of the refresh sequence.

k_ra8_iwdt_refresh_b 

Second byte of the refresh sequence.

Definition at line 78 of file ra8_iwdt_regs.h.

Function Documentation

◆ ra8_iwdt()

volatile r_iwdt_regs_t * ra8_iwdt ( void )
inlinestatic

Get pointer to the IWDT register block.

Returns
Pointer to the IWDT registers.
Precondition
IWDTCLK (the dedicated low-speed oscillator) is enabled at reset by hardware; nothing software-side is required to bring this peripheral online.
Postcondition
No hardware state is touched.
See also
HUM Ch 28.1 "Overview" p 1271.

Definition at line 237 of file ra8_iwdt_regs.h.

References k_ra8_iwdt_base_addr.

Referenced by ra8_iwdt_clear_status(), ra8_iwdt_dispatch(), ra8_iwdt_get_counter(), ra8_iwdt_get_status(), and ra8_iwdt_refresh().

◆ ra8_iwdt_refresh()

void ra8_iwdt_refresh ( void )
inlinestatic

Refresh the IWDT counter using the two-byte unlock sequence.

Writes 0x00 then 0xFF to IWDTRR – the only legal arming sequence per HUM Ch 28.2.1 p 1273 + FSP r_iwdt_refresh. Any deviation (single write, wrong order, intermediate write to another register that maps to bit-0..7 of IWDTRR) is silently dropped by silicon and the next underflow will reset the chip.

Must happen strictly faster than the IWDT period programmed in OFS0; the actual deadline depends on IWDTCLK frequency (~15 kHz) times IWDTTOPS cycles divided by IWDTCKS.

Precondition
OFS0 has armed the IWDT (auto-start mode).
Postcondition
IWDTRR holds 0xFF and the down-counter has reloaded.
Note
Not thread-safe. For a multi-task RTOS port, route refreshes through a single heartbeat aggregator task.
Warning
A SINGLE write to IWDTRR does NOT refresh the counter; both bytes are required, in order.
Precondition
Module state is consistent.
Postcondition
Caller-visible state matches the documented contract.
Since
0.1.0

Definition at line 270 of file ra8_iwdt_regs.h.

References r_iwdt_regs_t::IWDTRR, k_ra8_iwdt_refresh_a, k_ra8_iwdt_refresh_b, and ra8_iwdt().

Referenced by ra8_iwdt_refresh_deferred().