ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_iwdt_regs.h
Go to the documentation of this file.
1
41
42#pragma once
43
44#ifdef __cplusplus
45extern "C" {
46#endif
47
48#include <stdint.h>
49
50#include "ra8_attributes.h"
51
63typedef enum : uintptr_t {
64 k_ra8_iwdt_base_addr = 0x40202200UL,
66
78typedef enum : uint8_t {
82
110
132
142typedef enum : uint8_t {
145
155typedef enum : uint8_t {
158
193
211typedef struct {
212 /* HUM Ch 28.2 "Register Descriptions" p 1273 */ /* + FSP R_IWDT_Type */
213 volatile uint8_t IWDTRR;
214 volatile uint8_t _r0;
215 volatile uint16_t IWDTCR;
216 volatile uint16_t IWDTSR;
217 volatile uint8_t IWDTRCR;
218 volatile uint8_t _r1;
219 volatile uint8_t IWDTCSTPR;
220 volatile uint8_t _r2;
221 volatile uint16_t _r3;
223
237static inline volatile r_iwdt_regs_t* ra8_iwdt(void)
238{
239 /* HUM Ch 28.1 "Overview" p 1271 */
240 return (volatile r_iwdt_regs_t*)k_ra8_iwdt_base_addr;
241}
242
270static inline void ra8_iwdt_refresh(void)
271{
272 /* HUM Ch 28.2.1 "IWDTRR : IWDT Refresh Register", p 1273
273 * + FSP r_iwdt_refresh (writes IWDT_PRV_REFRESH_STEP_1 then _2). */
274 volatile r_iwdt_regs_t* w = ra8_iwdt();
277}
278
279#ifdef __cplusplus
280}
281#endif
Annotation-attribute framework macros for ra8-firmware.
#define RA8_HW_REGISTER_ACCESS
Mark an MMIO accessor function (returns volatile register pointer).
static volatile r_iwdt_regs_t * ra8_iwdt(void)
Get pointer to the IWDT register block.
static void ra8_iwdt_refresh(void)
Refresh the IWDT counter using the two-byte unlock sequence.
ra8_iwdt_iwdtrcr_layout_t
Bit definitions of the IWDTRCR (reset control) register.
@ k_ra8_iwdt_rcr_rstirqs
RSTIRQS = bit 7 (1 = reset, 0 = NMI / IRQ).
ra8_iwdt_ofs0_layout_t
Bit positions and field widths of the IWDT view of OFS0.
@ k_ra8_iwdt_ofs0_shift_strt
IWDTSTRT bit.
@ k_ra8_iwdt_ofs0_mask_cks
IWDTCKS field width.
@ k_ra8_iwdt_ofs0_shift_tops
IWDTTOPS shift (bits 3:2).
@ k_ra8_iwdt_ofs0_mask_tops
IWDTTOPS field width.
@ k_ra8_iwdt_ofs0_shift_cks
IWDTCKS shift (bits 7:4).
@ k_ra8_iwdt_ofs0_mask_nmi
NMI request select bit 12.
@ k_ra8_iwdt_ofs0_mask_strt
IWDTSTRT (bit 1) full mask.
ra8_iwdt_refresh_t
Two-byte unlock pattern written to IWDTRR to refresh.
@ k_ra8_iwdt_refresh_a
First byte of the refresh sequence.
@ k_ra8_iwdt_refresh_b
Second byte of the refresh sequence.
ra8_iwdt_iwdtcr_layout_t
Bit-field layout of the IWDTCR (control) register.
@ k_ra8_iwdt_shift_tops
TOPS occupies bits 1:0.
@ k_ra8_iwdt_mask_rpss
RPSS field width (2 bits).
@ k_ra8_iwdt_shift_rpss
RPSS occupies bits 13:12.
@ k_ra8_iwdt_mask_cks
CKS field width (4 bits).
@ k_ra8_iwdt_mask_rpes
RPES field width (2 bits).
@ k_ra8_iwdt_shift_cks
CKS occupies bits 7:4.
@ k_ra8_iwdt_mask_tops
TOPS field width (2 bits).
@ k_ra8_iwdt_shift_rpes
RPES occupies bits 9:8.
ra8_iwdt_iwdtcstpr_layout_t
Bit definitions of the IWDTCSTPR (count-stop control) register.
@ k_ra8_iwdt_cstpr_slcstp
SLCSTP = bit 7 (1 = halt counter in Sleep).
ra8_iwdt_addr_t
Base address of the RA8D2 IWDT instance.
@ k_ra8_iwdt_base_addr
IWDT register block base.
ra8_iwdt_iwdtsr_layout_t
Bit definitions of the IWDTSR (status) register.
@ k_ra8_iwdt_sr_undff
UNDFF bit 14 (underflow flag).
@ k_ra8_iwdt_sr_status_shift
Shift to extract UNDFF/REFEF pair.
@ k_ra8_iwdt_sr_cnt_mask
CNTVAL[13:0] mask.
@ k_ra8_iwdt_sr_refef
REFEF bit 15 (refresh-error).
Memory-mapped layout of the IWDT block.
volatile uint8_t IWDTRR
+0x00 Refresh register.
volatile uint8_t _r0
+0x01 Reserved.
volatile uint8_t _r1
+0x07 Reserved.
volatile uint8_t _r2
+0x09 Reserved.
volatile uint16_t IWDTSR
+0x04 Status register.
volatile uint8_t IWDTRCR
+0x06 Reset control register.
volatile uint16_t _r3
+0x0A Reserved (pads to 0x0C).
volatile uint16_t IWDTCR
+0x02 Control register.
volatile uint8_t IWDTCSTPR
+0x08 Count-stop control register.