ra8_wdt_regs.h File Reference

Watchdog Timer (WDT) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_wdt_regs.h:

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Go to the source code of this file.

Data Structures
struct	r_wdt_regs_t
	Memory-mapped layout of one WDT instance. More...

Enumerations
enum	ra8_wdt_addr_t : uintptr_t {   k_ra8_wdt_base_addr = 0x40202600UL ,   k_ra8_wdt0_base_addr = 0x40202600UL ,   k_ra8_wdt1_base_addr = 0x40202700UL }
	Base addresses of the WDT instances on RA8D2. More...
enum	ra8_wdt_refresh_t : uint8_t {   k_ra8_wdt_refresh_a = 0x00U ,   k_ra8_wdt_refresh_b = 0xFFU }
	Two-byte unlock pattern written to WDTRR to refresh. More...
enum	ra8_wdt_instance_t : uint8_t {   k_ra8_wdt0 = 0U ,   k_ra8_wdt1 = 1U ,   k_ra8_wdt_instance_count = 2U }
	Hardware instance selector used by per-instance helpers. More...
enum	ra8_wdt_wdtcr_layout_t : uint16_t {   k_ra8_wdt_mask_tops = 0x0003U ,   k_ra8_wdt_mask_cks = 0x000FU ,   k_ra8_wdt_mask_rpes = 0x0003U ,   k_ra8_wdt_mask_rpss = 0x0003U ,   k_ra8_wdt_shift_tops = 0U ,   k_ra8_wdt_shift_cks = 4U ,   k_ra8_wdt_shift_rpes = 8U ,   k_ra8_wdt_shift_rpss = 12U }
	Bit-field layout of the WDTCR (control) register. More...
enum	ra8_wdt_wdtsr_layout_t : uint16_t {   k_ra8_wdt_sr_cnt_mask = 0x3FFFU ,   k_ra8_wdt_sr_undff = 0x4000U ,   k_ra8_wdt_sr_refef = 0x8000U }
	Bit definitions of the WDTSR (status) register. More...
enum	ra8_wdt_wdtrcr_layout_t : uint8_t { k_ra8_wdt_rcr_rstirqs = 0x80U }
	Bit definitions of the WDTRCR (reset control) register. More...
enum	ra8_wdt_wdtcstpr_layout_t : uint8_t { k_ra8_wdt_cstpr_slcstp = 0x80U }
	Bit definitions of the WDTCSTPR (count stop control) register. More...
enum	ra8_wdt_cycles_t : uint16_t {   k_ra8_wdt_cycles_1024 = 1024U ,   k_ra8_wdt_cycles_4096 = 4096U ,   k_ra8_wdt_cycles_8192 = 8192U ,   k_ra8_wdt_cycles_16384 = 16384U }
	TOPS-field decoded cycle counts. More...
enum	ra8_wdt_div_value_t : uint16_t {   k_ra8_wdt_div_value_4 = 4U ,   k_ra8_wdt_div_value_64 = 64U ,   k_ra8_wdt_div_value_128 = 128U ,   k_ra8_wdt_div_value_512 = 512U ,   k_ra8_wdt_div_value_2048 = 2048U ,   k_ra8_wdt_div_value_8192 = 8192U }
	CKS-field decoded numeric divisors. More...
enum	ra8_wdt_nmier_layout_t : uint32_t { k_ra8_wdt_nmier_wdten_mask = 0x00000002UL }
	WDT-relevant bit in the ICU's NMIER register. More...
enum	ra8_wdt_ofs_layout_t : uint32_t {   k_ra8_wdt_ofs_shift_strt = 17U ,   k_ra8_wdt_ofs_shift_tops = 18U ,   k_ra8_wdt_ofs_shift_cks = 20U ,   k_ra8_wdt_ofs_shift_rpes = 24U ,   k_ra8_wdt_ofs_shift_rpss = 26U ,   k_ra8_wdt_ofs_shift_rstirqs = 28U ,   k_ra8_wdt_ofs_shift_stpctl = 30U ,   k_ra8_wdt_ofs_mask_strt = 0x1U ,   k_ra8_wdt_ofs_mask_tops = 0x3U ,   k_ra8_wdt_ofs_mask_cks = 0xFU ,   k_ra8_wdt_ofs_mask_rpes = 0x3U ,   k_ra8_wdt_ofs_mask_rpss = 0x3U ,   k_ra8_wdt_ofs_mask_rstirqs = 0x1U ,   k_ra8_wdt_ofs_mask_stpctl = 0x1U ,   k_ra8_wdt_ofs_field_mask = 0x5FFE0000UL }
	Bit positions and field widths of the WDT view of OFSm. More...

Functions
static volatile r_wdt_regs_t *	ra8_wdt (void)
	Get pointer to WDT0 (the default / M85-side instance).
static volatile r_wdt_regs_t *	ra8_wdt_for (ra8_wdt_instance_t which)
	Get pointer to a specific WDT instance.
static void	ra8_wdt_refresh (void)
	Refresh the WDT0 instance using the two-byte unlock sequence.
static void	ra8_wdt_refresh_instance (ra8_wdt_instance_t which)
	Refresh a specific WDT instance.

Detailed Description

Watchdog Timer (WDT) register layout for the RA8D2.

The WDT is the software-clocked companion to the IWDT. Where the IWDT runs from its own oscillator and cannot be stopped, the WDT shares PCLKB with the rest of the peripherals and can be halted by debug. Use the IWDT for safety resets and the WDT for application liveness checks that should pause when the debugger halts.

This header is the single source of truth for WDT register-level constants – bit positions, masks, raw encoding values for the OFSm mirror of the same fields, and the dispatch instance count. The higher-level driver (ra8_wdt.h) layers semantic enum names on top.

Offset	Reg	Width	RW	Purpose
0x00	WDTRR	8	RW	Refresh register
0x02	WDTCR	16	RW	Control register
0x04	WDTSR	16	R	Status register
0x06	WDTRCR	8	RW	Reset control
0x08	WDTCSTPR	8	RW	Count Stop control

All citations point at the RA8D2 Hardware User's Manual (R01UH1065EJ), chapter 27 "Watchdog Timer (WDT)" pages 1256-1270. The block is 12 bytes (0x0C) total – matches FSP R_WDT_Type in R7KA8D2KF_core0.h.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_wdt_regs.h.

Enumeration Type Documentation

ra8_wdt_addr_t

enum ra8_wdt_addr_t : uintptr_t

Base addresses of the WDT instances on RA8D2.

The chip carries two WDTs: WDT0 lives on the Cortex-M85 side and WDT1 on the Cortex-M33 side. Both share the same register layout (this file's r_wdt_regs_t) so a single driver reaches both.

See also

HUM Ch 27.1.2 "Block Diagram" p 1256.

Enumerator
k_ra8_wdt_base_addr	WDT0 base (M85 side).
k_ra8_wdt0_base_addr	Alias for WDT0.
k_ra8_wdt1_base_addr	WDT1 base (M33 side).

Definition at line 57 of file ra8_wdt_regs.h.

ra8_wdt_cycles_t

enum ra8_wdt_cycles_t : uint16_t

TOPS-field decoded cycle counts.

HUM Ch 27.2.2 Table 27.2 p 1259 row by row.

Enumerator
k_ra8_wdt_cycles_1024	TOPS = 0b00.
k_ra8_wdt_cycles_4096	TOPS = 0b01.
k_ra8_wdt_cycles_8192	TOPS = 0b10.
k_ra8_wdt_cycles_16384	TOPS = 0b11.

Definition at line 170 of file ra8_wdt_regs.h.

ra8_wdt_div_value_t

enum ra8_wdt_div_value_t : uint16_t

CKS-field decoded numeric divisors.

HUM Ch 27.2.2 p 1258 – only six CKS encodings are legal; the others are marked "Setting prohibited".

Enumerator
k_ra8_wdt_div_value_4	RA8 wdt div value 4.
k_ra8_wdt_div_value_64	RA8 wdt div value 64.
k_ra8_wdt_div_value_128	RA8 wdt div value 128.
k_ra8_wdt_div_value_512	RA8 wdt div value 512.
k_ra8_wdt_div_value_2048	RA8 wdt div value 2048.
k_ra8_wdt_div_value_8192	RA8 wdt div value 8192.

Definition at line 185 of file ra8_wdt_regs.h.

ra8_wdt_instance_t

enum ra8_wdt_instance_t : uint8_t

Hardware instance selector used by per-instance helpers.

RA8D2 carries WDT0 (M85) and WDT1 (M33). The driver exposes per-instance refresh / OFSm decode helpers so a single firmware image can manage both cores' watchdogs.

See also

HUM Ch 27.1 "Overview" p 1256.

Enumerator
k_ra8_wdt0	WDT0 – Cortex-M85 side.
k_ra8_wdt1	WDT1 – Cortex-M33 side.
k_ra8_wdt_instance_count	Number of WDT instances on RA8D2.

Definition at line 91 of file ra8_wdt_regs.h.

ra8_wdt_nmier_layout_t

enum ra8_wdt_nmier_layout_t : uint32_t

WDT-relevant bit in the ICU's NMIER register.

HUM Ch 14.2.14 "NMIER" p 542 – the WDT underflow / refresh-error source is gated by WDTEN at bit 1 (mask 0x2). The companion NMICLR register (Ch 14.2.15 p 544) uses the same bit position for the W1C flag clear.

Enumerator
k_ra8_wdt_nmier_wdten_mask	NMIER.WDTEN = bit 1.

Definition at line 204 of file ra8_wdt_regs.h.

ra8_wdt_ofs_layout_t

enum ra8_wdt_ofs_layout_t : uint32_t

Bit positions and field widths of the WDT view of OFSm.

HUM Ch 27.3.8 Table 27.5 p 1269 – the OFS0 word (consumed by WDT0) and OFS3 word (consumed by WDT1) carry seven WDT-related fields in the same bit layout:

• WDTSTRT bit 17 – start mode (0 = auto, 1 = register)
• WDTTOPS bits 19:18 – timeout period
• WDTCKS bits 23:20 – clock divider
• WDTRPES bits 25:24 – refresh window end
• WDTRPSS bits 27:26 – refresh window start
• WDTRSTIRQS bit 28 – reset (1) or NMI / IRQ (0)
• WDTSTPCTL bit 30 – 1 = halt counter in Sleep, 0 = keep

Masks are post-shift (i.e. the field width); shifts are bit positions inside the 32-bit OFSm word.

k_ra8_wdt_ofs_field_mask is the union of all seven fields in place. It matters because OFS3_SEL (HUM Ch 7.2.7 p 289) is a per-field selector whose bits sit at exactly these positions: for each field, 0 selects OFS3_SEC and 1 selects OFS3. That co-location is what lets ra8_wdt_ofs_get resolve WDT1 with a single bitwise mux instead of seven field extractions.

Enumerator
k_ra8_wdt_ofs_shift_strt	OFSm.WDTSTRT shift.
k_ra8_wdt_ofs_shift_tops	OFSm.WDTTOPS shift.
k_ra8_wdt_ofs_shift_cks	OFSm.WDTCKS shift.
k_ra8_wdt_ofs_shift_rpes	OFSm.WDTRPES shift.
k_ra8_wdt_ofs_shift_rpss	OFSm.WDTRPSS shift.
k_ra8_wdt_ofs_shift_rstirqs	OFSm.WDTRSTIRQS shift.
k_ra8_wdt_ofs_shift_stpctl	OFSm.WDTSTPCTL shift.
k_ra8_wdt_ofs_mask_strt	1-bit field.
k_ra8_wdt_ofs_mask_tops	2-bit field.
k_ra8_wdt_ofs_mask_cks	4-bit field.
k_ra8_wdt_ofs_mask_rpes	2-bit field.
k_ra8_wdt_ofs_mask_rpss	2-bit field.
k_ra8_wdt_ofs_mask_rstirqs	1-bit field.
k_ra8_wdt_ofs_mask_stpctl	1-bit field.
k_ra8_wdt_ofs_field_mask	Union of all seven fields.

Definition at line 235 of file ra8_wdt_regs.h.

ra8_wdt_refresh_t

enum ra8_wdt_refresh_t : uint8_t

Two-byte unlock pattern written to WDTRR to refresh.

Per HUM Ch 27.2.1 p 1257 the only legal way to reload the down- counter is to write 0x00 followed by 0xFF; any other sequence is silently dropped.

Enumerator
k_ra8_wdt_refresh_a	First byte of the refresh sequence.
k_ra8_wdt_refresh_b	Second byte of the refresh sequence.

Definition at line 75 of file ra8_wdt_regs.h.

ra8_wdt_wdtcr_layout_t

enum ra8_wdt_wdtcr_layout_t : uint16_t

Bit-field layout of the WDTCR (control) register.

HUM Ch 27.2.2 "WDTCR : WDT Control Register" p 1258 defines:

• TOPS[1:0] bits 1:0 – timeout period select
• CKS[3:0] bits 7:4 – clock divider select
• RPES[1:0] bits 9:8 – refresh window end
• RPSS[1:0] bits 13:12 – refresh window start

Masks are the field-width before shifting; shifts are the bit positions. internal_pack_wdtcr ANDs the caller-supplied enum with the mask and shifts into place.

Enumerator
k_ra8_wdt_mask_tops	TOPS field width (2 bits).
k_ra8_wdt_mask_cks	CKS field width (4 bits).
k_ra8_wdt_mask_rpes	RPES field width (2 bits).
k_ra8_wdt_mask_rpss	RPSS field width (2 bits).
k_ra8_wdt_shift_tops	TOPS occupies bits 1:0.
k_ra8_wdt_shift_cks	CKS occupies bits 7:4.
k_ra8_wdt_shift_rpes	RPES occupies bits 9:8.
k_ra8_wdt_shift_rpss	RPSS occupies bits 13:12.

Definition at line 112 of file ra8_wdt_regs.h.

ra8_wdt_wdtcstpr_layout_t

enum ra8_wdt_wdtcstpr_layout_t : uint8_t

Bit definitions of the WDTCSTPR (count stop control) register.

HUM Ch 27.2.5 "WDTCSTPR : WDT Count Stop Control Register" p 1262 – only SLCSTP (bit 7) is implemented.

Enumerator
k_ra8_wdt_cstpr_slcstp	SLCSTP = bit 7 (1 = halt counter in Sleep).

Definition at line 159 of file ra8_wdt_regs.h.

ra8_wdt_wdtrcr_layout_t

enum ra8_wdt_wdtrcr_layout_t : uint8_t

Bit definitions of the WDTRCR (reset control) register.

HUM Ch 27.2.4 "WDTRCR : WDT Reset Control Register" p 1262 – only the high bit RSTIRQS is implemented; all other bits read 0.

Enumerator
k_ra8_wdt_rcr_rstirqs	RSTIRQS = bit 7 (1 = reset, 0 = NMI / IRQ).

Definition at line 147 of file ra8_wdt_regs.h.

ra8_wdt_wdtsr_layout_t

enum ra8_wdt_wdtsr_layout_t : uint16_t

Bit definitions of the WDTSR (status) register.

HUM Ch 27.2.3 "WDTSR : WDT Status Register" p 1260:

• CNTVAL[13:0] bits 13:0 – live down-counter value (RO)
• UNDFF bit 14 – underflow flag (W0C)
• REFEF bit 15 – refresh-error flag (W0C)

Enumerator
k_ra8_wdt_sr_cnt_mask	CNTVAL[13:0] mask.
k_ra8_wdt_sr_undff	UNDFF bit 14.
k_ra8_wdt_sr_refef	REFEF bit 15.

Definition at line 133 of file ra8_wdt_regs.h.

Function Documentation

ra8_wdt()

volatile r_wdt_regs_t * ra8_wdt ( void )

inlinestatic

Get pointer to WDT0 (the default / M85-side instance).

Returns

Pointer to the WDT0 register block.

Precondition

WDT module-stop bit cleared (always-on for WDT, but listed for symmetry with other peripherals).

Postcondition

No hardware state is touched.

See also

HUM Ch 27.1 "Overview" p 1256.

Definition at line 301 of file ra8_wdt_regs.h.

References k_ra8_wdt_base_addr.

Referenced by ra8_wdt_clear_status(), ra8_wdt_clear_status_blocking(), ra8_wdt_deinit(), ra8_wdt_dispatch(), ra8_wdt_enter_stop(), ra8_wdt_exit_stop(), ra8_wdt_get_counter(), ra8_wdt_get_status(), ra8_wdt_init(), and ra8_wdt_refresh().

ra8_wdt_for()

volatile r_wdt_regs_t * ra8_wdt_for ( ra8_wdt_instance_t which )

inlinestatic

Get pointer to a specific WDT instance.

Parameters

[in]

which

Instance selector.

Returns

Pointer to the targeted WDT register block, or WDT0 if which is out of range (defensive fallback).

Precondition

which < k_ra8_wdt_instance_count.

Postcondition

No hardware state is touched.

See also

HUM Ch 27.1 "Overview" p 1256.

Definition at line 320 of file ra8_wdt_regs.h.

References k_ra8_wdt0, k_ra8_wdt0_base_addr, k_ra8_wdt1, k_ra8_wdt1_base_addr, and k_ra8_wdt_instance_count.

Referenced by ra8_wdt_refresh_instance().

ra8_wdt_refresh()

void ra8_wdt_refresh ( void )

inlinestatic

Refresh the WDT0 instance using the two-byte unlock sequence.

Writes 0x00 then 0xFF to WDTRR – the only legal arming sequence per HUM Ch 27.2.1 p 1257. Any deviation is silently dropped by silicon.

Precondition

WDT0 is in register-start mode and ra8_wdt_init has run, OR WDT0 is in auto-start mode (refresh works in either case).

Postcondition

WDTRR holds 0xFF and the down-counter has reloaded.

Note

Not thread-safe; serialise externally if multiple writers.

Precondition

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Since

0.1.0

Definition at line 352 of file ra8_wdt_regs.h.

References k_ra8_wdt_refresh_a, k_ra8_wdt_refresh_b, ra8_wdt(), and r_wdt_regs_t::WDTRR.

Referenced by ra8_wdt_init(), and ra8_wdt_refresh_deferred().

ra8_wdt_refresh_instance()

void ra8_wdt_refresh_instance ( ra8_wdt_instance_t which )

inlinestatic

Refresh a specific WDT instance.

Parameters

[in]

which

Instance selector.

Precondition

which < k_ra8_wdt_instance_count.

Postcondition

Targeted instance's WDTRR holds 0xFF.

Note

Not thread-safe.

See also

HUM Ch 27.2.1 "WDTRR : WDT Refresh Register", p 1257.

See implementation.

Precondition

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Since

0.1.0

Definition at line 377 of file ra8_wdt_regs.h.

References k_ra8_wdt_refresh_a, k_ra8_wdt_refresh_b, ra8_wdt_for(), and r_wdt_regs_t::WDTRR.

Referenced by ra8_wdt_refresh_for().