ra8_wdt_regs.h

Go to the documentation of this file.

 
#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  /* HUM Ch 27.1 + FSP R7KA8D2KF_core0.h R_WDT_BASE = 0x40202600,
   * R_WDT1_BASE = 0x40202700. The two instances are 0x100 apart,
   * NOT 0x10000 as an earlier version of this header claimed. */
  k_ra8_wdt_base_addr  = 0x40202600UL, 
  k_ra8_wdt0_base_addr = 0x40202600UL, 
  k_ra8_wdt1_base_addr = 0x40202700UL, 
} ra8_wdt_addr_t;

typedef enum : uint8_t {
  k_ra8_wdt_refresh_a = 0x00U, 
  k_ra8_wdt_refresh_b = 0xFFU, 
} ra8_wdt_refresh_t;

typedef enum : uint8_t {
  k_ra8_wdt0               = 0U, 
  k_ra8_wdt1               = 1U, 
  k_ra8_wdt_instance_count = 2U, 
} ra8_wdt_instance_t;

typedef enum : uint16_t {
  k_ra8_wdt_mask_tops  = 0x0003U, 
  k_ra8_wdt_mask_cks   = 0x000FU, 
  k_ra8_wdt_mask_rpes  = 0x0003U, 
  k_ra8_wdt_mask_rpss  = 0x0003U, 
  k_ra8_wdt_shift_tops = 0U,      
  k_ra8_wdt_shift_cks  = 4U,      
  k_ra8_wdt_shift_rpes = 8U,      
  k_ra8_wdt_shift_rpss = 12U,     
} ra8_wdt_wdtcr_layout_t;

typedef enum : uint16_t {
  k_ra8_wdt_sr_cnt_mask = 0x3FFFU, 
  k_ra8_wdt_sr_undff    = 0x4000U, 
  k_ra8_wdt_sr_refef    = 0x8000U, 
} ra8_wdt_wdtsr_layout_t;

typedef enum : uint8_t {
  k_ra8_wdt_rcr_rstirqs = 0x80U, 
} ra8_wdt_wdtrcr_layout_t;

typedef enum : uint8_t {
  k_ra8_wdt_cstpr_slcstp = 0x80U, 
} ra8_wdt_wdtcstpr_layout_t;

typedef enum : uint16_t {
  k_ra8_wdt_cycles_1024  = 1024U,  
  k_ra8_wdt_cycles_4096  = 4096U,  
  k_ra8_wdt_cycles_8192  = 8192U,  
  k_ra8_wdt_cycles_16384 = 16384U, 
} ra8_wdt_cycles_t;

typedef enum : uint16_t {
  k_ra8_wdt_div_value_4    = 4U,    
  k_ra8_wdt_div_value_64   = 64U,   
  k_ra8_wdt_div_value_128  = 128U,  
  k_ra8_wdt_div_value_512  = 512U,  
  k_ra8_wdt_div_value_2048 = 2048U, 
  k_ra8_wdt_div_value_8192 = 8192U, 
} ra8_wdt_div_value_t;

typedef enum : uint32_t {
  k_ra8_wdt_nmier_wdten_mask = 0x00000002UL, 
} ra8_wdt_nmier_layout_t;

typedef enum : uint32_t {
  k_ra8_wdt_ofs_shift_strt    = 17U,  
  k_ra8_wdt_ofs_shift_tops    = 18U,  
  k_ra8_wdt_ofs_shift_cks     = 20U,  
  k_ra8_wdt_ofs_shift_rpes    = 24U,  
  k_ra8_wdt_ofs_shift_rpss    = 26U,  
  k_ra8_wdt_ofs_shift_rstirqs = 28U,  
  k_ra8_wdt_ofs_shift_stpctl  = 30U,  
  k_ra8_wdt_ofs_mask_strt     = 0x1U, 
  k_ra8_wdt_ofs_mask_tops     = 0x3U, 
  k_ra8_wdt_ofs_mask_cks      = 0xFU, 
  k_ra8_wdt_ofs_mask_rpes     = 0x3U, 
  k_ra8_wdt_ofs_mask_rpss     = 0x3U, 
  k_ra8_wdt_ofs_mask_rstirqs  = 0x1U, 
  k_ra8_wdt_ofs_mask_stpctl   = 0x1U, 
  /* bit 17 | 19:18 | 23:20 | 25:24 | 27:26 | 28 | 30 */
  k_ra8_wdt_ofs_field_mask = 0x5FFE0000UL, 
} ra8_wdt_ofs_layout_t;
 
static_assert(k_ra8_wdt_ofs_field_mask ==
                (((uint32_t)k_ra8_wdt_ofs_mask_strt << k_ra8_wdt_ofs_shift_strt) |
                 ((uint32_t)k_ra8_wdt_ofs_mask_tops << k_ra8_wdt_ofs_shift_tops) |
                 ((uint32_t)k_ra8_wdt_ofs_mask_cks << k_ra8_wdt_ofs_shift_cks) |
                 ((uint32_t)k_ra8_wdt_ofs_mask_rpes << k_ra8_wdt_ofs_shift_rpes) |
                 ((uint32_t)k_ra8_wdt_ofs_mask_rpss << k_ra8_wdt_ofs_shift_rpss) |
                 ((uint32_t)k_ra8_wdt_ofs_mask_rstirqs << k_ra8_wdt_ofs_shift_rstirqs) |
                 ((uint32_t)k_ra8_wdt_ofs_mask_stpctl << k_ra8_wdt_ofs_shift_stpctl)),
              "k_ra8_wdt_ofs_field_mask must equal the union of the seven WDT fields");

typedef struct {
  /* HUM Ch 27.2 "Register Descriptions" p 1256 */ /* + FSP R_WDT_Type                 */
  volatile uint8_t  WDTRR;                         
  volatile uint8_t  _r0;                           
  volatile uint16_t WDTCR;                         
  volatile uint16_t WDTSR;                         
  volatile uint8_t  WDTRCR;                        
  volatile uint8_t  _r1;                           
  volatile uint8_t  WDTCSTPR;                      
  volatile uint8_t  _r2;                           
  volatile uint16_t _r3;                           
} r_wdt_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_wdt_regs_t* ra8_wdt(void)
{
  /* HUM Ch 27.1 "Overview" p 1256 */
  return (volatile r_wdt_regs_t*)k_ra8_wdt_base_addr;
}

RA8_HW_REGISTER_ACCESS
static inline volatile r_wdt_regs_t* ra8_wdt_for(ra8_wdt_instance_t which)
{
  /* HUM Ch 27.1 "Overview" p 1256 */
  switch (which) {
    case k_ra8_wdt0:
      return (volatile r_wdt_regs_t*)k_ra8_wdt0_base_addr;
    case k_ra8_wdt1:
      return (volatile r_wdt_regs_t*)k_ra8_wdt1_base_addr;
    case k_ra8_wdt_instance_count:
    default:
      return (volatile r_wdt_regs_t*)k_ra8_wdt0_base_addr;
  }
}

static inline void ra8_wdt_refresh(void)
{
  /* HUM Ch 27.2.1 "WDTRR : WDT Refresh Register", p 1257 */
  volatile r_wdt_regs_t* w = ra8_wdt();
  w->WDTRR                 = k_ra8_wdt_refresh_a;
  w->WDTRR                 = k_ra8_wdt_refresh_b;
}

static inline void ra8_wdt_refresh_instance(ra8_wdt_instance_t which)
{
  /* HUM Ch 27.2.1 "WDTRR : WDT Refresh Register", p 1257 */
  volatile r_wdt_regs_t* w = ra8_wdt_for(which);
  w->WDTRR                 = k_ra8_wdt_refresh_a;
  w->WDTRR                 = k_ra8_wdt_refresh_b;
}
 
#ifdef __cplusplus
}
#endif