main.c

Go to the documentation of this file.

 
#include <stdint.h>
#include <string.h>
 
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_time.h"
 
/*
 * The host unit-test build (RA8_OFF_TARGET) does not link the
 * ThreadX / LevelX vendor trees, so `tx_api.h` and `lx_api.h` are
 * unreachable when clang-tidy walks this file. Pull them in only on
 * the cross-compile target.
 */
#ifndef RA8_OFF_TARGET
#include "lx_api.h"
#include "lx_nor_driver_ra8_xspi.h"
#include "tx_api.h"
#endif

typedef enum : uint32_t {
  k_lx_log_every_n = 100U, 
} lx_log_pace_t;
 
typedef enum : uint32_t {
  k_demo_baud = 115200U,

  k_demo_thread_stack = 4096U,

  k_demo_sector_index = 0U,

  k_demo_burnin_writes = 10000U,

  k_demo_tick_ms = 1000U,

  k_demo_sector_bytes = 512U,

  k_demo_radix_dec = 10U,

  k_demo_u32_buf_size = 12U,
} demo_config_t;
 
#ifndef RA8_OFF_TARGET
/* LevelX state. ThreadX requires statically-allocated control blocks
 * (NASA Power of 10 Rule 3 -- no dynamic memory). */
static LX_NOR_FLASH s_nor_flash;
 
/* LevelX logical-sector scratch buffer (512 bytes, ULONG-aligned). */
static ULONG s_demo_sector_io[k_demo_sector_bytes / sizeof(ULONG)];
 
/* ThreadX worker thread. */
static TX_THREAD s_demo_thread;
static UCHAR     s_demo_stack[k_demo_thread_stack];
#endif /* !RA8_OFF_TARGET */

static void demo_panic_halt(void)
{
  (void)ra8_board_uart_console_flush();
  while (1) {
    __asm__ volatile("wfi");
  }
}

static void demo_setup_or_halt(void)
{
  uint32_t cpuclk0_hz = 0U;
 
  if (ra8_cgc_init() != k_ra8_ok) {
    demo_panic_halt();
  }
  if (ra8_cgc_get_clock_hz(k_ra8_clock_id_cpuclk0, &cpuclk0_hz) != k_ra8_ok) {
    demo_panic_halt();
  }
  if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
    demo_panic_halt();
  }
  if (ra8_board_uart_console_init((uint32_t)k_demo_baud) != k_ra8_ok) {
    demo_panic_halt();
  }
}

static void demo_print(const char* s)
{
  if (s == (const char*)0) {
    return;
  }
  size_t len = strlen(s);
  (void)ra8_board_uart_console_write((const uint8_t*)s, len);
}

static void demo_print_u32(uint32_t value)
{
  /* Largest uint32_t = 4294967295 -> 10 chars + NUL. */
  char     buf[k_demo_u32_buf_size];
  uint32_t i = (uint32_t)sizeof(buf);
  buf[--i]   = '\0';
  if (value == 0U) {
    buf[--i] = '0';
  } else {
    while ((value != 0U) && (i > 0U)) {
      buf[--i] = (char)('0' + (value % k_demo_radix_dec));
      value /= k_demo_radix_dec;
    }
  }
  demo_print(&buf[i]);
}
 
#ifndef RA8_OFF_TARGET
static void demo_print_stat(const char* label, ULONG value)
{
  demo_print("  ");
  demo_print(label);
  demo_print(": ");
  demo_print_u32((uint32_t)value);
  demo_print("\r\n");
}

static void demo_lx_format_or_panic(void)
{
  static CHAR s_flash_name[] = "ra8_xspi_nor";
 
  UINT status =
    lx_nor_flash_format(&s_nor_flash, s_flash_name, lx_nor_driver_ra8_xspi_initialize, LX_NULL);
  if (status != LX_SUCCESS) {
    demo_print("[lx] format failed\r\n");
    demo_panic_halt();
  }
  status = lx_nor_flash_open(&s_nor_flash, s_flash_name, lx_nor_driver_ra8_xspi_initialize);
  if (status != LX_SUCCESS) {
    demo_print("[lx] open failed\r\n");
    demo_panic_halt();
  }
}

static UINT demo_heartbeat(uint32_t counter)
{
  /* Stamp the counter into the first ULONG of the scratch buffer. */
  s_demo_sector_io[0] = (ULONG)counter;
  UINT status =
    lx_nor_flash_sector_write(&s_nor_flash, (ULONG)k_demo_sector_index, &s_demo_sector_io[0]);
  if (status != LX_SUCCESS) {
    return status;
  }
  /* Wipe the buffer before read-back so we know the value really came
   * out of flash. */
  s_demo_sector_io[0] = 0U;
  status = lx_nor_flash_sector_read(&s_nor_flash, (ULONG)k_demo_sector_index, &s_demo_sector_io[0]);
  return status;
}

static void demo_print_wear_stats(void)
{
  demo_print("[lx] wear stats:\r\n");
  demo_print_stat("write_requests       ", s_nor_flash.lx_nor_flash_write_requests);
  demo_print_stat("read_requests        ", s_nor_flash.lx_nor_flash_read_requests);
  demo_print_stat("minimum_erase_count  ", s_nor_flash.lx_nor_flash_minimum_erase_count);
  demo_print_stat("maximum_erase_count  ", s_nor_flash.lx_nor_flash_maximum_erase_count);
  demo_print_stat("free_physical_sectors", s_nor_flash.lx_nor_flash_free_physical_sectors);
  demo_print_stat("mapped_phys_sectors  ", s_nor_flash.lx_nor_flash_mapped_physical_sectors);
  demo_print_stat("obsolete_phys_sectors", s_nor_flash.lx_nor_flash_obsolete_physical_sectors);
  demo_print_stat("phys_block_allocates ", s_nor_flash.lx_nor_flash_physical_block_allocates);
  demo_print_stat("sector_cache_hits    ", s_nor_flash.lx_nor_flash_sector_mapping_cache_hits);
  demo_print_stat("sector_cache_misses  ", s_nor_flash.lx_nor_flash_sector_mapping_cache_misses);
#ifndef LX_NOR_DISABLE_EXTENDED_CACHE
  demo_print_stat("extended_cache_hits  ", s_nor_flash.lx_nor_flash_extended_cache_hits);
  demo_print_stat("extended_cache_misses", s_nor_flash.lx_nor_flash_extended_cache_misses);
#endif
}

static void demo_report_rw_once(uint32_t counter, uint32_t readback)
{
  if (counter != 1U) {
    return;
  }
  if (readback == counter) {
    demo_print("[lx] sector rw verified readback=");
    demo_print_u32(readback);
    demo_print("\r\n");
  } else {
    demo_print("[lx] sector rw MISMATCH\r\n");
  }
}

static void demo_thread_entry(ULONG thread_input)
{
  (void)thread_input;
 
  demo_print("[lx] booting xSPI flash\r\n");
  /* The LevelX NOR driver owns OCTA bus bring-up: lx_nor_flash_format ->
   * lx_nor_driver_ra8_xspi_initialize -> priv_bus_init_once routes the
   * pins, runs the 8D/1S software-reset recovery, calls ra8_xspi_init,
   * and probes RDID exactly once. Doing it here as well double-routes
   * the PFS pins (the validator rejects the second route with
   * k_ra8_err_gpio_conflict), so the driver's initialize bails before
   * wiring the sector buffer and format returns LX_NO_MEMORY. Let the
   * driver be the single owner. */
  demo_print("[lx] formatting + opening LevelX partition\r\n");
  demo_lx_format_or_panic();
 
  demo_print("[lx] heartbeat begins\r\n");
  uint32_t counter = 0U;
  while (counter < (uint32_t)k_demo_burnin_writes) {
    counter++;
    UINT status = demo_heartbeat(counter);
    if (status != LX_SUCCESS) {
      demo_print("[lx] heartbeat I/O error at #");
      demo_print_u32(counter);
      demo_print("\r\n");
      break;
    }
    demo_report_rw_once(counter, (uint32_t)s_demo_sector_io[0]);
    /* Print every 100 cycles so the SCI8 stream stays readable. */
    if ((counter % k_lx_log_every_n) == 0U) {
      demo_print("[lx] cycle #");
      demo_print_u32(counter);
      demo_print(" readback=");
      demo_print_u32((uint32_t)s_demo_sector_io[0]);
      demo_print("\r\n");
    }
    /* Sleep ``k_demo_tick_ms`` between writes so a human can watch
     * the flash actually being beat on. ThreadX's tick rate is set by
     * ``port/threadx/inc/tx_user.h``; one tick is one millisecond at the
     * project default of ``TX_TIMER_TICKS_PER_SECOND = 1000``. */
    tx_thread_sleep((ULONG)k_demo_tick_ms);
  }
 
  demo_print("[lx] burn-in complete\r\n");
  demo_print_wear_stats();
 
  (void)lx_nor_flash_close(&s_nor_flash);
  demo_print("[lx] done\r\n");
}

void tx_application_define(void* first_unused_memory)
{
  static CHAR s_thread_name[] = "lx_demo";
 
  (void)first_unused_memory;
 
  lx_nor_flash_initialize();
 
  (void)tx_thread_create(&s_demo_thread,
                         s_thread_name,
                         demo_thread_entry,
                         0U,
                         s_demo_stack,
                         (ULONG)sizeof(s_demo_stack),
                         8U, /* priority          */
                         8U, /* preempt threshold */
                         TX_NO_TIME_SLICE,
                         TX_AUTO_START);
}
#endif /* !RA8_OFF_TARGET */

void main(void)
{
  demo_setup_or_halt();
  ra8_isr_globals_enable();
  demo_print("[lx] booting ThreadX + LevelX...\r\n");
 
#ifndef RA8_OFF_TARGET
  /* Hands control over to ThreadX permanently. */
  tx_kernel_enter();
#endif
 
  /* Should never return. */
  demo_panic_halt();
}