main.c File Reference

IIC_B peripheral-mode demo on EK-RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_i3c.h"
#include "ra8_isr.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Go to the source code of this file.

Enumerations
enum	iic_peripheral_const_t : uint32_t { k_iic_peripheral_period_ms = 1U }
	Demo tunables. More...
enum	iic_peripheral_layout_t : uint8_t {   k_iic_peripheral_channel = 0U ,   k_iic_peripheral_addr_7b = 0x42U }
	Channel + peripheral address. More...

Functions
static void	internal_iic_peripheral_panic_halt (void)
	Park the CPU after a fatal initialization or service failure.
static void	internal_iic_peripheral_setup_or_halt (void)
	Bring CGC + SysTick + LED1 + IIC_B peripheral up.
static ra8_err_t	internal_iic_peripheral_service (uint8_t *last_byte)
	Service one event from the peripheral status mask.
void	main (void)
	The application entry point Reset_Handler hands control to.

Detailed Description

IIC_B peripheral-mode demo on EK-RA8D2.

Tag

[Ring 6 / APP] {World: S}

Brings IIC_B0 up as a 7-bit-addressed peripheral at address 0x42, then loops:

1. Polls peripheral status, waiting for an Address-Matched (AAS) event.
2. On AAS + RDBFF0, drains a single byte from the controller.
3. On AAS + TDBEF0, pushes a one-byte response (echoing the previously received command byte).
4. Toggles LED1 on every successful transaction.

The demo is wired for an external IIC controller talking to the EK-RA8D2 (e.g. a Raspberry Pi as i2cset/i2cget); when no controller is attached the peripheral simply idles. There is no internal IIC loopback path on the RA8D2.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file main.c.

Enumeration Type Documentation

iic_peripheral_const_t

enum iic_peripheral_const_t : uint32_t

Demo tunables.

Enumerator
k_iic_peripheral_period_ms	Iic peripheral period ms.

Definition at line 39 of file main.c.

iic_peripheral_layout_t

enum iic_peripheral_layout_t : uint8_t

Channel + peripheral address.

Enumerator
k_iic_peripheral_channel	Iic peripheral channel.
k_iic_peripheral_addr_7b	Iic peripheral address 7b.

Definition at line 44 of file main.c.

Function Documentation

internal_iic_peripheral_panic_halt()

void internal_iic_peripheral_panic_halt ( void )

static

Park the CPU after a fatal initialization or service failure.

Enters a permanent wait-for-interrupt loop so peripheral state can be inspected without continuing with a partially initialized demo.

Precondition

Reset startup initialized the exception and stack environment.

The caller has determined that normal peripheral service cannot continue.

Postcondition

Control never returns to the caller.

No further IIC peripheral transactions are initiated by the application.

Note

An interrupt can wake one iteration, but the terminal loop resumes.

Since

0.1.0

Definition at line 60 of file main.c.

References RA8_INTERNAL.

Referenced by internal_iic_peripheral_setup_or_halt(), and main().

internal_iic_peripheral_service()

ra8_err_t internal_iic_peripheral_service ( uint8_t * last_byte )

staticnodiscard

Service one event from the peripheral status mask.

MC/DC:

Compound decision: (mask & rx_full) != 0 || (mask & tx_empty) != 0. Two atomic conditions x N+1 = 3 vectors – rx-only, tx-only, both; the host test exercises each independently by pre-loading the status mask before calling this function.

Parameters

[in,out]

last_byte

Latched controller-write byte; echoed back on the next controller-read.

Return values

k_ra8_ok	Event handled (or no event present).
k_ra8_err_hw_error	Underlying HAL surfaced an error.

Since

0.1.0

Definition at line 119 of file main.c.

References k_iic_peripheral_channel, k_ra8_board_led1, k_ra8_err_hw_error, k_ra8_i3c_peripheral_status_rx_full, k_ra8_i3c_peripheral_status_tx_empty, k_ra8_ok, ra8_board_led_toggle(), ra8_i3c_peripheral_receive(), ra8_i3c_peripheral_send(), ra8_i3c_peripheral_status(), and RA8_INTERNAL.

Referenced by main().

internal_iic_peripheral_setup_or_halt()

void internal_iic_peripheral_setup_or_halt ( void )

static

Bring CGC + SysTick + LED1 + IIC_B peripheral up.

Initializes the clock tree and timebase, prepares the observable LED, then opens channel zero at the fixed seven-bit peripheral address.

Precondition

Reset startup completed data and BSS initialization.

IIC_B channel zero and LED1 are not owned by another subsystem.

Postcondition

On return, timekeeping and LED1 are initialized and IIC_B accepts address 0x42.

Any failed prerequisite has entered the terminal panic loop.

Note

Single-shot boot helper; it is not reentrant.

Since

0.1.0

Definition at line 78 of file main.c.

References internal_iic_peripheral_panic_halt(), k_iic_peripheral_addr_7b, k_iic_peripheral_channel, k_ra8_board_led1, k_ra8_clock_id_cpuclk0, k_ra8_ok, ra8_board_led_init(), ra8_cgc_get_clock_hz(), ra8_cgc_init(), ra8_i3c_peripheral_open(), RA8_INTERNAL, and ra8_time_init().

Referenced by main().

main()

void main

(

void

)

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has configured the clock tree and VTOR.

Postcondition

Control does not return; the image runs until reset or halt.

Any value the application wanted to report has been logged, not returned.

Note

Not thread-safe; single-threaded startup context only.

Warning

Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also

SystemInit()

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the playback loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the sweep loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition

Reset_Handler has copied .data and zeroed .bss.

Postcondition

On clean entry the kernel runs the worker thread once.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the kernel runs the worker thread forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition

Reset_Handler has copied .data + zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

CPUCLK0 is raised to the PLL1 target before the kernel starts.

On clean entry the SD card thread runs forever.

On any HAL init failure the function halts in __WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the iso-IN feed loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition

Boot init has completed.

The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition

Diagnostic counter latched, CPU parked in a halt loop.

Function never returns.

Note

Single-threaded entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.

On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.

On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition

The shelf scans on the panel; taps open books, browse, and read.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the cache globals are latched and g_pc_heartbeat advances.

On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the profile + blink loop.

On any HAL hard error LED2 latches ON.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

The shared board boot files installed the vector table.

Postcondition

The demo has run once and its verdict banner is streaming steadily.

The CPU idles re-emitting the banner (or halts after a fatal init error).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On a clean run the CPU loops forever after the PASS banner.

On any failure the function prints FAIL and halts in WFI.

Note

Not thread-safe; this is the single-threaded app entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition

SystemInit configured VTOR / FPU / priority grouping.

The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition

Exactly one PASS or FAIL verdict line has been queued on SCI8.

Control parks in an infinite loop; the function never returns.

Note

Single-threaded; runs to the park loop on the main stack.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The page-count + render-hash banner is emitted; the CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The cal=OK / cal=SKIP result and the finger-free touchcal: ready sentinel are emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The open=OK touch banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Both USB controllers' clocks and pins come up before the kernel so the workers only deal with stack bring-up.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR, FPU, priority grouping.

Postcondition

On clean entry the CPU stays in tx_kernel_enter forever.

On any HAL init failure the function halts in WFI.

Note

Single entry point; not re-entrant.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging and the clock tree, releases the Cortex-M33 (which then blinks LED1 via ra8_pcntr_set_output()), and idles. See the file header.

Precondition

SystemInit has completed core bring-up.

The M33 is held in reset by hardware until released here.

Postcondition

The M33 has been released and is blinking LED1.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

The application links ra8_c6link and ESP-hosted generated codecs.

No hardware validation is inferred from this function.

Postcondition

No c6link operation is attempted.

No network or storage state is modified.

Note

Single-threaded compile fixture.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the cacheable-SRAM round-trip with the D-cache that SystemInit() enabled through ra8_cache_dcache_enable(), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU + RA8_BOOT_CACHE_VIA_HAL).

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit enabled the MPU + I-cache + D-cache via the ra8_cache HAL.

Postcondition

Exactly one banner (PASS or FAIL) has been emitted.

The core is parked in WFI.

Note

Single-threaded; no RTOS and no IRQ sources in this template.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, releases the Cortex-M33 into the emitter, yields until it signals done, validates the blob the M33 built, then logs the PASS/FAIL verdict and the chapter count read back from the blob. See the file header for the offload narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held inactive by hardware until released here.

Postcondition

The M33 has built a RABOOK1 blob and the M85 has validated it.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this example.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the CPU heartbeats after epaper: PASS.

On any HAL error the console prints epaper: FAIL and the red LED latches on.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The chapters/toc/cover banner is emitted; CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The reader loop runs forever, redrawing on each tap.

A page-1 banner is emitted once after the first render.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The cover-size / framebuffer-CRC banner is emitted; CPU loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The panel shows the reader screen and the input loop runs forever.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, arms the IPC0 wake and configures the LPM block, releases the Cortex-M33 into the reader, waits for the first held page, logs the page-0 verdict, then runs the #150 mode-switch cycle – parking in low-power WFI and waking on the M33's page-turn pokes – before logging the handoff verdict and parking for good. See the file header for the narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held inactive by hardware until released here.

Postcondition

The M33 has rendered + re-rendered the held page and the M85 is parked.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this example.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The boot banner is emitted; the reader loop services taps forever.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the timebase then measures forever.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the measure + blink loop forever.

On any HAL init failure the function halts in WFI.

Note

Never returns.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Arms the RIIC1 target and polls the dispatcher.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

The CPU stays in the dispatch poll loop forever.

On any fatal init error the CPU parks in riic_target_panic_halt.

Since

0.1.0

Definition at line 146 of file main.c.

References internal_iic_peripheral_panic_halt(), internal_iic_peripheral_service(), internal_iic_peripheral_setup_or_halt(), k_iic_peripheral_period_ms, k_ra8_ok, ra8_delay_ms(), and ra8_isr_globals_enable().