DMAC0 transfer peripheral-block model for the board emulator. More...

#include <stdint.h>
#include <stdio.h>
#include "board_console.h"
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

Include dependency graph for board_periph_dmac.c:

Data Structures
struct	dmac_chan_t
	One DMAC channel's modelled register shadow. More...

Enumerations
enum	dmac_console_t : uint32_t { k_dmac_console_line_cap = 48U }
	Console-tap line buffer capacity for a DMAC transfer summary. More...
enum	dmac_lit_t : uint32_t { k_u16_mask = 0xFFFFU }
	Field mask for the DMAC block-count register. More...
enum	dmac_order_t : uint32_t { k_dmac_block_order = 50U }
	Per-tick order slot for the DMAC / DTC windows. More...
enum	dmac_geom_t : uint64_t { k_dmac_base = 0x4000A000UL , k_dmac_stride = 0x40UL , k_dmac_count = 8UL , k_dmac_span = 0x40UL * 8UL }
	DMAC0 per-channel window geometry (ra8_dmac_regs.h). More...
enum	dma_shared_geom_t : uint64_t { k_dma_shared_base = 0x4000A800UL , k_dma_shared_span = 0xA0UL }
	Shared DMA module-control bank geometry (R_DMA at 0x4000A800). More...
enum	dmac_off_t : uint64_t { k_dmac_off_dmsar = 0x00UL , k_dmac_off_dmdar = 0x04UL , k_dmac_off_dmcra = 0x08UL , k_dmac_off_dmcrb = 0x0CUL , k_dmac_off_dmtmd = 0x10UL , k_dmac_off_dmint = 0x13UL , k_dmac_off_dmamd = 0x14UL , k_dmac_off_dmofr = 0x18UL , k_dmac_off_dmcnt = 0x1CUL , k_dmac_off_dmreq = 0x1DUL , k_dmac_off_dmsts = 0x1EUL }
	Per-channel register byte offsets (subset the driver touches). More...
enum	dmac_bit_t : uint8_t { k_dmac_dte_mask = 0x01U , k_dmac_swreq_mask = 0x01U , k_dmac_dtif_mask = 0x10U , k_dmac_act_mask = 0x80U }
	DMCNT / DMREQ / DMSTS bit masks (ra8_dmac_regs.h). More...
enum	dmac_sz_t : uint32_t { k_dmac_sz_pos = 8U , k_dmac_sz_mask = 0x3U , k_dmac_sz_byte = 0x0U , k_dmac_sz_half = 0x1U , k_dmac_sz_word = 0x2U , k_dmac_unit_byte = 1U , k_dmac_unit_half = 2U , k_dmac_unit_word = 4U }
	DMTMD.SZ transfer-width field (bits 8..9) and unit sizes. More...
enum	dmac_am_t : uint32_t { k_dmac_dm_pos = 6U , k_dmac_sm_pos = 14U , k_dmac_am_mask = 0x3U , k_dmac_am_incr = 0x2U }
	DMAMD address-update fields (ra8_dmac_regs.h). More...
enum	dmac_dmcra_t : uint32_t { k_dmac_dmcra_low_mask = 0x3FFU }
	DMCRA low half holds the running transfer count (bits 0..9). More...
enum	dmac_limit_t : uint32_t { k_dmac_max_units = 0x10000U }
	A bounded ceiling on units copied per trigger (safety net). More...
enum	dmac_event_t : uint16_t { k_dmac_event_ch0 = 0x0E0U }
	DMAC0 transfer-end ELC event the model emits (FSP ra8d2 bsp_elc). More...

Functions
static RA8_INTERNAL uint32_t	internal_dmac_unit_bytes (uint32_t sz_code)
	Bytes moved per unit for a DMTMD.SZ code (defaults to byte width).
static RA8_INTERNAL uint32_t	internal_dmac_total_units (const dmac_chan_t *c)
	Total units one software trigger transfers for channel `c`.
static RA8_INTERNAL void	internal_dmac_copy_units (uc_engine uc, dmac_chan_t c, uint32_t units, uint32_t unit)
	Copy `units` of `unit` bytes src->dst in emulated memory.
static RA8_INTERNAL void	internal_dmac_run_transfer (uc_engine *uc, uint32_t ch)
	Run one software-triggered transfer on channel `ch`.
static RA8_INTERNAL uint64_t	internal_dmac_reg_read (uint32_t ch, uint64_t off)
	Dispatch a DMAC channel register read for channel `ch`.
static RA8_INTERNAL void	internal_dmac_reg_store (dmac_chan_t *c, uint64_t off, uint32_t value)
	Apply a DMAC channel register write (non-trigger registers).
static RA8_INTERNAL void	internal_dmac_reg_write (uc_engine *uc, uint32_t ch, uint64_t off, uint32_t value)
	Dispatch a DMAC channel register write; DMREQ.SWREQ triggers a copy.
static RA8_INTERNAL uint64_t	internal_dmac_read (uc_engine *uc, uint64_t addr, unsigned size)
	MMIO read inside the DMAC0 channel window.
static RA8_INTERNAL void	internal_dmac_write (uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
	MMIO write inside the DMAC0 channel window.
static RA8_INTERNAL uint64_t	internal_shadow_read (const uint8_t *shadow, uint64_t span, uint64_t off, unsigned size)
	Read `size` bytes little-endian from a byte-array shadow.
static RA8_INTERNAL void	internal_shadow_write (uint8_t *shadow, uint64_t span, uint64_t off, unsigned size, uint64_t value)
	Write `size` bytes little-endian into a byte-array shadow.
static RA8_INTERNAL uint64_t	internal_dma_shared_read (uc_engine *uc, uint64_t addr, unsigned size)
	MMIO read inside the shared DMA module-control bank.
static RA8_INTERNAL void	internal_dma_shared_write (uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
	MMIO write inside the shared DMA module-control bank.
static RA8_INTERNAL void	internal_dmac_reset (void)
	Clear all DMAC channel state plus the shared module-control shadow.
static RA8_INTERNAL void	internal_dmac_report (void)
	Print one line per DMAC channel that completed any transfer.
static RA8_INTERNAL void	internal_board_periph_dmac_register (void)
	Self-register the DMAC0 / shared module-control windows before main.

Variables
static dmac_chan_t	s_dmac [k_dmac_count]
static uint8_t	s_dma_shared [k_dma_shared_span]
	Shared DMA module-control bank shadow (DMAST / DMCTL / DELSR).
static const board_periph_block_t	s_k_dmac_block
	DMAC0 channel window + the combined reset / report.
static const board_periph_block_t	s_k_dma_shared_block
	Shared DMA module-control bank window (transparent shadow).

Detailed Description

DMAC0 transfer peripheral-block model for the board emulator.

Models the RA8D2 Direct Memory Access Controller (DMAC0) closely enough that a software-triggered block copy actually MOVES bytes in emulated memory, so an example such as dma_memcopy_demo – which programmes a channel, fires a software request, then verifies the destination buffer equals the source – passes its dst==src check against real data rather than a faked handshake.

DMAC0 (ra8_dmac_regs.h, ra8_dmac.c): eight channels at 0x4000A000, 0x40 bytes apart. The driver writes DMSAR (source), DMDAR (destination), DMCRA (transfer count – low half is the running count), DMTMD (SZ = transfer width), DMAMD (SM/DM = source/dest address update mode) and arms the channel with DMCNT.DTE. A write to DMREQ.SWREQ on an armed channel is the software trigger: the model reads the channel's programmed source/destination/width/increment out of its own register shadow and copies the configured number of units between the two emulated addresses with uc_mem_read / uc_mem_write, advancing each address by the unit size when its increment mode says so. It then drains DMCRA to zero, latches DMSTS.DTIF, clears DMSTS.ACT (the transfer is synchronous in the model, so the demo's "poll ACT until idle" gate falls straight through), auto-clears SWREQ, and – if DMINT.DTIE is set – raises the channel's transfer-end ELC event through the core's ICU -> NVIC path so an interrupt-driven transfer also works.

The DTC (Data Transfer Controller, ra8_dtc_regs.h) shares MSTPA22 with DMAC0 but is modelled in its own file (board_periph_dtc.c), which owns the DTC control window (0x4000AC00) and the ELC software-event activation path.

The shared DMA module-control bank (DMAST activation gate, DMCTL, DELSR ELC links) at 0x4000A800 is a second window, a transparent shadow: the driver sets DMAST.DMST before the per-channel DTE write, and the model honours the readback. The two DMAC windows register two block descriptors with the core; the per-channel transfer state and the shared registers all reset together from the channel descriptor's reset hook.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file board_periph_dmac.c.

Enumeration Type Documentation

◆ dma_shared_geom_t

enum dma_shared_geom_t : uint64_t

Shared DMA module-control bank geometry (R_DMA at 0x4000A800).

Enumerator
k_dma_shared_base	DMAST / DMCTL / DMECHR / DELSR.
k_dma_shared_span	FSP R_DMA_Type size.

Definition at line 83 of file board_periph_dmac.c.

◆ dmac_am_t

enum dmac_am_t : uint32_t

DMAMD address-update fields (ra8_dmac_regs.h).

Enumerator
k_dmac_dm_pos	DMAMD.DM destination-update position.
k_dmac_sm_pos	DMAMD.SM source-update position.
k_dmac_am_mask	Address-update field width (2 bits).
k_dmac_am_incr	10b: increment after each unit.

Definition at line 124 of file board_periph_dmac.c.

◆ dmac_bit_t

enum dmac_bit_t : uint8_t

DMCNT / DMREQ / DMSTS bit masks (ra8_dmac_regs.h).

Enumerator
k_dmac_dte_mask	DMCNT.DTE channel-enable.
k_dmac_swreq_mask	DMREQ.SWREQ software request.
k_dmac_dtif_mask	DMSTS.DTIF transfer-end flag.
k_dmac_act_mask	DMSTS.ACT active flag.

Definition at line 104 of file board_periph_dmac.c.

◆ dmac_console_t

enum dmac_console_t : uint32_t

Console-tap line buffer capacity for a DMAC transfer summary.

Enumerator
k_dmac_console_line_cap	Max chars in a "DMAC.. .. units" line.

Definition at line 52 of file board_periph_dmac.c.

◆ dmac_dmcra_t

enum dmac_dmcra_t : uint32_t

DMCRA low half holds the running transfer count (bits 0..9).

Enumerator
k_dmac_dmcra_low_mask	DMCRA.DMCRAL count field.

Definition at line 132 of file board_periph_dmac.c.

◆ dmac_event_t

enum dmac_event_t : uint16_t

DMAC0 transfer-end ELC event the model emits (FSP ra8d2 bsp_elc).

The RA8D2 ELC signal table (HUM Ch 19) places the DMAC0 channel-0 transfer interrupt (DMAC0_INT) at 0x0E0; FSP bsp_elc.h lists the eight DMAC channel events contiguously from there. A firmware that routes the channel's transfer-end interrupt through ra8_isr_register writes the matching number into an IELSR slot, so the ICU model links the raised event to that slot.

Enumerator
k_dmac_event_ch0	DMAC0 channel-0 transfer-end event.

Definition at line 151 of file board_periph_dmac.c.

◆ dmac_geom_t

enum dmac_geom_t : uint64_t

DMAC0 per-channel window geometry (ra8_dmac_regs.h).

Enumerator
k_dmac_base	DMAC0 channel 0 base.
k_dmac_stride	Bytes per DMAC channel.
k_dmac_count	DMAC0 channel 0..7.
k_dmac_span	DMAC span.

Definition at line 75 of file board_periph_dmac.c.

◆ dmac_limit_t

enum dmac_limit_t : uint32_t

A bounded ceiling on units copied per trigger (safety net).

Enumerator
k_dmac_max_units	Largest one-trigger unit count.

Definition at line 137 of file board_periph_dmac.c.

◆ dmac_lit_t

enum dmac_lit_t : uint32_t

Field mask for the DMAC block-count register.

Enumerator
k_u16_mask	U16 mask.

Definition at line 57 of file board_periph_dmac.c.

◆ dmac_off_t

enum dmac_off_t : uint64_t

Per-channel register byte offsets (subset the driver touches).

Enumerator
k_dmac_off_dmsar	Source address (32-bit).
k_dmac_off_dmdar	Destination address (32-bit).
k_dmac_off_dmcra	Transfer count (low/high halves).
k_dmac_off_dmcrb	Block transfer count.
k_dmac_off_dmtmd	Transfer mode (SZ / MD / DTS).
k_dmac_off_dmint	Interrupt setting (DTIE et al.).
k_dmac_off_dmamd	Address mode (SM / DM).
k_dmac_off_dmofr	Offset register.
k_dmac_off_dmcnt	Transfer enable (DTE bit0).
k_dmac_off_dmreq	Software start (SWREQ / CLRS).
k_dmac_off_dmsts	Status (ESIF / DTIF / ACT).

Definition at line 89 of file board_periph_dmac.c.

◆ dmac_order_t

enum dmac_order_t : uint32_t

Per-tick order slot for the DMAC / DTC windows.

These blocks have no tick, so their order only affects reset / report sequencing. The value sits above the existing board_periph_block_order_t slots (gpio 10, timer 20, sci 30, i2c 40) with spacing to spare, so the DMAC summary prints after the existing peripheral sections without renumbering them – and without editing the shared header the conflict-free rule forbids touching.

Enumerator
k_dmac_block_order	DMAC / DMA / DTC reset+report order slot.

Definition at line 70 of file board_periph_dmac.c.

◆ dmac_sz_t

enum dmac_sz_t : uint32_t

DMTMD.SZ transfer-width field (bits 8..9) and unit sizes.

Enumerator
k_dmac_sz_pos	DMTMD.SZ field position.
k_dmac_sz_mask	DMTMD.SZ field width (2 bits).
k_dmac_sz_byte	00b: 8-bit unit.
k_dmac_sz_half	01b: 16-bit unit.
k_dmac_sz_word	10b: 32-bit unit.
k_dmac_unit_byte	Bytes moved per byte-width unit.
k_dmac_unit_half	Bytes moved per half-width unit.
k_dmac_unit_word	Bytes moved per word-width unit.

Definition at line 112 of file board_periph_dmac.c.

Function Documentation

◆ internal_board_periph_dmac_register()

RA8_INTERNAL void internal_board_periph_dmac_register ( void )

static

Self-register the DMAC0 / shared module-control windows before main.

Definition at line 656 of file board_periph_dmac.c.

References board_periph_register_block(), RA8_INTERNAL, s_k_dma_shared_block, and s_k_dmac_block.

◆ internal_dma_shared_read()

RA8_INTERNAL uint64_t internal_dma_shared_read	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size )

static

MMIO read inside the shared DMA module-control bank.

MMIO read inside the shared dma module-control bank; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.

Returns: The DMA shared read result produced by the board periph DMA controller model.

Return values

value The operation-specific DMA shared read value.

Precondition: Arguments satisfy the ranges documented for DMA shared read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 548 of file board_periph_dmac.c.

References internal_shadow_read(), k_dma_shared_base, k_dma_shared_span, RA8_INTERNAL, and s_dma_shared.

◆ internal_dma_shared_write()

RA8_INTERNAL void internal_dma_shared_write	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size,
		uint64_t	value )

static

MMIO write inside the shared DMA module-control bank.

MMIO write inside the shared dma module-control bank; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for DMA shared write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 570 of file board_periph_dmac.c.

References internal_shadow_write(), k_dma_shared_base, k_dma_shared_span, and s_dma_shared.

◆ internal_dmac_copy_units()

RA8_INTERNAL void internal_dmac_copy_units	(	uc_engine *	uc,
		dmac_chan_t *	c,
		uint32_t	units,
		uint32_t	unit )

static

Copy units of unit bytes src->dst in emulated memory.

Copy units of unit bytes src->dst in emulated memory; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in,out]	c	Active controller, card, or command state processed by the operation.
[in]	units	Units input used by the operation.
[in]	unit	Unit input used by the operation.

Precondition: Arguments satisfy the ranges documented for DMA controller copy units.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 244 of file board_periph_dmac.c.

References dmac_chan_t::dmamd, dmac_chan_t::dmdar, dmac_chan_t::dmsar, emu_mem_read(), emu_mem_write(), k_dmac_am_incr, k_dmac_am_mask, k_dmac_dm_pos, k_dmac_sm_pos, k_dmac_unit_word, and dmac_chan_t::units.

Referenced by internal_dmac_run_transfer().

◆ internal_dmac_read()

RA8_INTERNAL uint64_t internal_dmac_read	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size )

static

MMIO read inside the DMAC0 channel window.

MMIO read inside the dmac0 channel window; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.

Returns: The DMA controller read result produced by the board periph DMA controller model.

Return values

value The operation-specific DMA controller read value.

Precondition: Arguments satisfy the ranges documented for DMA controller read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 448 of file board_periph_dmac.c.

References internal_dmac_reg_read(), k_dmac_base, k_dmac_stride, and RA8_INTERNAL.

◆ internal_dmac_reg_read()

RA8_INTERNAL uint64_t internal_dmac_reg_read	(	uint32_t	ch,
		uint64_t	off )

static

Dispatch a DMAC channel register read for channel ch.

Dispatch a dmac channel register read for channel ch; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in]	ch	Selected channel identifier.
[in]	off	Register or byte offset addressed by the operation.

Returns: The DMA controller reg read result produced by the board periph DMA controller model.

Return values

value The operation-specific DMA controller reg read value.

Precondition: Arguments satisfy the ranges documented for DMA controller reg read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 332 of file board_periph_dmac.c.

References dmac_chan_t::dmamd, dmac_chan_t::dmcnt, dmac_chan_t::dmcra, dmac_chan_t::dmcrb, dmac_chan_t::dmdar, dmac_chan_t::dmint, dmac_chan_t::dmofr, dmac_chan_t::dmsar, dmac_chan_t::dmsts, dmac_chan_t::dmtmd, k_dmac_off_dmamd, k_dmac_off_dmcnt, k_dmac_off_dmcra, k_dmac_off_dmcrb, k_dmac_off_dmdar, k_dmac_off_dmint, k_dmac_off_dmofr, k_dmac_off_dmsar, k_dmac_off_dmsts, k_dmac_off_dmtmd, RA8_INTERNAL, and s_dmac.

Referenced by internal_dmac_read().

◆ internal_dmac_reg_store()

RA8_INTERNAL void internal_dmac_reg_store	(	dmac_chan_t *	c,
		uint64_t	off,
		uint32_t	value )

static

Apply a DMAC channel register write (non-trigger registers).

Apply a dmac channel register write (non-trigger registers); this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	c	Active controller, card, or command state processed by the operation.
[in]	off	Register or byte offset addressed by the operation.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for DMA controller reg store.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 372 of file board_periph_dmac.c.

References dmac_chan_t::dmamd, dmac_chan_t::dmcnt, dmac_chan_t::dmcra, dmac_chan_t::dmcrb, dmac_chan_t::dmdar, dmac_chan_t::dmint, dmac_chan_t::dmofr, dmac_chan_t::dmsar, dmac_chan_t::dmsts, dmac_chan_t::dmtmd, k_dmac_off_dmamd, k_dmac_off_dmcnt, k_dmac_off_dmcra, k_dmac_off_dmcrb, k_dmac_off_dmdar, k_dmac_off_dmint, k_dmac_off_dmofr, k_dmac_off_dmsar, k_dmac_off_dmsts, k_dmac_off_dmtmd, and RA8_INTERNAL.

Referenced by internal_dmac_reg_write().

◆ internal_dmac_reg_write()

RA8_INTERNAL void internal_dmac_reg_write	(	uc_engine *	uc,
		uint32_t	ch,
		uint64_t	off,
		uint32_t	value )

static

Dispatch a DMAC channel register write; DMREQ.SWREQ triggers a copy.

Dispatch a dmac channel register write; dmreq.swreq triggers a copy; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	ch	Selected channel identifier.
[in]	off	Register or byte offset addressed by the operation.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for DMA controller reg write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 424 of file board_periph_dmac.c.

References internal_dmac_reg_store(), internal_dmac_run_transfer(), k_dmac_off_dmreq, k_dmac_swreq_mask, and s_dmac.

Referenced by internal_dmac_write().

◆ internal_dmac_report()

RA8_INTERNAL void internal_dmac_report ( void )

static

Print one line per DMAC channel that completed any transfer.

Print one line per dmac channel that completed any transfer; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Precondition: Arguments satisfy the ranges documented for DMA controller report.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 611 of file board_periph_dmac.c.

References k_dmac_count, priv_emu_io_errf(), RA8_INTERNAL, and s_dmac.

◆ internal_dmac_reset()

RA8_INTERNAL void internal_dmac_reset ( void )

static

Clear all DMAC channel state plus the shared module-control shadow.

Clear all dmac channel state plus the shared module-control shadow; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Precondition: Arguments satisfy the ranges documented for DMA controller reset.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 593 of file board_periph_dmac.c.

References k_dma_shared_span, k_dmac_count, RA8_INTERNAL, s_dma_shared, and s_dmac.

◆ internal_dmac_run_transfer()

RA8_INTERNAL void internal_dmac_run_transfer	(	uc_engine *	uc,
		uint32_t	ch )

static

Run one software-triggered transfer on channel ch.

Run one software-triggered transfer on channel ch; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	ch	Selected channel identifier.

Precondition: Arguments satisfy the ranges documented for DMA controller run transfer.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 282 of file board_periph_dmac.c.

References board_console_push(), board_periph_icu_raise_event(), board_periph_trace(), dmac_chan_t::copies, dmac_chan_t::dmcnt, dmac_chan_t::dmcra, dmac_chan_t::dmint, dmac_chan_t::dmsts, dmac_chan_t::dmtmd, internal_dmac_copy_units(), internal_dmac_total_units(), internal_dmac_unit_bytes(), k_board_console_ch_dma, k_dmac_act_mask, k_dmac_console_line_cap, k_dmac_dmcra_low_mask, k_dmac_dte_mask, k_dmac_dtif_mask, k_dmac_event_ch0, k_dmac_sz_mask, k_dmac_sz_pos, priv_emu_io_errf(), RA8_INTERNAL, s_dmac, and dmac_chan_t::units.

Referenced by internal_dmac_reg_write().

◆ internal_dmac_total_units()

RA8_INTERNAL uint32_t internal_dmac_total_units ( const dmac_chan_t * c )

static

Total units one software trigger transfers for channel c.

Total units one software trigger transfers for channel c; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in] c Active controller, card, or command state processed by the operation.

Returns: The DMA controller total units result produced by the board periph DMA controller model.

Return values

value The operation-specific DMA controller total units value.

Precondition: Arguments satisfy the ranges documented for DMA controller total units.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 214 of file board_periph_dmac.c.

References dmac_chan_t::dmcra, dmac_chan_t::dmcrb, k_dmac_dmcra_low_mask, k_dmac_max_units, k_u16_mask, and RA8_INTERNAL.

Referenced by internal_dmac_run_transfer().

◆ internal_dmac_unit_bytes()

RA8_INTERNAL uint32_t internal_dmac_unit_bytes ( uint32_t sz_code )

static

Bytes moved per unit for a DMTMD.SZ code (defaults to byte width).

Bytes moved per unit for a dmtmd.sz code (defaults to byte width); this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in] sz_code Sz code input used by the operation.

Returns: The DMA controller unit bytes result produced by the board periph DMA controller model.

Return values

value The operation-specific DMA controller unit bytes value.

Precondition: Arguments satisfy the ranges documented for DMA controller unit bytes.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 192 of file board_periph_dmac.c.

References k_dmac_sz_half, k_dmac_sz_word, k_dmac_unit_byte, k_dmac_unit_half, k_dmac_unit_word, and RA8_INTERNAL.

Referenced by internal_dmac_run_transfer().

◆ internal_dmac_write()

RA8_INTERNAL void internal_dmac_write	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size,
		uint64_t	value )

static

MMIO write inside the DMAC0 channel window.

MMIO write inside the dmac0 channel window; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for DMA controller write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 469 of file board_periph_dmac.c.

References internal_dmac_reg_write(), k_dmac_base, and k_dmac_stride.

◆ internal_shadow_read()

RA8_INTERNAL uint64_t internal_shadow_read	(	const uint8_t *	shadow,
		uint64_t	span,
		uint64_t	off,
		unsigned	size )

static

Read size bytes little-endian from a byte-array shadow.

Read size bytes little-endian from a byte-array shadow; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in]	shadow	Shadow input used by the operation.
[in]	span	Bounded address span covered by the operation.
[in]	off	Register or byte offset addressed by the operation.
[in]	size	Size of the requested region or access in bytes.

Returns: The shadow read result produced by the board periph DMA controller model.

Return values

value The operation-specific shadow read value.

Precondition: Arguments satisfy the ranges documented for shadow read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 499 of file board_periph_dmac.c.

Referenced by internal_dma_shared_read().

◆ internal_shadow_write()

RA8_INTERNAL void internal_shadow_write	(	uint8_t *	shadow,
		uint64_t	span,
		uint64_t	off,
		unsigned	size,
		uint64_t	value )

static

Write size bytes little-endian into a byte-array shadow.

Write size bytes little-endian into a byte-array shadow; this step is contained within the board periph DMA controller model and uses bounded caller or module-owned storage.

Parameters

[in,out]	shadow	Shadow state or storage updated in place by the operation.
[in]	span	Bounded address span covered by the operation.
[in]	off	Register or byte offset addressed by the operation.
[in]	size	Size of the requested region or access in bytes.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for shadow write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph DMA controller model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 525 of file board_periph_dmac.c.

Referenced by internal_dma_shared_write().

Variable Documentation

◆ s_dma_shared

uint8_t s_dma_shared[k_dma_shared_span]

static

Shared DMA module-control bank shadow (DMAST / DMCTL / DELSR).

Definition at line 174 of file board_periph_dmac.c.

Referenced by internal_dma_shared_read(), internal_dma_shared_write(), and internal_dmac_reset().

◆ s_dmac

dmac_chan_t s_dmac[k_dmac_count]

static

Definition at line 171 of file board_periph_dmac.c.

Referenced by internal_dmac_reg_read(), internal_dmac_reg_write(), internal_dmac_report(), internal_dmac_reset(), and internal_dmac_run_transfer().

◆ s_k_dma_shared_block

const board_periph_block_t s_k_dma_shared_block

static

Initial value:

                                                       = {
  .base   = (uint64_t)k_dma_shared_base,
  .span   = (uint64_t)k_dma_shared_span,
  .order  = (uint32_t)k_dmac_block_order,
  .read   = internal_dma_shared_read,
  .write  = internal_dma_shared_write,
  .tick   = nullptr,
  .reset  = nullptr,
  .report = nullptr,
  .name   = "DMA",
}

Shared DMA module-control bank window (transparent shadow).

Definition at line 643 of file board_periph_dmac.c.

Referenced by internal_board_periph_dmac_register().

◆ s_k_dmac_block

const board_periph_block_t s_k_dmac_block

static

Initial value:

                                                 = {
  .base   = (uint64_t)k_dmac_base,
  .span   = (uint64_t)k_dmac_span,
  .order  = (uint32_t)k_dmac_block_order,
  .read   = internal_dmac_read,
  .write  = internal_dmac_write,
  .tick   = nullptr,
  .reset  = internal_dmac_reset,
  .report = internal_dmac_report,
  .name   = "DMAC",
}

DMAC0 channel window + the combined reset / report.

Definition at line 630 of file board_periph_dmac.c.

Referenced by internal_board_periph_dmac_register().

Data Structures

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ dma_shared_geom_t

◆ dmac_am_t

◆ dmac_bit_t

◆ dmac_console_t

◆ dmac_dmcra_t

◆ dmac_event_t

◆ dmac_geom_t

◆ dmac_limit_t

◆ dmac_lit_t

◆ dmac_off_t

◆ dmac_order_t

◆ dmac_sz_t

Function Documentation

◆ internal_board_periph_dmac_register()

◆ internal_dma_shared_read()

◆ internal_dma_shared_write()

◆ internal_dmac_copy_units()

◆ internal_dmac_read()

◆ internal_dmac_reg_read()

◆ internal_dmac_reg_store()

◆ internal_dmac_reg_write()

◆ internal_dmac_report()

◆ internal_dmac_reset()

◆ internal_dmac_run_transfer()

◆ internal_dmac_total_units()

◆ internal_dmac_unit_bytes()

◆ internal_dmac_write()

◆ internal_shadow_read()

◆ internal_shadow_write()

Variable Documentation

◆ s_dma_shared

◆ s_dmac

◆ s_k_dma_shared_block

◆ s_k_dmac_block