board_periph_dmac.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_console.h"
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

typedef enum : uint32_t {
  k_dmac_console_line_cap = 48U, 
} dmac_console_t;

typedef enum : uint32_t { k_u16_mask = 0xFFFFU  } dmac_lit_t;

typedef enum : uint32_t {
  k_dmac_block_order = 50U, 
} dmac_order_t;

typedef enum : uint64_t {
  k_dmac_base   = 0x4000A000UL, 
  k_dmac_stride = 0x40UL,       
  k_dmac_count  = 8UL,          
  k_dmac_span   = 0x40UL * 8UL, 
} dmac_geom_t;

typedef enum : uint64_t {
  k_dma_shared_base = 0x4000A800UL, 
  k_dma_shared_span = 0xA0UL,       
} dma_shared_geom_t;

typedef enum : uint64_t {
  k_dmac_off_dmsar = 0x00UL, 
  k_dmac_off_dmdar = 0x04UL, 
  k_dmac_off_dmcra = 0x08UL, 
  k_dmac_off_dmcrb = 0x0CUL, 
  k_dmac_off_dmtmd = 0x10UL, 
  k_dmac_off_dmint = 0x13UL, 
  k_dmac_off_dmamd = 0x14UL, 
  k_dmac_off_dmofr = 0x18UL, 
  k_dmac_off_dmcnt = 0x1CUL, 
  k_dmac_off_dmreq = 0x1DUL, 
  k_dmac_off_dmsts = 0x1EUL, 
} dmac_off_t;

typedef enum : uint8_t {
  k_dmac_dte_mask   = 0x01U, 
  k_dmac_swreq_mask = 0x01U, 
  k_dmac_dtif_mask  = 0x10U, 
  k_dmac_act_mask   = 0x80U, 
} dmac_bit_t;

typedef enum : uint32_t {
  k_dmac_sz_pos    = 8U,   
  k_dmac_sz_mask   = 0x3U, 
  k_dmac_sz_byte   = 0x0U, 
  k_dmac_sz_half   = 0x1U, 
  k_dmac_sz_word   = 0x2U, 
  k_dmac_unit_byte = 1U,   
  k_dmac_unit_half = 2U,   
  k_dmac_unit_word = 4U,   
} dmac_sz_t;

typedef enum : uint32_t {
  k_dmac_dm_pos  = 6U,   
  k_dmac_sm_pos  = 14U,  
  k_dmac_am_mask = 0x3U, 
  k_dmac_am_incr = 0x2U, 
} dmac_am_t;

typedef enum : uint32_t {
  k_dmac_dmcra_low_mask = 0x3FFU, 
} dmac_dmcra_t;

typedef enum : uint32_t {
  k_dmac_max_units = 0x10000U, 
} dmac_limit_t;

typedef enum : uint16_t {
  k_dmac_event_ch0 = 0x0E0U, 
} dmac_event_t;

typedef struct {
  uint32_t dmsar;  
  uint32_t dmdar;  
  uint32_t dmcra;  
  uint32_t dmcrb;  
  uint32_t dmofr;  
  uint16_t dmtmd;  
  uint16_t dmamd;  
  uint8_t  dmint;  
  uint8_t  dmcnt;  
  uint8_t  dmsts;  
  uint32_t copies; 
  uint32_t units;  
} dmac_chan_t;
 
static dmac_chan_t s_dmac[k_dmac_count];

static uint8_t s_dma_shared[k_dma_shared_span];
 
/* =============================================================================
 * DMAC channel transfer primitive (the part that actually moves memory).
 * =============================================================================
 */

RA8_INTERNAL static uint32_t internal_dmac_unit_bytes(uint32_t sz_code)
{
  if (sz_code == (uint32_t)k_dmac_sz_word) {
    return (uint32_t)k_dmac_unit_word;
  }
  if (sz_code == (uint32_t)k_dmac_sz_half) {
    return (uint32_t)k_dmac_unit_half;
  }
  return (uint32_t)k_dmac_unit_byte;
}

RA8_INTERNAL static uint32_t internal_dmac_total_units(const dmac_chan_t* c)
{
  uint32_t count = c->dmcra & (uint32_t)k_dmac_dmcra_low_mask;
  if (count == 0U) {
    count = (uint32_t)k_dmac_dmcra_low_mask + 1U; /* DMCRAL==0 means 1024 units */
  }
  uint32_t blocks = c->dmcrb & (uint32_t)k_u16_mask;
  if (blocks == 0U) {
    blocks = 1U; /* normal mode: a single block of `count` units */
  }
  uint64_t total = (uint64_t)count * (uint64_t)blocks;
  if (total > (uint64_t)k_dmac_max_units) {
    total = (uint64_t)k_dmac_max_units;
  }
  return (uint32_t)total;
}

RA8_INTERNAL static void
internal_dmac_copy_units(uc_engine* uc, dmac_chan_t* c, uint32_t units, uint32_t unit)
{
  uint64_t       src     = (uint64_t)c->dmsar;
  uint64_t       dst     = (uint64_t)c->dmdar;
  const uint32_t sm      = (c->dmamd >> (uint32_t)k_dmac_sm_pos) & (uint32_t)k_dmac_am_mask;
  const uint32_t dm      = (c->dmamd >> (uint32_t)k_dmac_dm_pos) & (uint32_t)k_dmac_am_mask;
  const bool     src_inc = (sm == (uint32_t)k_dmac_am_incr);
  const bool     dst_inc = (dm == (uint32_t)k_dmac_am_incr);
  uint8_t        word[k_dmac_unit_word] = {};
  for (uint32_t i = 0U; i < units; i++) {
    if (emu_mem_read(uc, src, word, unit) != UC_ERR_OK) {
      break;
    }
    if (emu_mem_write(uc, dst, word, unit) != UC_ERR_OK) {
      break;
    }
    if (src_inc) {
      src += unit;
    }
    if (dst_inc) {
      dst += unit;
    }
    c->units++;
  }
  c->dmsar = (uint32_t)src;
  c->dmdar = (uint32_t)dst;
}

RA8_INTERNAL static void internal_dmac_run_transfer(uc_engine* uc, uint32_t ch)
{
  dmac_chan_t* c = &s_dmac[ch];
  if ((c->dmcnt & (uint8_t)k_dmac_dte_mask) == 0U) {
    return; /* channel disarmed: SWREQ does nothing */
  }
  const uint32_t sz    = (c->dmtmd >> (uint32_t)k_dmac_sz_pos) & (uint32_t)k_dmac_sz_mask;
  const uint32_t unit  = internal_dmac_unit_bytes(sz);
  const uint32_t units = internal_dmac_total_units(c);
  c->units             = 0U;
  internal_dmac_copy_units(uc, c, units, unit);
  c->dmcra &= ~(uint32_t)k_dmac_dmcra_low_mask; /* count drained to zero        */
  c->dmsts &= (uint8_t)~k_dmac_act_mask;        /* synchronous: idle after copy */
  c->dmsts |= (uint8_t)k_dmac_dtif_mask;        /* transfer-end status latched  */
  c->copies++;
  /* Console DMA tab: one line per completed DMAC transfer (not per unit). */
  char ln[k_dmac_console_line_cap];
  (void)snprintf(ln,
                 sizeof(ln),
                 "DMAC%u %u units x %uB",
                 (unsigned)ch,
                 (unsigned)c->units,
                 (unsigned)unit);
  board_console_push(k_board_console_ch_dma, ln);
  if (board_periph_trace()) {
    (void)
      priv_emu_io_errf("  DMAC%u         : copied %u units x %uB (SWREQ)\n", ch, c->units, unit);
  }
  if ((c->dmint & (uint8_t)k_dmac_dtif_mask) != 0U) {
    board_periph_icu_raise_event(uc, (uint16_t)((uint16_t)k_dmac_event_ch0 + (uint16_t)ch));
  }
}
 
/* =============================================================================
 * DMAC0 per-channel MMIO.
 * =============================================================================
 */

RA8_INTERNAL static uint64_t internal_dmac_reg_read(uint32_t ch, uint64_t off)
{
  const dmac_chan_t* c = &s_dmac[ch];
  switch (off) {
    case (uint64_t)k_dmac_off_dmsar:
      return c->dmsar;
    case (uint64_t)k_dmac_off_dmdar:
      return c->dmdar;
    case (uint64_t)k_dmac_off_dmcra:
      return c->dmcra;
    case (uint64_t)k_dmac_off_dmcrb:
      return c->dmcrb;
    case (uint64_t)k_dmac_off_dmtmd:
      return c->dmtmd;
    case (uint64_t)k_dmac_off_dmamd:
      return c->dmamd;
    case (uint64_t)k_dmac_off_dmofr:
      return c->dmofr;
    case (uint64_t)k_dmac_off_dmint:
      return c->dmint;
    case (uint64_t)k_dmac_off_dmcnt:
      return c->dmcnt;
    case (uint64_t)k_dmac_off_dmsts:
      return c->dmsts;
    default:
      return 0U;
  }
}

RA8_INTERNAL static void internal_dmac_reg_store(dmac_chan_t* c, uint64_t off, uint32_t value)
{
  switch (off) {
    case (uint64_t)k_dmac_off_dmsar:
      c->dmsar = value;
      break;
    case (uint64_t)k_dmac_off_dmdar:
      c->dmdar = value;
      break;
    case (uint64_t)k_dmac_off_dmcra:
      c->dmcra = value;
      break;
    case (uint64_t)k_dmac_off_dmcrb:
      c->dmcrb = value;
      break;
    case (uint64_t)k_dmac_off_dmtmd:
      c->dmtmd = (uint16_t)value;
      break;
    case (uint64_t)k_dmac_off_dmamd:
      c->dmamd = (uint16_t)value;
      break;
    case (uint64_t)k_dmac_off_dmofr:
      c->dmofr = value;
      break;
    case (uint64_t)k_dmac_off_dmint:
      c->dmint = (uint8_t)value;
      break;
    case (uint64_t)k_dmac_off_dmcnt:
      c->dmcnt = (uint8_t)value;
      break;
    case (uint64_t)k_dmac_off_dmsts:
      /* ESIF/DTIF are write-0-to-clear; keep only bits still set. */
      c->dmsts &= (uint8_t)value;
      break;
    default:
      break;
  }
}

RA8_INTERNAL static void
internal_dmac_reg_write(uc_engine* uc, uint32_t ch, uint64_t off, uint32_t value)
{
  if (off == (uint64_t)k_dmac_off_dmreq) {
    if ((value & (uint32_t)k_dmac_swreq_mask) != 0U) {
      internal_dmac_run_transfer(uc, ch); /* SWREQ auto-clears once accepted */
    }
    return;
  }
  internal_dmac_reg_store(&s_dmac[ch], off, value);
}

RA8_INTERNAL static uint64_t internal_dmac_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint32_t ch = (uint32_t)((addr - (uint64_t)k_dmac_base) / (uint64_t)k_dmac_stride);
  return internal_dmac_reg_read(ch, (addr - (uint64_t)k_dmac_base) % (uint64_t)k_dmac_stride);
}

RA8_INTERNAL static void
internal_dmac_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)size;
  const uint32_t ch = (uint32_t)((addr - (uint64_t)k_dmac_base) / (uint64_t)k_dmac_stride);
  internal_dmac_reg_write(uc,
                          ch,
                          (addr - (uint64_t)k_dmac_base) % (uint64_t)k_dmac_stride,
                          (uint32_t)value);
}
 
/* =============================================================================
 * Shared DMA module-control bank (transparent shadow).
 * =============================================================================
 */

RA8_INTERNAL static uint64_t
internal_shadow_read(const uint8_t* shadow, uint64_t span, uint64_t off, unsigned size)
{
  uint64_t v = 0U;
  for (unsigned i = 0U; i < size; i++) {
    const uint64_t b = off + (uint64_t)i;
    if (b < span) {
      v |= (uint64_t)shadow[b] << (8U * i);
    }
  }
  return v;
}

RA8_INTERNAL static void
internal_shadow_write(uint8_t* shadow, uint64_t span, uint64_t off, unsigned size, uint64_t value)
{
  for (unsigned i = 0U; i < size; i++) {
    const uint64_t b = off + (uint64_t)i;
    if (b < span) {
      shadow[b] = (uint8_t)(value >> (8U * i));
    }
  }
}

RA8_INTERNAL static uint64_t internal_dma_shared_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  return internal_shadow_read(s_dma_shared,
                              (uint64_t)k_dma_shared_span,
                              addr - (uint64_t)k_dma_shared_base,
                              size);
}

RA8_INTERNAL static void
internal_dma_shared_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  internal_shadow_write(s_dma_shared,
                        (uint64_t)k_dma_shared_span,
                        addr - (uint64_t)k_dma_shared_base,
                        size,
                        value);
}
 
/* =============================================================================
 * Reset / report (carried by the DMAC channel descriptor).
 * =============================================================================
 */

RA8_INTERNAL static void internal_dmac_reset(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_dmac_count; i++) {
    s_dmac[i] = (dmac_chan_t){};
  }
  for (uint32_t i = 0U; i < (uint32_t)k_dma_shared_span; i++) {
    s_dma_shared[i] = 0U;
  }
}

RA8_INTERNAL static void internal_dmac_report(void)
{
  for (uint32_t ch = 0U; ch < (uint32_t)k_dmac_count; ch++) {
    if (s_dmac[ch].copies > 0U) {
      (void)priv_emu_io_errf("  DMAC%u         : transfers=%u last_units=%u DMSTS=0x%02X\n",
                             ch,
                             s_dmac[ch].copies,
                             s_dmac[ch].units,
                             s_dmac[ch].dmsts);
    }
  }
}
 
/* The DMAC channel descriptor carries reset + report covering every DMAC
 * window; the shared-bank and DTC descriptors only own their register windows.
 * Registration order between them is irrelevant (dispatch is by disjoint
 * range). */

static const board_periph_block_t s_k_dmac_block = {
  .base   = (uint64_t)k_dmac_base,
  .span   = (uint64_t)k_dmac_span,
  .order  = (uint32_t)k_dmac_block_order,
  .read   = internal_dmac_read,
  .write  = internal_dmac_write,
  .tick   = nullptr,
  .reset  = internal_dmac_reset,
  .report = internal_dmac_report,
  .name   = "DMAC",
};

static const board_periph_block_t s_k_dma_shared_block = {
  .base   = (uint64_t)k_dma_shared_base,
  .span   = (uint64_t)k_dma_shared_span,
  .order  = (uint32_t)k_dmac_block_order,
  .read   = internal_dma_shared_read,
  .write  = internal_dma_shared_write,
  .tick   = nullptr,
  .reset  = nullptr,
  .report = nullptr,
  .name   = "DMA",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_board_periph_dmac_register(void)
{
  board_periph_register_block(&s_k_dmac_block);
  board_periph_register_block(&s_k_dma_shared_block);
}