ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_pdm_regs_t Struct Reference

Full PDM-IF register block: common bank + 3 channel banks. More...

#include <ra8_pdm_regs.h>

Collaboration diagram for r_pdm_regs_t:

Data Fields

volatile uint32_t PDCSTRTR
 +0x00 Channel Software Start Trigger.
volatile uint32_t PDCSTPTR
 +0x04 Channel Software Stop Trigger.
volatile uint32_t PDCCHGTR
 +0x08 Channel Software Change Trigger.
volatile uint32_t PDCICR
 +0x0C Channel Interrupt Control.
volatile uint32_t PDCSR
 +0x10 Channel Status.
volatile uint32_t PDCSCR
 +0x14 Channel Status Clear.
volatile uint32_t RESERVED0 [2]
 +0x18 reserved.
volatile uint32_t PDCSDCR
 +0x20 Channel Sound Detection Control.
volatile uint32_t PDCDRCR
 +0x24 Channel Data Read Control.
volatile uint32_t PDCDCR
 +0x28 Channel Data Clear.
volatile uint32_t RESERVED1 [k_ra8_pdm_common_rsvd1_words]
 +0x2C reserved.
volatile uint32_t PDVR
 +0x80 Version.
volatile uint32_t RESERVED2 [k_ra8_pdm_common_rsvd2_words]
 +0x84 reserved.
r_pdm_ch_regs_t CH [3]
 +0x100 Per-channel register banks.

Detailed Description

Full PDM-IF register block: common bank + 3 channel banks.

Accessed through ra8_pdm(). The common bank drives channel-wide start/stop/status; CH[n] carries the per-channel configuration and data path.

Definition at line 159 of file ra8_pdm_regs.h.

Field Documentation

◆ CH

r_pdm_ch_regs_t r_pdm_regs_t::CH[3]

+0x100 Per-channel register banks.

Definition at line 176 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_ch().

◆ PDCCHGTR

volatile uint32_t r_pdm_regs_t::PDCCHGTR

+0x08 Channel Software Change Trigger.

Definition at line 162 of file ra8_pdm_regs.h.

◆ PDCDCR

volatile uint32_t r_pdm_regs_t::PDCDCR

+0x28 Channel Data Clear.

Definition at line 169 of file ra8_pdm_regs.h.

◆ PDCDRCR

volatile uint32_t r_pdm_regs_t::PDCDRCR

+0x24 Channel Data Read Control.

Definition at line 168 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_deinit(), and ra8_pdm_init().

◆ PDCICR

volatile uint32_t r_pdm_regs_t::PDCICR

+0x0C Channel Interrupt Control.

Definition at line 163 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_init().

◆ PDCSCR

volatile uint32_t r_pdm_regs_t::PDCSCR

+0x14 Channel Status Clear.

Definition at line 165 of file ra8_pdm_regs.h.

◆ PDCSDCR

volatile uint32_t r_pdm_regs_t::PDCSDCR

+0x20 Channel Sound Detection Control.

Definition at line 167 of file ra8_pdm_regs.h.

◆ PDCSR

volatile uint32_t r_pdm_regs_t::PDCSR

+0x10 Channel Status.

Definition at line 164 of file ra8_pdm_regs.h.

◆ PDCSTPTR

volatile uint32_t r_pdm_regs_t::PDCSTPTR

+0x04 Channel Software Stop Trigger.

Definition at line 161 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_stop().

◆ PDCSTRTR

volatile uint32_t r_pdm_regs_t::PDCSTRTR

+0x00 Channel Software Start Trigger.

Definition at line 160 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_start().

◆ PDVR

volatile uint32_t r_pdm_regs_t::PDVR

+0x80 Version.

Definition at line 173 of file ra8_pdm_regs.h.

◆ RESERVED0

volatile uint32_t r_pdm_regs_t::RESERVED0[2]

+0x18 reserved.

Definition at line 166 of file ra8_pdm_regs.h.

◆ RESERVED1

volatile uint32_t r_pdm_regs_t::RESERVED1[k_ra8_pdm_common_rsvd1_words]

+0x2C reserved.

Definition at line 171 of file ra8_pdm_regs.h.

◆ RESERVED2

volatile uint32_t r_pdm_regs_t::RESERVED2[k_ra8_pdm_common_rsvd2_words]

+0x84 reserved.

Definition at line 175 of file ra8_pdm_regs.h.

The documentation for this struct was generated from the following file: