ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_pdm_ch_regs_t Struct Reference

Per-channel PDM-IF register bank (256 bytes, HUM Ch 49.2). More...

#include <ra8_pdm_regs.h>

Data Fields

volatile uint32_t PDSTRTR
 +0x00 Software Start Trigger.
volatile uint32_t PDSTPTR
 +0x04 Software Stop Trigger.
volatile uint32_t PDCHGTR
 +0x08 Software Change Trigger.
volatile uint32_t PDICR
 +0x0C Interrupt Control.
volatile uint32_t PDSDCR
 +0x10 Status Detection Control.
volatile uint32_t PDSR
 +0x14 Status.
volatile uint32_t PDSCR
 +0x18 Status Clear.
volatile uint32_t RESERVED0
 +0x1C reserved.
volatile uint32_t PDMDSR
 +0x20 Mode Setting.
volatile uint32_t PDSFCR
 +0x24 Sinc Filter Control.
volatile uint32_t PDHFCS0R
 +0x28 High-pass filter coeff s(0).
volatile uint32_t PDHFCK1R
 +0x2C High-pass filter coeff k(1).
volatile uint32_t PDHFCHR [2]
 +0x30 High-pass filter coeff h(0..1).
volatile uint32_t PDCFCHR [k_ra8_pdm_cfch_count]
 +0x38 Comp filter coeff h(0..10).
volatile uint32_t PDLFCH010R
 +0x64 Low-pass filter coeff h0(10).
volatile uint32_t PDLFCH1R [k_ra8_pdm_lfch1_count]
 +0x68 Low-pass filter coeff h1(0..19).
volatile uint32_t PDSDLTR
 +0xB8 Sound Detection Lower Threshold.
volatile uint32_t PDSDUTR
 +0xBC Sound Detection Upper Threshold.
volatile uint32_t PDDBCR
 +0xC0 Data Buffer Control.
volatile uint32_t PDSCTSR
 +0xC4 Short Circuit Threshold Setting.
volatile uint32_t PDOVLTR
 +0xC8 Overvoltage Lower Threshold.
volatile uint32_t PDOVUTR
 +0xCC Overvoltage Upper Threshold.
volatile uint32_t RESERVED1 [4]
 +0xD0 reserved.
volatile uint32_t PDDRCR
 +0xE0 Data Read Control.
volatile uint32_t PDDCR
 +0xE4 Data Clear.
volatile uint32_t PDDRR
 +0xE8 Data Read (20-bit PCM out).
volatile uint32_t PDDSR
 +0xEC Data Status (FIFO fill count).
volatile uint32_t RESERVED2 [4]
 +0xF0 reserved.

Detailed Description

Per-channel PDM-IF register bank (256 bytes, HUM Ch 49.2).

One instance per channel; ra8_pdm()->CH[n] selects channel n. Every member maps a register documented in HUM Ch 49; the RESERVED* gaps reproduce the manual's address map so the offsets of live registers stay correct.

Definition at line 107 of file ra8_pdm_regs.h.

Field Documentation

◆ PDCFCHR

volatile uint32_t r_pdm_ch_regs_t::PDCFCHR[k_ra8_pdm_cfch_count]

+0x38 Comp filter coeff h(0..10).

Definition at line 121 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_coeffs().

◆ PDCHGTR

volatile uint32_t r_pdm_ch_regs_t::PDCHGTR

+0x08 Software Change Trigger.

Definition at line 110 of file ra8_pdm_regs.h.

◆ PDDBCR

volatile uint32_t r_pdm_ch_regs_t::PDDBCR

+0xC0 Data Buffer Control.

Definition at line 126 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_configure().

◆ PDDCR

volatile uint32_t r_pdm_ch_regs_t::PDDCR

+0xE4 Data Clear.

Definition at line 132 of file ra8_pdm_regs.h.

◆ PDDRCR

volatile uint32_t r_pdm_ch_regs_t::PDDRCR

+0xE0 Data Read Control.

Definition at line 131 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_read_enable(), and ra8_pdm_stop().

◆ PDDRR

volatile uint32_t r_pdm_ch_regs_t::PDDRR

+0xE8 Data Read (20-bit PCM out).

Definition at line 133 of file ra8_pdm_regs.h.

Referenced by internal_pdm_data_isr(), ra8_pdm_read(), and ra8_pdm_read_enable().

◆ PDDSR

volatile uint32_t r_pdm_ch_regs_t::PDDSR

+0xEC Data Status (FIFO fill count).

Definition at line 134 of file ra8_pdm_regs.h.

Referenced by internal_pdm_data_isr(), and ra8_pdm_read().

◆ PDHFCHR

volatile uint32_t r_pdm_ch_regs_t::PDHFCHR[2]

+0x30 High-pass filter coeff h(0..1).

Definition at line 120 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_coeffs().

◆ PDHFCK1R

volatile uint32_t r_pdm_ch_regs_t::PDHFCK1R

+0x2C High-pass filter coeff k(1).

Definition at line 119 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_coeffs().

◆ PDHFCS0R

volatile uint32_t r_pdm_ch_regs_t::PDHFCS0R

+0x28 High-pass filter coeff s(0).

Definition at line 118 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_coeffs().

◆ PDICR

volatile uint32_t r_pdm_ch_regs_t::PDICR

+0x0C Interrupt Control.

Definition at line 111 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_stream_disable(), and ra8_pdm_stream_enable().

◆ PDLFCH010R

volatile uint32_t r_pdm_ch_regs_t::PDLFCH010R

+0x64 Low-pass filter coeff h0(10).

Definition at line 122 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_coeffs().

◆ PDLFCH1R

volatile uint32_t r_pdm_ch_regs_t::PDLFCH1R[k_ra8_pdm_lfch1_count]

+0x68 Low-pass filter coeff h1(0..19).

Definition at line 123 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_coeffs().

◆ PDMDSR

volatile uint32_t r_pdm_ch_regs_t::PDMDSR

+0x20 Mode Setting.

Definition at line 116 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_mode().

◆ PDOVLTR

volatile uint32_t r_pdm_ch_regs_t::PDOVLTR

+0xC8 Overvoltage Lower Threshold.

Definition at line 128 of file ra8_pdm_regs.h.

◆ PDOVUTR

volatile uint32_t r_pdm_ch_regs_t::PDOVUTR

+0xCC Overvoltage Upper Threshold.

Definition at line 129 of file ra8_pdm_regs.h.

◆ PDSCR

volatile uint32_t r_pdm_ch_regs_t::PDSCR

+0x18 Status Clear.

Definition at line 114 of file ra8_pdm_regs.h.

Referenced by ra8_pdm_read_enable().

◆ PDSCTSR

volatile uint32_t r_pdm_ch_regs_t::PDSCTSR

+0xC4 Short Circuit Threshold Setting.

Definition at line 127 of file ra8_pdm_regs.h.

◆ PDSDCR

volatile uint32_t r_pdm_ch_regs_t::PDSDCR

+0x10 Status Detection Control.

Definition at line 112 of file ra8_pdm_regs.h.

◆ PDSDLTR

volatile uint32_t r_pdm_ch_regs_t::PDSDLTR

+0xB8 Sound Detection Lower Threshold.

Definition at line 124 of file ra8_pdm_regs.h.

◆ PDSDUTR

volatile uint32_t r_pdm_ch_regs_t::PDSDUTR

+0xBC Sound Detection Upper Threshold.

Definition at line 125 of file ra8_pdm_regs.h.

◆ PDSFCR

volatile uint32_t r_pdm_ch_regs_t::PDSFCR

+0x24 Sinc Filter Control.

Definition at line 117 of file ra8_pdm_regs.h.

Referenced by internal_pdm_write_mode().

◆ PDSR

volatile uint32_t r_pdm_ch_regs_t::PDSR

+0x14 Status.

Definition at line 113 of file ra8_pdm_regs.h.

◆ PDSTPTR

volatile uint32_t r_pdm_ch_regs_t::PDSTPTR

+0x04 Software Stop Trigger.

Definition at line 109 of file ra8_pdm_regs.h.

◆ PDSTRTR

volatile uint32_t r_pdm_ch_regs_t::PDSTRTR

+0x00 Software Start Trigger.

Definition at line 108 of file ra8_pdm_regs.h.

◆ RESERVED0

volatile uint32_t r_pdm_ch_regs_t::RESERVED0

+0x1C reserved.

Definition at line 115 of file ra8_pdm_regs.h.

◆ RESERVED1

volatile uint32_t r_pdm_ch_regs_t::RESERVED1[4]

+0xD0 reserved.

Definition at line 130 of file ra8_pdm_regs.h.

◆ RESERVED2

volatile uint32_t r_pdm_ch_regs_t::RESERVED2[4]

+0xF0 reserved.

Definition at line 135 of file ra8_pdm_regs.h.

The documentation for this struct was generated from the following file: