ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_pdm_regs.h
Go to the documentation of this file.
1
22
23#pragma once
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <stddef.h>
30#include <stdint.h>
31
36typedef enum : uintptr_t {
37 k_ra8_pdm_base_addr = 0x40256000UL,
39
44typedef enum : uint8_t {
47
62
81
90typedef enum : uint32_t {
96
107typedef struct {
108 volatile uint32_t PDSTRTR;
109 volatile uint32_t PDSTPTR;
110 volatile uint32_t PDCHGTR;
111 volatile uint32_t PDICR;
112 volatile uint32_t PDSDCR;
113 volatile uint32_t PDSR;
114 volatile uint32_t PDSCR;
115 volatile uint32_t RESERVED0;
116 volatile uint32_t PDMDSR;
117 volatile uint32_t PDSFCR;
118 volatile uint32_t PDHFCS0R;
119 volatile uint32_t PDHFCK1R;
120 volatile uint32_t PDHFCHR[2];
121 volatile uint32_t PDCFCHR[k_ra8_pdm_cfch_count];
122 volatile uint32_t PDLFCH010R;
123 volatile uint32_t PDLFCH1R[k_ra8_pdm_lfch1_count];
124 volatile uint32_t PDSDLTR;
125 volatile uint32_t PDSDUTR;
126 volatile uint32_t PDDBCR;
127 volatile uint32_t PDSCTSR;
128 volatile uint32_t PDOVLTR;
129 volatile uint32_t PDOVUTR;
130 volatile uint32_t RESERVED1[4];
131 volatile uint32_t PDDRCR;
132 volatile uint32_t PDDCR;
133 volatile uint32_t PDDRR;
134 volatile uint32_t PDDSR;
135 volatile uint32_t RESERVED2[4];
137
138static_assert(sizeof(r_pdm_ch_regs_t) == (size_t)k_ra8_pdm_ch_bank_bytes,
139 "PDM channel bank must be 256 bytes");
140static_assert(offsetof(r_pdm_ch_regs_t, PDMDSR) == (size_t)k_ra8_pdm_off_pdmdsr, "PDMDSR offset");
141static_assert(offsetof(r_pdm_ch_regs_t, PDSFCR) == (size_t)k_ra8_pdm_off_pdsfcr, "PDSFCR offset");
142static_assert(offsetof(r_pdm_ch_regs_t, PDCFCHR) == (size_t)k_ra8_pdm_off_pdcfchr,
143 "PDCFCHR offset");
144static_assert(offsetof(r_pdm_ch_regs_t, PDLFCH010R) == (size_t)k_ra8_pdm_off_pdlfch010r,
145 "PDLFCH010R offset");
146static_assert(offsetof(r_pdm_ch_regs_t, PDDRCR) == (size_t)k_ra8_pdm_off_pddrcr, "PDDRCR offset");
147static_assert(offsetof(r_pdm_ch_regs_t, PDDRR) == (size_t)k_ra8_pdm_off_pddrr, "PDDRR offset");
148static_assert(offsetof(r_pdm_ch_regs_t, PDDSR) == (size_t)k_ra8_pdm_off_pddsr, "PDDSR offset");
149
159typedef struct {
160 volatile uint32_t PDCSTRTR;
161 volatile uint32_t PDCSTPTR;
162 volatile uint32_t PDCCHGTR;
163 volatile uint32_t PDCICR;
164 volatile uint32_t PDCSR;
165 volatile uint32_t PDCSCR;
166 volatile uint32_t RESERVED0[2];
167 volatile uint32_t PDCSDCR;
168 volatile uint32_t PDCDRCR;
169 volatile uint32_t PDCDCR;
173 volatile uint32_t PDVR;
178
179static_assert(offsetof(r_pdm_regs_t, PDCSR) == (size_t)k_ra8_pdm_off_pdcsr, "PDCSR offset");
180static_assert(offsetof(r_pdm_regs_t, PDVR) == (size_t)k_ra8_pdm_off_pdvr, "PDVR offset");
181static_assert(offsetof(r_pdm_regs_t, CH) == (size_t)k_ra8_pdm_off_ch, "CH bank offset");
182static_assert(sizeof(r_pdm_regs_t) == (size_t)k_ra8_pdm_block_bytes,
183 "PDM block must be 1024 bytes");
184
198
208
222
227typedef enum : uint32_t {
233
238static inline volatile r_pdm_regs_t* ra8_pdm(void)
239{
240 return (volatile r_pdm_regs_t*)k_ra8_pdm_base_addr;
241}
242
248static inline volatile r_pdm_ch_regs_t* ra8_pdm_ch(uint8_t ch)
249{
250 return &ra8_pdm()->CH[ch];
251}
252
253#ifdef __cplusplus
254}
255#endif
ra8_pdm_addr_t
Base address of the PDM-IF register block.
@ k_ra8_pdm_base_addr
PDM-IF Secure base (HUM Ch 49 p 3190).
static volatile r_pdm_regs_t * ra8_pdm(void)
Get a pointer to the PDM-IF register block.
ra8_pdm_status_bits_t
Trigger / status / data-read bit masks (HUM Ch 49.2).
@ k_ra8_pdm_pdsr_drf
PDSR[2] data reception flag.
@ k_ra8_pdm_pdscr_clr_all
PDSCR clear-all write pattern.
@ k_ra8_pdm_pdstptr_stp
PDSTPTR[0] stop trigger.
@ k_ra8_pdm_pddrcr_datre
PDDRCR[0] data read enable.
@ k_ra8_pdm_pdsr_state
PDSR[0] channel running.
@ k_ra8_pdm_pdstrtr_strt
PDSTRTR[0] start trigger.
@ k_ra8_pdm_pdicr_idre
PDICR[2] data IRQ enable.
ra8_pdm_pdmdsr_bits_t
PDMDSRCHn (Mode Setting) field shifts (HUM Ch 49.2.19 p 3208).
@ k_ra8_pdm_pdmdsr_hfis_pos
[9:8] High-pass input shift.
@ k_ra8_pdm_pdmdsr_dbis_pos
[31:28] Data buffer input shift.
@ k_ra8_pdm_pdmdsr_sdma_pos
[25:24] Sound-detect avg mode.
@ k_ra8_pdm_pdmdsr_lfis_pos
[17:16] Low-pass input shift.
@ k_ra8_pdm_pdmdsr_sfmd_pos
[6:4] Sinc filter mode shift.
@ k_ra8_pdm_pdmdsr_inpsel
[0] Input data edge select.
@ k_ra8_pdm_pdmdsr_cfis_pos
[13:12] Compensation input shift.
ra8_pdm_data_bits_t
PDDRRCHn / PDDSRCHn field masks (HUM Ch 49.2.36, 49.2.37).
@ k_ra8_pdm_pddrr_dat_mask
PDDRR[19:0] 20-bit PCM.
@ k_ra8_pdm_pddrr_sign_ext
High bits set on negatives.
@ k_ra8_pdm_pddrr_sign_bit
PDDRR[19] sign bit.
@ k_ra8_pdm_pddsr_num_mask
PDDSR[7:0] FIFO fill count.
static volatile r_pdm_ch_regs_t * ra8_pdm_ch(uint8_t ch)
Get a pointer to a PDM-IF channel register bank.
ra8_pdm_array_count_t
Element counts for the variable-length register arrays.
@ k_ra8_pdm_cfch_count
PDCFCHR compensation-filter coeffs h(0..10).
@ k_ra8_pdm_common_rsvd2_words
Common bank +0x84 reserved-word run.
@ k_ra8_pdm_lfch1_count
PDLFCH1R low-pass-filter coeffs h1(0..19).
@ k_ra8_pdm_common_rsvd1_words
Common bank +0x2C reserved-word run.
ra8_pdm_ch_off_t
Byte offsets of live registers within one channel bank (HUM Ch 49.2).
@ k_ra8_pdm_off_pdcfchr
PDCFCHR Compensation filter coeff h0.
@ k_ra8_pdm_off_pddrr
PDDRR Data Read (20-bit PCM out).
@ k_ra8_pdm_off_pddsr
PDDSR Data Status (FIFO fill count).
@ k_ra8_pdm_ch_bank_bytes
Per-channel bank stride and size (256 B).
@ k_ra8_pdm_off_pdsfcr
PDSFCR Sinc Filter Control.
@ k_ra8_pdm_off_pddrcr
PDDRCR Data Read Control.
@ k_ra8_pdm_off_pdmdsr
PDMDSR Mode Setting.
@ k_ra8_pdm_off_pdlfch010r
PDLFCH010R Low-pass filter coeff h0(10).
ra8_pdm_fifo_t
Receive-FIFO geometry constants (HUM Ch 49.3.4).
@ k_ra8_pdm_fifo_depth
PDDRR FIFO depth (samples).
ra8_pdm_pdsfcr_bits_t
PDSFCRCHn (Sinc Filter Control) field shifts (HUM Ch 49.2.20 p 3209).
@ k_ra8_pdm_pdsfcr_ckdiv_pos
[3:0] PDM_CLKn dividend ratio.
@ k_ra8_pdm_pdsfcr_sincrng_pos
[28:24] Sinc output valid range.
@ k_ra8_pdm_pdsfcr_sincdec_pos
[23:16] Sinc decimation ratio.
ra8_pdm_common_off_t
Byte offsets of live common-bank registers plus the block size.
@ k_ra8_pdm_block_bytes
Full PDM-IF block size (1024 bytes).
@ k_ra8_pdm_off_pdcsr
PDCSR Channel Status.
@ k_ra8_pdm_off_pdvr
PDVR Version.
@ k_ra8_pdm_off_ch
CH[0] per-channel banks start offset.
Per-channel PDM-IF register bank (256 bytes, HUM Ch 49.2).
volatile uint32_t PDICR
+0x0C Interrupt Control.
volatile uint32_t PDCHGTR
+0x08 Software Change Trigger.
volatile uint32_t PDSR
+0x14 Status.
volatile uint32_t PDDSR
+0xEC Data Status (FIFO fill count).
volatile uint32_t PDOVUTR
+0xCC Overvoltage Upper Threshold.
volatile uint32_t PDOVLTR
+0xC8 Overvoltage Lower Threshold.
volatile uint32_t PDLFCH1R[k_ra8_pdm_lfch1_count]
+0x68 Low-pass filter coeff h1(0..19).
volatile uint32_t PDSDLTR
+0xB8 Sound Detection Lower Threshold.
volatile uint32_t PDDBCR
+0xC0 Data Buffer Control.
volatile uint32_t PDDRCR
+0xE0 Data Read Control.
volatile uint32_t PDSFCR
+0x24 Sinc Filter Control.
volatile uint32_t PDDRR
+0xE8 Data Read (20-bit PCM out).
volatile uint32_t PDSDUTR
+0xBC Sound Detection Upper Threshold.
volatile uint32_t PDSDCR
+0x10 Status Detection Control.
volatile uint32_t PDHFCHR[2]
+0x30 High-pass filter coeff h(0..1).
volatile uint32_t RESERVED1[4]
+0xD0 reserved.
volatile uint32_t PDSCR
+0x18 Status Clear.
volatile uint32_t PDSTRTR
+0x00 Software Start Trigger.
volatile uint32_t PDCFCHR[k_ra8_pdm_cfch_count]
+0x38 Comp filter coeff h(0..10).
volatile uint32_t PDSTPTR
+0x04 Software Stop Trigger.
volatile uint32_t RESERVED2[4]
+0xF0 reserved.
volatile uint32_t PDHFCS0R
+0x28 High-pass filter coeff s(0).
volatile uint32_t PDLFCH010R
+0x64 Low-pass filter coeff h0(10).
volatile uint32_t PDHFCK1R
+0x2C High-pass filter coeff k(1).
volatile uint32_t PDSCTSR
+0xC4 Short Circuit Threshold Setting.
volatile uint32_t RESERVED0
+0x1C reserved.
volatile uint32_t PDDCR
+0xE4 Data Clear.
volatile uint32_t PDMDSR
+0x20 Mode Setting.
Full PDM-IF register block: common bank + 3 channel banks.
volatile uint32_t PDCSR
+0x10 Channel Status.
volatile uint32_t PDVR
+0x80 Version.
volatile uint32_t PDCSTRTR
+0x00 Channel Software Start Trigger.
volatile uint32_t PDCDRCR
+0x24 Channel Data Read Control.
volatile uint32_t PDCSDCR
+0x20 Channel Sound Detection Control.
volatile uint32_t PDCDCR
+0x28 Channel Data Clear.
volatile uint32_t PDCCHGTR
+0x08 Channel Software Change Trigger.
volatile uint32_t PDCICR
+0x0C Channel Interrupt Control.
volatile uint32_t RESERVED1[k_ra8_pdm_common_rsvd1_words]
+0x2C reserved.
volatile uint32_t RESERVED0[2]
+0x18 reserved.
r_pdm_ch_regs_t CH[3]
+0x100 Per-channel register banks.
volatile uint32_t PDCSCR
+0x14 Channel Status Clear.
volatile uint32_t RESERVED2[k_ra8_pdm_common_rsvd2_words]
+0x84 reserved.
volatile uint32_t PDCSTPTR
+0x04 Channel Software Stop Trigger.