ra8_sdhi_regs.h File Reference

SDHI (SD/MMC host interface) register layout for the Renesas RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_sdhi_regs.h:

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Data Structures
struct	r_sdhi_regs_t
	SDHI register window. More...

Enumerations
enum	ra8_sdhi_addr_t : uintptr_t {   k_ra8_sdhi0_base_addr = 0x40252000UL ,   k_ra8_sdhi1_base_addr = 0x40252400UL ,   k_ra8_sdhi_stride = 0x400UL }
enum	ra8_sdhi_limits_t : uint8_t { k_ra8_sdhi_instance_count = 2U }
enum	ra8_sdhi_xfer_bits_t : uint32_t {   k_ra8_sdhi_info2_bre_mask = 0x00000100UL ,   k_ra8_sdhi_info2_bwe_mask = 0x00000200UL ,   k_ra8_sdhi_info2_brem_bwem = 0x00000300UL ,   k_ra8_sdhi_stop_seccnt_en = 0x00000100UL ,   k_ra8_sdhi_dmaen_set = 0x00000002UL }
	SD_INFO2 / SD_STOP bit-masks used by the block-transfer path. More...
enum	ra8_sdhi_cmd_id_t : uint8_t {   k_ra8_sdhi_cmd_set_bus_width = 6U ,   k_ra8_sdhi_cmd_emmc_switch = 6U ,   k_ra8_sdhi_cmd_stop_transmission = 12U ,   k_ra8_sdhi_cmd_read_single_block = 17U ,   k_ra8_sdhi_cmd_read_multi_block = 18U ,   k_ra8_sdhi_cmd_write_single_block = 24U ,   k_ra8_sdhi_cmd_write_multi_block = 25U ,   k_ra8_sdhi_cmd_app_cmd = 55U }
	SD command numbers used by the block-transfer API. More...
enum	ra8_sdhi_geometry_t : uint32_t {   k_ra8_sdhi_block_bytes = 512UL ,   k_ra8_sdhi_fifo_word_bytes = 4UL ,   k_ra8_sdhi_words_per_block = 128UL }
	Block-transfer geometry constants. More...
enum	ra8_sdhi_option_bits_t : uint32_t {   k_ra8_sdhi_option_top_default = 0x000000E0UL ,   k_ra8_sdhi_option_rsvd_bit14 = 0x00004000UL ,   k_ra8_sdhi_option_width8_bit = 0x00002000UL ,   k_ra8_sdhi_option_width_bit = 0x00008000UL ,   k_ra8_sdhi_option_width_mask = k_ra8_sdhi_option_width_bit | k_ra8_sdhi_option_width8_bit ,   k_ra8_sdhi_option_bus_1bit ,   k_ra8_sdhi_option_bus_4bit = k_ra8_sdhi_option_rsvd_bit14 | k_ra8_sdhi_option_top_default ,   k_ra8_sdhi_option_bus_8bit }
	SD_OPTION bus-width selectors and timeout-field defaults. More...
enum	ra8_sdhi_acmd6_bits_t : uint32_t {   k_ra8_sdhi_acmd6_arg_1bit = 0x00000000UL ,   k_ra8_sdhi_acmd6_arg_4bit = 0x00000002UL ,   k_ra8_sdhi_r1_app_cmd_mask = 0x00000020UL ,   k_ra8_sdhi_r1_illegal_command = 0x00400000UL ,   k_ra8_sdhi_r1_error_mask = 0xFDF90008UL }
	ACMD6 (SET_BUS_WIDTH) argument + R1 status-bit masks. More...
enum	ra8_sdhi_cmd6_switch_bits_t : uint32_t {   k_ra8_sdhi_switch_access_write_byte = 0x03000000UL ,   k_ra8_sdhi_switch_index_bus_width = 0x00B70000UL ,   k_ra8_sdhi_switch_value_8bit = 0x00000200UL ,   k_ra8_sdhi_cmd6_arg_8bit }
	eMMC CMD6 (SWITCH) argument fields for the 8-bit bus-width switch. More...
enum	ra8_sdhi_arg_shift_t : uint8_t { k_ra8_sdhi_rca_arg_shift = 16U }
	Bit-shift amounts for SD command-argument packing. More...

Functions
static volatile r_sdhi_regs_t *	ra8_sdhi (uint8_t instance)
	Get pointer to SDHI instance N (0 or 1).

Detailed Description

SDHI (SD/MMC host interface) register layout for the Renesas RA8D2.

Two SDHI instances at 0x40252000 (SDHI0) and 0x40252400 (SDHI1). The full register window covers command issue, response, status, interrupt mask, clock control, transfer-data length, access option, error status, FIFO buffer, SDIO mode, DMA enable, software reset, SD interface mode, and endianness swap.

Layout cross-verified against FSP R_SDHI0_Type (sibling RA SoC BSP header R7FA6M3AH.h lines 14964-15442, structure size 0x1E4 bytes) – the same hardware block ships unchanged across RA6M3, RA6M5, and RA8 series. Register access widths and bit positions are identical; only the base address differs on RA8D2.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_sdhi_regs.h.

Enumeration Type Documentation

ra8_sdhi_acmd6_bits_t

enum ra8_sdhi_acmd6_bits_t : uint32_t

ACMD6 (SET_BUS_WIDTH) argument + R1 status-bit masks.

The ACMD6 application command negotiates the card-side data-bus width. Its 32-bit argument carries the width in bits [1:0] (0b00 = 1-bit, 0b10 = 4-bit); the SDHI replays the R1 card-status response in SD_RSP10 (HUM Ch 47.2.5 "SD_RSP10..76 : SD Response Registers" p 3132). These constants name the bits the ACMD6 negotiation inspects so the driver carries no magic numbers:

• APP_CMD (R1 bit 5) is set in the CMD55 response to confirm the card accepted the application-command prefix.
• ILLEGAL_COMMAND (R1 bit 22) is a representative R1 error bit.
• R1_ERROR_MASK covers every R1 error/violation bit (31..19, 16, 3); a non-zero AND means the card rejected the command and the host must stay at 1-bit.

Enumerator
k_ra8_sdhi_acmd6_arg_1bit	ACMD6 arg: 1-bit data bus.
k_ra8_sdhi_acmd6_arg_4bit	ACMD6 arg: 4-bit data bus.
k_ra8_sdhi_r1_app_cmd_mask	R1 bit 5 APP_CMD acknowledged.
k_ra8_sdhi_r1_illegal_command	R1 bit 22 ILLEGAL_COMMAND.
k_ra8_sdhi_r1_error_mask	R1 error/violation bit-mask.

Definition at line 176 of file ra8_sdhi_regs.h.

ra8_sdhi_addr_t

enum ra8_sdhi_addr_t : uintptr_t

Enumerator
k_ra8_sdhi0_base_addr	RA8 sdhi0 base address.
k_ra8_sdhi1_base_addr	RA8 sdhi1 base address.
k_ra8_sdhi_stride	RA8 SDHI stride.

Definition at line 33 of file ra8_sdhi_regs.h.

ra8_sdhi_arg_shift_t

enum ra8_sdhi_arg_shift_t : uint8_t

Bit-shift amounts for SD command-argument packing.

CMD55 (APP_CMD) carries the card's relative address (RCA) in the upper half of SD_ARG, i.e. SD_ARG[31:16] = RCA; the lower 16 bits are stuff bits. Naming the shift keeps the packing free of inline magic numbers.

Enumerator
k_ra8_sdhi_rca_arg_shift	RCA occupies SD_ARG[31:16].

Definition at line 225 of file ra8_sdhi_regs.h.

ra8_sdhi_cmd6_switch_bits_t

enum ra8_sdhi_cmd6_switch_bits_t : uint32_t

eMMC CMD6 (SWITCH) argument fields for the 8-bit bus-width switch.

SD cards top out at a 4-bit bus (negotiated with ACMD6); the 8-bit data bus is an eMMC-only feature reached through the JEDEC CMD6 SWITCH command (JESD84-B51 Section 6.6.4) rather than an application command – there is no CMD55 prefix. The 32-bit argument packs four fields:

| Bits    | Field  | Value here                              |
|---------|--------|-----------------------------------------|
| [25:24] | Access | 0b11 Write Byte                         |
| [23:16] | Index  | 183 (0xB7) = EXT_CSD BUS_WIDTH byte      |
| [15:8]  | Value  | 2 = 8-bit SDR (1 = 4-bit, 0 = 1-bit)    |
| [2:0]   | CmdSet | 0                                       |

The card replays an R1b card-status response in SD_RSP10; the same k_ra8_sdhi_r1_error_mask that guards ACMD6 rejects a switch that the card refused. k_ra8_sdhi_cmd6_arg_8bit is the whole argument composed from the three named field selectors so the driver carries no inline magic number.

Enumerator
k_ra8_sdhi_switch_access_write_byte	Access[25:24] = 0b11 Write Byte.
k_ra8_sdhi_switch_index_bus_width	Index[23:16] = 183 BUS_WIDTH.
k_ra8_sdhi_switch_value_8bit	Value[15:8] = 2 -> 8-bit SDR.
k_ra8_sdhi_cmd6_arg_8bit	Whole CMD6 SWITCH argument: BUS_WIDTH <- 8-bit (0x03B70200).

Definition at line 207 of file ra8_sdhi_regs.h.

ra8_sdhi_cmd_id_t

enum ra8_sdhi_cmd_id_t : uint8_t

SD command numbers used by the block-transfer API.

Mirrors FSP r_sdhi_private.h SDHI_PRV_CMD_*. The hardware SD_CMD register accepts the bare command index (0..63) for data transfer commands; the SDHI block infers the response and data direction from the command index alone – no additional data-phase or response-type bits are required for the four commands used by ra8_sdhi_read_block and ra8_sdhi_write_block.

Enumerator
k_ra8_sdhi_cmd_set_bus_width	ACMD6 SET_BUS_WIDTH (SD).
k_ra8_sdhi_cmd_emmc_switch	CMD6 SWITCH (eMMC EXT_CSD).
k_ra8_sdhi_cmd_stop_transmission	CMD12 STOP_TRANSMISSION.
k_ra8_sdhi_cmd_read_single_block	CMD17 READ_SINGLE_BLOCK.
k_ra8_sdhi_cmd_read_multi_block	CMD18 READ_MULTIPLE_BLOCK.
k_ra8_sdhi_cmd_write_single_block	CMD24 WRITE_SINGLE_BLOCK.
k_ra8_sdhi_cmd_write_multi_block	CMD25 WRITE_MULTIPLE_BLOCK.
k_ra8_sdhi_cmd_app_cmd	CMD55 APP_CMD prefix.

Definition at line 82 of file ra8_sdhi_regs.h.

ra8_sdhi_geometry_t

enum ra8_sdhi_geometry_t : uint32_t

Block-transfer geometry constants.

SD cards use a fixed 512-byte block size for SDHC/SDXC. The SDHI FIFO is 4 bytes wide (SD_BUF0 is a 32-bit register), so each block requires 128 four-byte transfers.

Enumerator
k_ra8_sdhi_block_bytes	SD block size in bytes.
k_ra8_sdhi_fifo_word_bytes	SD_BUF0 FIFO word width.
k_ra8_sdhi_words_per_block	512 / 4 = 128 word fills per block

Definition at line 101 of file ra8_sdhi_regs.h.

ra8_sdhi_limits_t

enum ra8_sdhi_limits_t : uint8_t

Enumerator
k_ra8_sdhi_instance_count	RA8 SDHI instance count.

Definition at line 39 of file ra8_sdhi_regs.h.

ra8_sdhi_option_bits_t

enum ra8_sdhi_option_bits_t : uint32_t

SD_OPTION bus-width selectors and timeout-field defaults.

SD_OPTION (HUM Ch 47.2.16 "SD_OPTION : SD Card Access Control Option Register" p 3139-3140) packs two bus-width bits, a timeout mask, and two timeout counters:

• WIDTH (bit 15) and WIDTH8 (bit 13) jointly select the bus width per the HUM truth table:

WIDTH	WIDTH8	Bus width
1	0	1-bit
0	0	4-bit
0	1	8-bit
1	1	1-bit

• Bit 14 is reserved but documented "read as 1, the write value should be 1", so every value written here keeps it set.
• TOP[3:0] (bits 7..4) is the data-timeout counter; 0xE selects the largest non-prohibited timeout.
• CTOP[3:0] (bits 3..0) is the card-detect counter; left at 0.

The three k_ra8_sdhi_option_bus_* values are the only ones the driver writes whole; k_ra8_sdhi_option_width_mask is the read-modify-write clear mask that isolates WIDTH+WIDTH8 so the timeout fields survive a bus-width change.

Note

The legacy literal 0x40E0 (WIDTH=0, WIDTH8=0) is the 4-bit encoding, not 1-bit as earlier scaffold comments claimed; the genuine 1-bit safe default is k_ra8_sdhi_option_bus_1bit (0xC0E0).

Enumerator
k_ra8_sdhi_option_top_default	TOP[3:0]=0xE, CTOP=0 (bits 7..0).
k_ra8_sdhi_option_rsvd_bit14	bit 14 reserved, must write 1
k_ra8_sdhi_option_width8_bit	WIDTH8 (bit 13): 1 -> 8-bit.
k_ra8_sdhi_option_width_bit	WIDTH (bit 15): 1 -> narrow bus.
k_ra8_sdhi_option_width_mask	Combined WIDTH+WIDTH8 clear mask for read-modify-write.
k_ra8_sdhi_option_bus_1bit	1-bit safe default: WIDTH=1, WIDTH8=0 (0xC0E0).
k_ra8_sdhi_option_bus_4bit	4-bit: WIDTH=0, WIDTH8=0 (0x40E0).
k_ra8_sdhi_option_bus_8bit	8-bit: WIDTH=0, WIDTH8=1 (0x60E0).

Definition at line 141 of file ra8_sdhi_regs.h.

ra8_sdhi_xfer_bits_t

enum ra8_sdhi_xfer_bits_t : uint32_t

SD_INFO2 / SD_STOP bit-masks used by the block-transfer path.

These bits are documented in HUM Ch 47.2.15 / 47.2.13. FSP's r_sdhi.c exposes them as private macros SDHI_PRV_SDHI_INFO2_CARD_BRE / CARD_BWE and SDHI_PRV_SD_STOP_SD_SECCNT_ENABLE. We mirror them here so the polled FIFO drain in :c:func:ra8_sdhi_read_block / :c:func:ra8_sdhi_write_block does not carry magic numbers.

• BRE (Buffer Read Enable, SD_INFO2 bit 8) - asserted when SD_BUF0 has at least one block worth of data ready to drain.
• BWE (Buffer Write Enable, SD_INFO2 bit 9) - asserted when the SD_BUF0 FIFO has space for one block worth of writes.
• BREM / BWEM mask bits live at the same positions in SD_INFO2_MASK and gate the two flags above when DMA is in use.
• SD_STOP_SECCNT_ENABLE (SD_STOP bit 8) tells the IP to stop the data phase after SD_SECCNT blocks have transferred.

Enumerator
k_ra8_sdhi_info2_bre_mask	SD_INFO2.BRE bit 8.
k_ra8_sdhi_info2_bwe_mask	SD_INFO2.BWE bit 9.
k_ra8_sdhi_info2_brem_bwem	SD_INFO2_MASK. {BREM,BWEM}
k_ra8_sdhi_stop_seccnt_en	SD_STOP.SEC bit 8.
k_ra8_sdhi_dmaen_set	SD_DMAEN.DMAEN bit 1.

Definition at line 63 of file ra8_sdhi_regs.h.

Function Documentation

ra8_sdhi()

volatile r_sdhi_regs_t * ra8_sdhi ( uint8_t instance )

inlinestatic

Get pointer to SDHI instance N (0 or 1).

Definition at line 291 of file ra8_sdhi_regs.h.

References k_ra8_sdhi0_base_addr, k_ra8_sdhi_instance_count, and k_ra8_sdhi_stride.

Referenced by ra8_sdhi_attach_dma(), ra8_sdhi_clear_status(), ra8_sdhi_deinit(), ra8_sdhi_dispatch(), ra8_sdhi_get_status(), ra8_sdhi_init(), ra8_sdhi_read_block(), ra8_sdhi_send_command(), ra8_sdhi_set_bus_width(), ra8_sdhi_set_bus_width_4bit(), ra8_sdhi_set_bus_width_8bit(), ra8_sdhi_set_clock(), and ra8_sdhi_write_block().