ra8_sci_regs.h File Reference

SCI_B (Serial Communication Interface, B variant) register layoutfor the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_sci_regs.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures
struct	r_sci_regs_t
	Per-channel SCI_B register window. More...

Enumerations
enum	ra8_sci_base_addr_t : uintptr_t {   k_ra8_sci0_base_addr = 0x40358000UL ,   k_ra8_sci1_base_addr = 0x40358100UL ,   k_ra8_sci2_base_addr = 0x40358200UL ,   k_ra8_sci3_base_addr = 0x40358300UL ,   k_ra8_sci4_base_addr = 0x40358400UL ,   k_ra8_sci5_base_addr = 0x40358500UL ,   k_ra8_sci6_base_addr = 0x40358600UL ,   k_ra8_sci7_base_addr = 0x40358700UL ,   k_ra8_sci8_base_addr = 0x40358800UL ,   k_ra8_sci9_base_addr = 0x40358900UL }
	Per-channel SCI_B base addresses (Secure alias). More...
enum	ra8_sci_limits_t : uint16_t {   k_ra8_sci_channel_count = 10U ,   k_ra8_sci_channel_max = 9U ,   k_ra8_sci_channel_stride = 0x100U }
	Channel-count and stride constants. More...
enum	ra8_sci_ccr0_bit_t : uint8_t {   k_ra8_sci_ccr0_bit_re = 0U ,   k_ra8_sci_ccr0_bit_te = 4U ,   k_ra8_sci_ccr0_bit_mpie = 8U ,   k_ra8_sci_ccr0_bit_dcme = 9U ,   k_ra8_sci_ccr0_bit_idsel = 10U ,   k_ra8_sci_ccr0_bit_rie = 16U ,   k_ra8_sci_ccr0_bit_tie = 20U ,   k_ra8_sci_ccr0_bit_teie = 21U ,   k_ra8_sci_ccr0_bit_sse = 24U }
	Bit positions in CCR0. More...
enum	ra8_sci_ccr1_bit_t : uint8_t {   k_ra8_sci_ccr1_bit_ctse = 0U ,   k_ra8_sci_ccr1_bit_ctspen = 1U ,   k_ra8_sci_ccr1_bit_spb2dt = 4U ,   k_ra8_sci_ccr1_bit_spb2io = 5U ,   k_ra8_sci_ccr1_bit_pe = 8U ,   k_ra8_sci_ccr1_bit_pm = 9U ,   k_ra8_sci_ccr1_bit_tinv = 12U ,   k_ra8_sci_ccr1_bit_rinv = 13U ,   k_ra8_sci_ccr1_bit_splp = 16U ,   k_ra8_sci_ccr1_bit_sharps = 20U ,   k_ra8_sci_ccr1_bit_nfen = 28U ,   k_ra8_sci_ccr1_bit_nfm = 29U }
	Bit positions in CCR1. More...
enum	ra8_sci_ccr2_bit_t : uint8_t {   k_ra8_sci_ccr2_bit_bgdm = 4U ,   k_ra8_sci_ccr2_bit_abcs = 5U ,   k_ra8_sci_ccr2_bit_abcse = 6U ,   k_ra8_sci_ccr2_bit_abcse2 = 7U ,   k_ra8_sci_ccr2_shift_brr = 8U ,   k_ra8_sci_ccr2_bit_brme = 16U ,   k_ra8_sci_ccr2_shift_cks = 20U ,   k_ra8_sci_ccr2_shift_mddr = 24U }
	Bit positions / shifts in CCR2. More...
enum	ra8_sci_ccr2_mask_t : uint32_t {   k_ra8_sci_ccr2_mask_brr_field = 0x000000FFU << 8U ,   k_ra8_sci_ccr2_mask_brr_byte = 0xFFU ,   k_ra8_sci_ccr2_mask_cks_field = 0x3U << 20U ,   k_ra8_sci_ccr2_mask_mddr_field = 0xFFU << 24U }
	Field masks (post-shift) for CCR2. More...
enum	ra8_sci_ccr2_brr_const_t : uint32_t { k_ra8_sci_brr_async_divisor = 32U }
	Constants used in the BRR formula. More...
enum	ra8_sci_ccr2_mddr_const_t : uint32_t { k_ra8_sci_mddr_default = 0xFFU }
	Modulation-duty-setting constants. More...
enum	ra8_sci_ccr3_bit_t : uint8_t {   k_ra8_sci_ccr3_bit_cpha = 0U ,   k_ra8_sci_ccr3_bit_cpol = 1U ,   k_ra8_sci_ccr3_bit_bpen = 7U ,   k_ra8_sci_ccr3_shift_chr = 8U ,   k_ra8_sci_ccr3_bit_lsbf = 12U ,   k_ra8_sci_ccr3_bit_sinv = 13U ,   k_ra8_sci_ccr3_bit_stp = 14U ,   k_ra8_sci_ccr3_bit_rxdesel = 15U ,   k_ra8_sci_ccr3_shift_mod = 16U ,   k_ra8_sci_ccr3_bit_mp = 19U ,   k_ra8_sci_ccr3_bit_fm = 20U ,   k_ra8_sci_ccr3_bit_den = 21U ,   k_ra8_sci_ccr3_shift_cke = 24U ,   k_ra8_sci_ccr3_bit_acs0 = 26U ,   k_ra8_sci_ccr3_bit_gm = 28U ,   k_ra8_sci_ccr3_bit_blk = 29U }
	Bit positions / shifts in CCR3. More...
enum	ra8_sci_ccr3_chr_t : uint32_t {   k_ra8_sci_ccr3_chr_9bit_a = 0x0U ,   k_ra8_sci_ccr3_chr_9bit_b = 0x1U ,   k_ra8_sci_ccr3_chr_8bit = 0x2U ,   k_ra8_sci_ccr3_chr_7bit = 0x3U }
	Encoded values for CCR3.CHR[1:0] (HUM Ch 38.2.8, p 2204). More...
enum	ra8_sci_ccr3_mod_t : uint32_t {   k_ra8_sci_ccr3_mod_async = 0x0U ,   k_ra8_sci_ccr3_mod_smartcard = 0x1U ,   k_ra8_sci_ccr3_mod_clocksync = 0x2U ,   k_ra8_sci_ccr3_mod_simple_spi = 0x3U ,   k_ra8_sci_ccr3_mod_simple_iic = 0x4U ,   k_ra8_sci_ccr3_mod_manchester = 0x5U ,   k_ra8_sci_ccr3_mod_simple_lin = 0x6U }
	Encoded values for CCR3.MOD[2:0] (HUM Ch 38.2.8, p 2204). More...
enum	ra8_sci_ccr3_mod_mask_t : uint32_t { k_ra8_sci_ccr3_mask_mod = 0x00070000U }
	Field mask for CCR3.MOD[18:16] (mode select). More...
enum	ra8_sci_xcr0_bit_t : uint8_t {   k_ra8_sci_xcr0_shift_tcss = 0U ,   k_ra8_sci_xcr0_bit_bfe = 8U ,   k_ra8_sci_xcr0_bit_cf0re = 9U ,   k_ra8_sci_xcr0_shift_cf1ds = 10U ,   k_ra8_sci_xcr0_bit_pibe = 12U ,   k_ra8_sci_xcr0_shift_pibs = 13U ,   k_ra8_sci_xcr0_bit_bfoie = 16U ,   k_ra8_sci_xcr0_bit_bcdie = 17U ,   k_ra8_sci_xcr0_bit_bfdie = 20U ,   k_ra8_sci_xcr0_bit_cofie = 21U ,   k_ra8_sci_xcr0_bit_aedie = 22U ,   k_ra8_sci_xcr0_shift_bccs = 24U }
	Bit positions / field shifts in XCR0 (Simple LIN Control 0). More...
enum	ra8_sci_xcr0_tcss_t : uint32_t {   k_ra8_sci_xcr0_tcss_div4 = 0x1U ,   k_ra8_sci_xcr0_tcss_div16 = 0x2U ,   k_ra8_sci_xcr0_tcss_div64 = 0x3U }
	Encoded values for XCR0.TCSS[1:0] (timer count clock source). More...
enum	ra8_sci_xcr1_bit_t : uint8_t {   k_ra8_sci_xcr1_bit_tcst = 0U ,   k_ra8_sci_xcr1_bit_sdst = 4U ,   k_ra8_sci_xcr1_bit_bmen = 5U ,   k_ra8_sci_xcr1_shift_pcf1d = 8U ,   k_ra8_sci_xcr1_shift_scf1d = 16U ,   k_ra8_sci_xcr1_shift_cf1ce = 24U }
	Bit positions / field shifts in XCR1 (Simple LIN Control 1). More...
enum	ra8_sci_xcr2_bit_t : uint8_t {   k_ra8_sci_xcr2_shift_cf0d = 0U ,   k_ra8_sci_xcr2_shift_cf0ce = 8U ,   k_ra8_sci_xcr2_shift_bflw = 16U }
	Field shifts in XCR2 (Simple LIN Control 2). More...
enum	ra8_sci_xcr2_bflw_t : uint32_t {   k_ra8_sci_xcr2_bflw_reset = 0xFFFEU ,   k_ra8_sci_xcr2_bflw_max = 0xFFFEU }
	Break Field length (XCR2.BFLW[15:0]) constants. More...
enum	ra8_sci_xsr0_bit_t : uint8_t {   k_ra8_sci_xsr0_bit_sfsf = 0U ,   k_ra8_sci_xsr0_bit_rxdsf = 1U ,   k_ra8_sci_xsr0_bit_bfof = 8U ,   k_ra8_sci_xsr0_bit_bcdf = 9U ,   k_ra8_sci_xsr0_bit_bfdf = 10U ,   k_ra8_sci_xsr0_bit_cf0mf = 11U ,   k_ra8_sci_xsr0_bit_cf1mf = 12U ,   k_ra8_sci_xsr0_bit_pibdf = 13U ,   k_ra8_sci_xsr0_bit_cof = 14U ,   k_ra8_sci_xsr0_bit_aedf = 15U }
	Bit positions in XSR0 (Simple LIN Status Register 0). More...
enum	ra8_sci_xsr1_field_t : uint32_t {   k_ra8_sci_xsr1_shift_tcnt = 0U ,   k_ra8_sci_xsr1_mask_tcnt = 0xFFFFU }
	Field shift / mask for XSR1 (Simple LIN Status Register 1). More...
enum	ra8_sci_xfclr_bit_t : uint8_t {   k_ra8_sci_xfclr_bit_bfoc = 8U ,   k_ra8_sci_xfclr_bit_bcdc = 9U ,   k_ra8_sci_xfclr_bit_bfdc = 10U ,   k_ra8_sci_xfclr_bit_cf0mc = 11U ,   k_ra8_sci_xfclr_bit_cf1mc = 12U ,   k_ra8_sci_xfclr_bit_pibdc = 13U ,   k_ra8_sci_xfclr_bit_cofc = 14U ,   k_ra8_sci_xfclr_bit_aedc = 15U }
	Bit positions in XFCLR (Simple LIN Flag Clear Register). More...
enum	ra8_sci_xfclr_default_t : uint32_t { k_ra8_sci_xfclr_default = 0x0000FF00U }
	XFCLR "clear-all-LIN-latches" default mask. More...
enum	ra8_sci_csr_bit_t : uint8_t {   k_ra8_sci_csr_bit_ers = 4U ,   k_ra8_sci_csr_bit_rxdmon = 15U ,   k_ra8_sci_csr_bit_dcmf = 16U ,   k_ra8_sci_csr_bit_dper = 17U ,   k_ra8_sci_csr_bit_dfer = 18U ,   k_ra8_sci_csr_bit_orer = 24U ,   k_ra8_sci_csr_bit_mff = 26U ,   k_ra8_sci_csr_bit_per = 27U ,   k_ra8_sci_csr_bit_fer = 28U ,   k_ra8_sci_csr_bit_tdre = 29U ,   k_ra8_sci_csr_bit_tend = 30U ,   k_ra8_sci_csr_bit_rdrf = 31U }
	Bit positions in CSR. More...
enum	ra8_sci_cfclr_bit_t : uint8_t {   k_ra8_sci_cfclr_bit_ersc = 4U ,   k_ra8_sci_cfclr_bit_dcmfc = 16U ,   k_ra8_sci_cfclr_bit_dperc = 17U ,   k_ra8_sci_cfclr_bit_dferc = 18U ,   k_ra8_sci_cfclr_bit_orerc = 24U ,   k_ra8_sci_cfclr_bit_mffc = 26U ,   k_ra8_sci_cfclr_bit_perc = 27U ,   k_ra8_sci_cfclr_bit_ferc = 28U ,   k_ra8_sci_cfclr_bit_tdrec = 29U ,   k_ra8_sci_cfclr_bit_rdrfc = 31U }
	Bit positions in CFCLR. More...
enum	ra8_sci_cfclr_default_t : uint32_t { k_ra8_sci_cfclr_default = 0x9D070010U }
	CFCLR "clear-all" default mask. More...
enum	ra8_sci_ffclr_bit_t : uint8_t { k_ra8_sci_ffclr_bit_drc = 0U }
	Bit positions in FFCLR. More...
enum	ra8_sci_ffclr_default_t : uint32_t { k_ra8_sci_ffclr_default = 0x00000001U }
	FFCLR "clear-all" default mask. More...
enum	ra8_sci_data_mask_t : uint32_t {   k_ra8_sci_rdr_mask_data8 = 0xFFU ,   k_ra8_sci_tdr_mask_data8 = 0xFFU }
	Masks for RDR/TDR data fields (HUM 38.2.2 p 2180, 38.2.3 p 2181). More...

Functions
static volatile r_sci_regs_t *	ra8_sci (uint8_t channel)
	Get pointer to SCI_B channel N (0..9).

Detailed Description

SCI_B (Serial Communication Interface, B variant) register layout

for the RA8D2.

The RA8D2 ships the SCI_B variant of the SCI peripheral (HUM Ch 38 "Serial Communications Interface (SCI)" intro page literally states "This is the SCI_B version of the SCI peripheral module"). SCI_B is register-incompatible with the legacy 8-bit SCI: every control, data, status, and clear register is 32-bit, and the bit layout is different.

RA8D2 has 10 SCI_B channels (SCI0..SCI9) at base 0x40358000 (Secure alias) / 0x50358000 (Non-Secure alias) with a stride of 0x100 per channel. Each channel covers a 256-byte window. This header models the asynchronous-UART-relevant subset of that window plus all per-mode satellite registers cited by the register summary table; bits required by Manchester / Simple LIN / Simple IIC / Smart-card sub-modes are not enumerated here and will be added when those modes get drivers.

Register map (per channel, partial)

Offset	Name	Width	Purpose
0x00	RDR	32	Receive Data Register
0x04	TDR	32	Transmit Data Register
0x08	CCR0	32	Common Control Register 0 (TE / RE / *IE)
0x0C	CCR1	32	Common Control Register 1 (parity / inv / NF)
0x10	CCR2	32	Common Control Register 2 (BRR / CKS / MDDR)
0x14	CCR3	32	Common Control Register 3 (mode / FIFO / CKE)
0x18	CCR4	32	Common Control Register 4 (sample / cmpd)
0x1C	CESR	8	Communication Enable Status (TIST / RIST)
0x20	ICR	32	Simple IIC Control Register
0x24	FCR	32	FIFO Control Register
0x2C	MCR	32	Manchester Control Register
0x30	DCR	32	Driver Control Register (DE assert / negate)
0x34	XCR0	32	Simple LIN Control Register 0
0x38	XCR1	32	Simple LIN Control Register 1
0x3C	XCR2	32	Simple LIN Control Register 2
0x48	CSR	32	Common Status Register (TDRE / TEND / *ER)
0x4C	ISR	32	Simple IIC Status Register
0x50	FRSR	32	FIFO Receive Status Register
0x54	FTSR	32	FIFO Transmit Status Register
0x58	MSR	32	Manchester Status Register
0x5C	XSR0	32	Simple LIN Status Register 0
0x60	XSR1	32	Simple LIN Status Register 1
0x68	CFCLR	32	Common Flag Clear Register
0x6C	ICFCLR	32	Simple IIC Flag Clear Register
0x70	FFCLR	32	FIFO Flag Clear Register
0x74	MFCLR	32	Manchester Flag Clear Register
0x78	XFCLR	32	Simple LIN Flag Clear Register

Citations are to the HUM Rev 1.30 (Feb 2026), section 38 starting at PDF page 2174.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_sci_regs.h.

Enumeration Type Documentation

ra8_sci_base_addr_t

enum ra8_sci_base_addr_t : uintptr_t

Per-channel SCI_B base addresses (Secure alias).

HUM Ch 38.2.1 "RSR : Receive Shift Register", p 2179 declares SCIn_B = 0x4035_8000 + 0x0100 * n. The non-secure alias is 0x5035_8000 + 0x0100 * n; this driver runs in the Secure world for now, so only the Secure alias is enumerated.

Enumerator
k_ra8_sci0_base_addr	RA8 sci0 base address.
k_ra8_sci1_base_addr	RA8 sci1 base address.
k_ra8_sci2_base_addr	RA8 sci2 base address.
k_ra8_sci3_base_addr	RA8 sci3 base address.
k_ra8_sci4_base_addr	RA8 sci4 base address.
k_ra8_sci5_base_addr	RA8 sci5 base address.
k_ra8_sci6_base_addr	RA8 sci6 base address.
k_ra8_sci7_base_addr	RA8 sci7 base address.
k_ra8_sci8_base_addr	RA8 sci8 base address.
k_ra8_sci9_base_addr	RA8 sci9 base address.

Definition at line 88 of file ra8_sci_regs.h.

ra8_sci_ccr0_bit_t

enum ra8_sci_ccr0_bit_t : uint8_t

Bit positions in CCR0.

HUM Ch 38.2.5 "CCR0 : Common Control Register 0", p 2182.

Enumerator
k_ra8_sci_ccr0_bit_re	Receive Enable.
k_ra8_sci_ccr0_bit_te	Transmit Enable.
k_ra8_sci_ccr0_bit_mpie	Multi-Processor Interrupt Enable.
k_ra8_sci_ccr0_bit_dcme	Data Compare Match Enable.
k_ra8_sci_ccr0_bit_idsel	ID Frame Select.
k_ra8_sci_ccr0_bit_rie	Receive Interrupt Enable.
k_ra8_sci_ccr0_bit_tie	Transmit Interrupt Enable.
k_ra8_sci_ccr0_bit_teie	Transmit End Interrupt Enable.
k_ra8_sci_ccr0_bit_sse	SSn Pin Function Enable.

Definition at line 200 of file ra8_sci_regs.h.

ra8_sci_ccr1_bit_t

enum ra8_sci_ccr1_bit_t : uint8_t

Bit positions in CCR1.

HUM Ch 38.2.6 "CCR1 : Common Control Register 1", p 2185.

Enumerator
k_ra8_sci_ccr1_bit_ctse	CTS Enable.
k_ra8_sci_ccr1_bit_ctspen	CTS External Pin Enable.
k_ra8_sci_ccr1_bit_spb2dt	Serial Port Break Data Select.
k_ra8_sci_ccr1_bit_spb2io	Serial Port Break I/O.
k_ra8_sci_ccr1_bit_pe	Parity Enable.
k_ra8_sci_ccr1_bit_pm	Parity Mode (0=even, 1=odd).
k_ra8_sci_ccr1_bit_tinv	TXD Invert.
k_ra8_sci_ccr1_bit_rinv	RXD Invert.
k_ra8_sci_ccr1_bit_splp	Loopback Control.
k_ra8_sci_ccr1_bit_sharps	Half-Duplex Communication Select.
k_ra8_sci_ccr1_bit_nfen	Digital Noise Filter Enable.
k_ra8_sci_ccr1_bit_nfm	Noise Filter Mode.

Definition at line 223 of file ra8_sci_regs.h.

ra8_sci_ccr2_bit_t

enum ra8_sci_ccr2_bit_t : uint8_t

Bit positions / shifts in CCR2.

HUM Ch 38.2.7 "CCR2 : Common Control Register 2", p 2189.

Enumerator
k_ra8_sci_ccr2_bit_bgdm	Baud Rate Generator Double-Speed.
k_ra8_sci_ccr2_bit_abcs	Async Mode Base Clock Select (0=16x).
k_ra8_sci_ccr2_bit_abcse	Async Mode Extended Base Clock.
k_ra8_sci_ccr2_bit_abcse2	Async Mode Extended Base Clock 2.
k_ra8_sci_ccr2_shift_brr	BRR[7:0] field shift.
k_ra8_sci_ccr2_bit_brme	Bit Rate Modulation Enable.
k_ra8_sci_ccr2_shift_cks	CKS[1:0] field shift.
k_ra8_sci_ccr2_shift_mddr	MDDR[7:0] field shift.

Definition at line 249 of file ra8_sci_regs.h.

ra8_sci_ccr2_brr_const_t

enum ra8_sci_ccr2_brr_const_t : uint32_t

Constants used in the BRR formula.

HUM Ch 38.2.7 "CCR2 : Common Control Register 2", p 2189 Table 38.7. For Asynchronous mode with the 16x base clock (ABCS=ABCSE=ABCSE2=BGDM=0), N = (TCLK / (64 * 2^(2n-1) * B)) - 1. With CKS = 0 -> n = 0 -> divisor = 64 * 0.5 = 32. We program CKS = 0 and BGDM = 0 for the "default 16x base clock" path so the effective divisor stays 32 here.

Enumerator
k_ra8_sci_brr_async_divisor	64 * 2^(2*0 - 1) for n = 0.

Definition at line 282 of file ra8_sci_regs.h.

ra8_sci_ccr2_mask_t

enum ra8_sci_ccr2_mask_t : uint32_t

Field masks (post-shift) for CCR2.

Enumerator
k_ra8_sci_ccr2_mask_brr_field	BRR[15:8] in CCR2.
k_ra8_sci_ccr2_mask_brr_byte	8-bit BRR value.
k_ra8_sci_ccr2_mask_cks_field	CKS[21:20] in CCR2.
k_ra8_sci_ccr2_mask_mddr_field	MDDR[31:24].

Definition at line 264 of file ra8_sci_regs.h.

ra8_sci_ccr2_mddr_const_t

enum ra8_sci_ccr2_mddr_const_t : uint32_t

Modulation-duty-setting constants.

HUM Ch 38.2.7 "CCR2 : Common Control Register 2", p 2189. The reset value of MDDR[7:0] is 0xFF; with BRME = 0 the modulation function is disabled and the field is treated as a no-op. We preserve the reset value when re-writing CCR2 so the field stays "modulation off".

Enumerator
k_ra8_sci_mddr_default	MDDR reset value (modulation disabled).

Definition at line 296 of file ra8_sci_regs.h.

ra8_sci_ccr3_bit_t

enum ra8_sci_ccr3_bit_t : uint8_t

Bit positions / shifts in CCR3.

HUM Ch 38.2.8 "CCR3 : Common Control Register 3", p 2203.

Enumerator
k_ra8_sci_ccr3_bit_cpha	Clock Phase (sync only).
k_ra8_sci_ccr3_bit_cpol	Clock Polarity (sync only).
k_ra8_sci_ccr3_bit_bpen	Synchronizer Bypass Enable.
k_ra8_sci_ccr3_shift_chr	CHR[1:0] data-length field.
k_ra8_sci_ccr3_bit_lsbf	LSB First.
k_ra8_sci_ccr3_bit_sinv	Data Invert.
k_ra8_sci_ccr3_bit_stp	Stop Bit Length (0=1, 1=2).
k_ra8_sci_ccr3_bit_rxdesel	Async Start Bit Edge Detect.
k_ra8_sci_ccr3_shift_mod	MOD[2:0] mode select.
k_ra8_sci_ccr3_bit_mp	Multi-Processor mode.
k_ra8_sci_ccr3_bit_fm	FIFO Mode Select.
k_ra8_sci_ccr3_bit_den	RS-485 Driver Enable.
k_ra8_sci_ccr3_shift_cke	CKE[1:0] clock enable.
k_ra8_sci_ccr3_bit_acs0	Async Mode Clock Source.
k_ra8_sci_ccr3_bit_gm	Smart-card GSM Mode.
k_ra8_sci_ccr3_bit_blk	Smart-card Block Transfer.

Definition at line 311 of file ra8_sci_regs.h.

ra8_sci_ccr3_chr_t

enum ra8_sci_ccr3_chr_t : uint32_t

Encoded values for CCR3.CHR[1:0] (HUM Ch 38.2.8, p 2204).

Enumerator
k_ra8_sci_ccr3_chr_9bit_a	00 = 9-bit data.
k_ra8_sci_ccr3_chr_9bit_b	01 = 9-bit data.
k_ra8_sci_ccr3_chr_8bit	10 = 8-bit data (initial value).
k_ra8_sci_ccr3_chr_7bit	11 = 7-bit data.

Definition at line 334 of file ra8_sci_regs.h.

ra8_sci_ccr3_mod_mask_t

enum ra8_sci_ccr3_mod_mask_t : uint32_t

Field mask for CCR3.MOD[18:16] (mode select).

HUM Ch 38.2.8 "CCR3 : Common Control Register 3", p 2203. MOD is a 3-bit field at bit 16; the mask isolates it so a driver can switch operating modes (e.g. async -> Simple LIN) without disturbing the framing bits (LSBF / BPEN / CHR / STP) that share CCR3.

Enumerator
k_ra8_sci_ccr3_mask_mod	MOD[18:16] in CCR3.

Definition at line 364 of file ra8_sci_regs.h.

ra8_sci_ccr3_mod_t

enum ra8_sci_ccr3_mod_t : uint32_t

Encoded values for CCR3.MOD[2:0] (HUM Ch 38.2.8, p 2204).

Enumerator
k_ra8_sci_ccr3_mod_async	Asynchronous (UART/multi-proc).
k_ra8_sci_ccr3_mod_smartcard	Smart Card.
k_ra8_sci_ccr3_mod_clocksync	Clock-synchronous.
k_ra8_sci_ccr3_mod_simple_spi	Simple SPI.
k_ra8_sci_ccr3_mod_simple_iic	Simple IIC.
k_ra8_sci_ccr3_mod_manchester	Manchester.
k_ra8_sci_ccr3_mod_simple_lin	Simple LIN.

Definition at line 345 of file ra8_sci_regs.h.

ra8_sci_cfclr_bit_t

enum ra8_sci_cfclr_bit_t : uint8_t

Bit positions in CFCLR.

HUM Ch 38.2.24 "CFCLR : Common Flag Clear Register", p 2238. Writing 1 to a bit clears the corresponding CSR flag; read returns 0.

Enumerator
k_ra8_sci_cfclr_bit_ersc	Clear CSR.ERS.
k_ra8_sci_cfclr_bit_dcmfc	Clear CSR.DCMF.
k_ra8_sci_cfclr_bit_dperc	Clear CSR.DPER.
k_ra8_sci_cfclr_bit_dferc	Clear CSR.DFER.
k_ra8_sci_cfclr_bit_orerc	Clear CSR.ORER.
k_ra8_sci_cfclr_bit_mffc	Clear CSR.MFF.
k_ra8_sci_cfclr_bit_perc	Clear CSR.PER.
k_ra8_sci_cfclr_bit_ferc	Clear CSR.FER.
k_ra8_sci_cfclr_bit_tdrec	Clear CSR.TDRE.
k_ra8_sci_cfclr_bit_rdrfc	Clear CSR.RDRF.

Definition at line 573 of file ra8_sci_regs.h.

ra8_sci_cfclr_default_t

enum ra8_sci_cfclr_default_t : uint32_t

CFCLR "clear-all" default mask.

HUM Ch 38.2.24 "CFCLR : Common Flag Clear Register", p 2238. Writing 1 to every defined W1C bit (ERSC, DCMFC, DPERC, DFERC, ORERC, MFFC, PERC, FERC, TDREC, RDRFC) clears the matching CSR latches in a single store. The decomposed mask is:

Bit	Name	Value
4	ERSC	0x00000010
16	DCMFC	0x00010000
17	DPERC	0x00020000
18	DFERC	0x00040000
24	ORERC	0x01000000
26	MFFC	0x04000000
27	PERC	0x08000000
28	FERC	0x10000000
29	TDREC	0x20000000
31	RDRFC	0x80000000

Sum = 0x9D070010, matching FSP r_sci_b_uart.c SCI_B_UART_CFCLR_CLEAR_ALL_MASK.

Enumerator
k_ra8_sci_cfclr_default	Clear every W1C bit at once.

Definition at line 611 of file ra8_sci_regs.h.

ra8_sci_csr_bit_t

enum ra8_sci_csr_bit_t : uint8_t

Bit positions in CSR.

HUM Ch 38.2.17 "CSR : Common Status Register", p 2225.

Enumerator
k_ra8_sci_csr_bit_ers	Smart-card Error Signal Status.
k_ra8_sci_csr_bit_rxdmon	RXDn Pin Monitor.
k_ra8_sci_csr_bit_dcmf	Data Compare Match.
k_ra8_sci_csr_bit_dper	Compare-Match Parity Error.
k_ra8_sci_csr_bit_dfer	Compare-Match Framing Error.
k_ra8_sci_csr_bit_orer	Overrun Error.
k_ra8_sci_csr_bit_mff	Mode Fault Error (SPI).
k_ra8_sci_csr_bit_per	Parity Error.
k_ra8_sci_csr_bit_fer	Framing Error.
k_ra8_sci_csr_bit_tdre	Transmit Data Empty.
k_ra8_sci_csr_bit_tend	Transmit End.
k_ra8_sci_csr_bit_rdrf	Receive Data Full.

Definition at line 545 of file ra8_sci_regs.h.

ra8_sci_data_mask_t

enum ra8_sci_data_mask_t : uint32_t

Masks for RDR/TDR data fields (HUM 38.2.2 p 2180, 38.2.3 p 2181).

Enumerator
k_ra8_sci_rdr_mask_data8	RDAT[7:0] for 8-bit reception.
k_ra8_sci_tdr_mask_data8	TDAT[7:0] for 8-bit transmission.

Definition at line 654 of file ra8_sci_regs.h.

ra8_sci_ffclr_bit_t

enum ra8_sci_ffclr_bit_t : uint8_t

Bit positions in FFCLR.

HUM Ch 38.2.26 "FFCLR : FIFO Flag Clear Register", p 2239. Only DRC (bit 0) is defined; writing 1 clears the FIFO data-ready (DR) latch in FRSR. Other bits read as 0.

Enumerator
k_ra8_sci_ffclr_bit_drc	Clear FRSR.DR.

Definition at line 628 of file ra8_sci_regs.h.

ra8_sci_ffclr_default_t

enum ra8_sci_ffclr_default_t : uint32_t

FFCLR "clear-all" default mask.

HUM Ch 38.2.26 "FFCLR : FIFO Flag Clear Register", p 2239. The only defined W1C bit is DRC (bit 0); a write of 0x00000001 mirrors FSP r_sci_b_uart.c SCI_B_UART_FFCLR_CLEAR_ALL_MASK.

Enumerator
k_ra8_sci_ffclr_default	Clear FRSR.DR latch.

Definition at line 641 of file ra8_sci_regs.h.

ra8_sci_limits_t

enum ra8_sci_limits_t : uint16_t

Channel-count and stride constants.

Enumerator
k_ra8_sci_channel_count	SCI0..SCI9.
k_ra8_sci_channel_max	Highest valid channel index.
k_ra8_sci_channel_stride	Bytes between SCI channels.

Definition at line 105 of file ra8_sci_regs.h.

ra8_sci_xcr0_bit_t

enum ra8_sci_xcr0_bit_t : uint8_t

Bit positions / field shifts in XCR0 (Simple LIN Control 0).

HUM Ch 38.2.14 "XCR0 : Simple LIN Control Register 0", p 2220. Only the fields the Simple-LIN commander path programs are enumerated; the interrupt-enable and bus-conflict fields are named for completeness.

Enumerator
k_ra8_sci_xcr0_shift_tcss	TCSS[1:0] timer count clock source.
k_ra8_sci_xcr0_bit_bfe	Break Field Enable.
k_ra8_sci_xcr0_bit_cf0re	Control Field 0 Enable.
k_ra8_sci_xcr0_shift_cf1ds	CF1DS[1:0] CF1 compare-data select.
k_ra8_sci_xcr0_bit_pibe	Priority Interrupt Bit Enable.
k_ra8_sci_xcr0_shift_pibs	PIBS[2:0] priority interrupt bit.
k_ra8_sci_xcr0_bit_bfoie	Break Field Output Completion IE.
k_ra8_sci_xcr0_bit_bcdie	Bus Conflict Detection IE.
k_ra8_sci_xcr0_bit_bfdie	Break Field Detection IE.
k_ra8_sci_xcr0_bit_cofie	Counter Overflow IE.
k_ra8_sci_xcr0_bit_aedie	Active Edge Detection IE.
k_ra8_sci_xcr0_shift_bccs	BCCS[1:0] bus-conflict clock.

Definition at line 381 of file ra8_sci_regs.h.

ra8_sci_xcr0_tcss_t

enum ra8_sci_xcr0_tcss_t : uint32_t

Encoded values for XCR0.TCSS[1:0] (timer count clock source).

HUM Ch 38.2.14 "XCR0 : Simple LIN Control Register 0", p 2221. Selects the divider applied to the Simple-LIN module timer clock (TCLK) that times the break field. Encoding 0b00 is not defined; only the three dividers below are legal.

Enumerator
k_ra8_sci_xcr0_tcss_div4	TCLK / 4.
k_ra8_sci_xcr0_tcss_div16	TCLK / 16.
k_ra8_sci_xcr0_tcss_div64	TCLK / 64.

Definition at line 405 of file ra8_sci_regs.h.

ra8_sci_xcr1_bit_t

enum ra8_sci_xcr1_bit_t : uint8_t

Bit positions / field shifts in XCR1 (Simple LIN Control 1).

HUM Ch 38.2.15 "XCR1 : Simple LIN Control Register 1", p 2223.

Enumerator
k_ra8_sci_xcr1_bit_tcst	Break Field Output Timer Count Start.
k_ra8_sci_xcr1_bit_sdst	Start Frame Detection Enable.
k_ra8_sci_xcr1_bit_bmen	Bit Rate Measurement Enable.
k_ra8_sci_xcr1_shift_pcf1d	PCF1D[7:0] priority compare data CF1.
k_ra8_sci_xcr1_shift_scf1d	SCF1D[7:0] secondary compare data CF1.
k_ra8_sci_xcr1_shift_cf1ce	CF1CE[7:0] CF1 compare bit enable.

Definition at line 417 of file ra8_sci_regs.h.

ra8_sci_xcr2_bflw_t

enum ra8_sci_xcr2_bflw_t : uint32_t

Break Field length (XCR2.BFLW[15:0]) constants.

HUM Ch 38.2.16 "XCR2 : Simple LIN Control Register 2", p 2224. The break field dominant time is (BFLW + 1) x the XCR0.TCSS timer clock period; the LIN standard requires at least 13 dominant bits. The reset value is 0xFFFE and 0xFFFF is a prohibited setting, so 0xFFFE is also the upper limit.

Enumerator
k_ra8_sci_xcr2_bflw_reset	BFLW reset value.
k_ra8_sci_xcr2_bflw_max	Highest legal BFLW (0xFFFF banned).

Definition at line 448 of file ra8_sci_regs.h.

ra8_sci_xcr2_bit_t

enum ra8_sci_xcr2_bit_t : uint8_t

Field shifts in XCR2 (Simple LIN Control 2).

HUM Ch 38.2.16 "XCR2 : Simple LIN Control Register 2", p 2224.

Enumerator
k_ra8_sci_xcr2_shift_cf0d	CF0D[7:0] Control Field 0 compare data.
k_ra8_sci_xcr2_shift_cf0ce	CF0CE[7:0] CF0 compare bit enable.
k_ra8_sci_xcr2_shift_bflw	BFLW[15:0] Break Field length.

Definition at line 432 of file ra8_sci_regs.h.

ra8_sci_xfclr_bit_t

enum ra8_sci_xfclr_bit_t : uint8_t

Bit positions in XFCLR (Simple LIN Flag Clear Register).

HUM Ch 38.2.28 "XFCLR : Simple LIN Flag Clear Register", p 2240. Writing 1 to a bit clears the correspondingly-named XSR0 flag; the register reads back 0. The clear bits occupy the same bit positions (8..15) as the XSR0 flags they clear.

Enumerator
k_ra8_sci_xfclr_bit_bfoc	Clear XSR0.BFOF.
k_ra8_sci_xfclr_bit_bcdc	Clear XSR0.BCDF.
k_ra8_sci_xfclr_bit_bfdc	Clear XSR0.BFDF.
k_ra8_sci_xfclr_bit_cf0mc	Clear XSR0.CF0MF.
k_ra8_sci_xfclr_bit_cf1mc	Clear XSR0.CF1MF.
k_ra8_sci_xfclr_bit_pibdc	Clear XSR0.PIBDF.
k_ra8_sci_xfclr_bit_cofc	Clear XSR0.COF.
k_ra8_sci_xfclr_bit_aedc	Clear XSR0.AEDF.

Definition at line 510 of file ra8_sci_regs.h.

ra8_sci_xfclr_default_t

enum ra8_sci_xfclr_default_t : uint32_t

XFCLR "clear-all-LIN-latches" default mask.

HUM Ch 38.2.28 "XFCLR : Simple LIN Flag Clear Register", p 2240. Writing 1 to every defined W1C bit (BFOC, BCDC, BFDC, CF0MC, CF1MC, PIBDC, COFC, AEDC – bits 8..15) clears all matching XSR0 latches in one store. The sum of bits 8..15 is 0x0000FF00.

Enumerator
k_ra8_sci_xfclr_default	Clear every LIN W1C latch at once.

Definition at line 530 of file ra8_sci_regs.h.

ra8_sci_xsr0_bit_t

enum ra8_sci_xsr0_bit_t : uint8_t

Bit positions in XSR0 (Simple LIN Status Register 0).

HUM Ch 38.2.22 "XSR0 : Simple LIN Status Register 0", p 2235. These read-only flags report the Simple-LIN receiver's view of an inbound Start Frame: the responder polls BFDF for the break field, AEDF for the sync-field active edge, and SFSF for the detection-in-progress state. Latched flags are cleared through the matching XFCLR bit (see ra8_sci_xfclr_bit_t).

Enumerator
k_ra8_sci_xsr0_bit_sfsf	Start Frame Status (1 = detecting).
k_ra8_sci_xsr0_bit_rxdsf	RXDn Input Status.
k_ra8_sci_xsr0_bit_bfof	Break Field Output Completion Flag.
k_ra8_sci_xsr0_bit_bcdf	Bus Conflict Detection Flag.
k_ra8_sci_xsr0_bit_bfdf	Break Field Detection Flag (1 = seen).
k_ra8_sci_xsr0_bit_cf0mf	Control Field 0 Compare Match Flag.
k_ra8_sci_xsr0_bit_cf1mf	Control Field 1 Compare Match Flag.
k_ra8_sci_xsr0_bit_pibdf	Priority Interrupt Bit Detection Flag.
k_ra8_sci_xsr0_bit_cof	Counter Overflow Flag.
k_ra8_sci_xsr0_bit_aedf	Active Edge Detection Flag (sync edge).

Definition at line 469 of file ra8_sci_regs.h.

ra8_sci_xsr1_field_t

enum ra8_sci_xsr1_field_t : uint32_t

Field shift / mask for XSR1 (Simple LIN Status Register 1).

HUM Ch 38.2.23 "XSR1 : Simple LIN Status Register 1", p 2237. XSR1 holds only TCNT[15:0], the 16-bit timer capture value latched from the break-field / sync-field measurement. Reading XSR1 releases the capture-hold so the next valid edge can be captured.

Enumerator
k_ra8_sci_xsr1_shift_tcnt	TCNT[15:0] field shift.
k_ra8_sci_xsr1_mask_tcnt	TCNT[15:0] field mask.

Definition at line 491 of file ra8_sci_regs.h.

Function Documentation

ra8_sci()

volatile r_sci_regs_t * ra8_sci ( uint8_t channel )

inlinestatic

Get pointer to SCI_B channel N (0..9).

Parameters

[in]

channel

SCI channel index (0..9).

Returns

Volatile pointer to the channel's register window, or nullptr if channel is out of range.

Precondition

Caller has verified the SCI module's MSTP gate is open.

Postcondition

No side effects; pointer arithmetic only.

Definition at line 180 of file ra8_sci_regs.h.

References k_ra8_sci0_base_addr, k_ra8_sci_channel_max, and k_ra8_sci_channel_stride.

Referenced by internal_reg(), ra8_sci_dispatch_rxi(), ra8_sci_dispatch_txi(), ra8_sci_lin_break_detected(), ra8_sci_lin_clear_status(), ra8_sci_lin_init(), ra8_sci_lin_read_response(), ra8_sci_lin_send_break(), ra8_sci_lin_send_header(), ra8_sci_lin_send_response(), ra8_sci_lin_wait_break(), ra8_sci_read_dma(), ra8_sci_spi_deinit(), ra8_sci_spi_init(), ra8_sci_spi_set_clock(), ra8_sci_spi_xfer8(), and ra8_sci_write_dma().