ra8_sci_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
 
/* =============================================================================
 * Base addresses + layout
 * =============================================================================
 */

typedef enum : uintptr_t {
  k_ra8_sci0_base_addr = 0x40358000UL, 
  k_ra8_sci1_base_addr = 0x40358100UL, 
  k_ra8_sci2_base_addr = 0x40358200UL, 
  k_ra8_sci3_base_addr = 0x40358300UL, 
  k_ra8_sci4_base_addr = 0x40358400UL, 
  k_ra8_sci5_base_addr = 0x40358500UL, 
  k_ra8_sci6_base_addr = 0x40358600UL, 
  k_ra8_sci7_base_addr = 0x40358700UL, 
  k_ra8_sci8_base_addr = 0x40358800UL, 
  k_ra8_sci9_base_addr = 0x40358900UL, 
} ra8_sci_base_addr_t;

typedef enum : uint16_t {
  k_ra8_sci_channel_count  = 10U,    
  k_ra8_sci_channel_max    = 9U,     
  k_ra8_sci_channel_stride = 0x100U, 
} ra8_sci_limits_t;
 
/* =============================================================================
 * Register layout (per channel)
 * =============================================================================
 */

typedef struct {
  volatile uint32_t RDR;      
  volatile uint32_t TDR;      
  volatile uint32_t CCR0;     
  volatile uint32_t CCR1;     
  volatile uint32_t CCR2;     
  volatile uint32_t CCR3;     
  volatile uint32_t CCR4;     
  volatile uint32_t CESR;     
  volatile uint32_t ICR;      
  volatile uint32_t FCR;      
  volatile uint32_t _r_28;    
  volatile uint32_t MCR;      
  volatile uint32_t DCR;      
  volatile uint32_t XCR0;     
  volatile uint32_t XCR1;     
  volatile uint32_t XCR2;     
  volatile uint32_t _r_40[2]; 
  volatile uint32_t CSR;      
  volatile uint32_t ISR;      
  volatile uint32_t FRSR;     
  volatile uint32_t FTSR;     
  volatile uint32_t MSR;      
  volatile uint32_t XSR0;     
  volatile uint32_t XSR1;     
  volatile uint32_t _r_64;    
  volatile uint32_t CFCLR;    
  volatile uint32_t ICFCLR;   
  volatile uint32_t FFCLR;    
  volatile uint32_t MFCLR;    
  volatile uint32_t XFCLR;    
} r_sci_regs_t;
 
/* =============================================================================
 * Accessors
 * =============================================================================
 */

RA8_HW_REGISTER_ACCESS
static inline volatile r_sci_regs_t* ra8_sci(uint8_t channel)
{
  if (channel > k_ra8_sci_channel_max) {
    return nullptr;
  }
  return (volatile r_sci_regs_t*)(k_ra8_sci0_base_addr +
                                  ((uintptr_t)channel * (uintptr_t)k_ra8_sci_channel_stride));
}
 
/* =============================================================================
 * CCR0 -- Common Control Register 0
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_ccr0_bit_re    = 0U,  
  k_ra8_sci_ccr0_bit_te    = 4U,  
  k_ra8_sci_ccr0_bit_mpie  = 8U,  
  k_ra8_sci_ccr0_bit_dcme  = 9U,  
  k_ra8_sci_ccr0_bit_idsel = 10U, 
  k_ra8_sci_ccr0_bit_rie   = 16U, 
  k_ra8_sci_ccr0_bit_tie   = 20U, 
  k_ra8_sci_ccr0_bit_teie  = 21U, 
  k_ra8_sci_ccr0_bit_sse   = 24U, 
} ra8_sci_ccr0_bit_t;
 
/* =============================================================================
 * CCR1 -- Common Control Register 1
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_ccr1_bit_ctse   = 0U,  
  k_ra8_sci_ccr1_bit_ctspen = 1U,  
  k_ra8_sci_ccr1_bit_spb2dt = 4U,  
  k_ra8_sci_ccr1_bit_spb2io = 5U,  
  k_ra8_sci_ccr1_bit_pe     = 8U,  
  k_ra8_sci_ccr1_bit_pm     = 9U,  
  k_ra8_sci_ccr1_bit_tinv   = 12U, 
  k_ra8_sci_ccr1_bit_rinv   = 13U, 
  k_ra8_sci_ccr1_bit_splp   = 16U, 
  k_ra8_sci_ccr1_bit_sharps = 20U, 
  k_ra8_sci_ccr1_bit_nfen   = 28U, 
  k_ra8_sci_ccr1_bit_nfm    = 29U, 
} ra8_sci_ccr1_bit_t;
 
/* =============================================================================
 * CCR2 -- Common Control Register 2 (BRR / clock select / MDDR)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_ccr2_bit_bgdm   = 4U,  
  k_ra8_sci_ccr2_bit_abcs   = 5U,  
  k_ra8_sci_ccr2_bit_abcse  = 6U,  
  k_ra8_sci_ccr2_bit_abcse2 = 7U,  
  k_ra8_sci_ccr2_shift_brr  = 8U,  
  k_ra8_sci_ccr2_bit_brme   = 16U, 
  k_ra8_sci_ccr2_shift_cks  = 20U, 
  k_ra8_sci_ccr2_shift_mddr = 24U, 
} ra8_sci_ccr2_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_ccr2_mask_brr_field  = 0x000000FFU << 8U, 
  k_ra8_sci_ccr2_mask_brr_byte   = 0xFFU,             
  k_ra8_sci_ccr2_mask_cks_field  = 0x3U << 20U,       
  k_ra8_sci_ccr2_mask_mddr_field = 0xFFU << 24U,      
} ra8_sci_ccr2_mask_t;

typedef enum : uint32_t {
  k_ra8_sci_brr_async_divisor = 32U, 
} ra8_sci_ccr2_brr_const_t;

typedef enum : uint32_t {
  k_ra8_sci_mddr_default = 0xFFU, 
} ra8_sci_ccr2_mddr_const_t;
 
/* =============================================================================
 * CCR3 -- Common Control Register 3 (mode / FIFO / clock-enable)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_ccr3_bit_cpha    = 0U,  
  k_ra8_sci_ccr3_bit_cpol    = 1U,  
  k_ra8_sci_ccr3_bit_bpen    = 7U,  
  k_ra8_sci_ccr3_shift_chr   = 8U,  
  k_ra8_sci_ccr3_bit_lsbf    = 12U, 
  k_ra8_sci_ccr3_bit_sinv    = 13U, 
  k_ra8_sci_ccr3_bit_stp     = 14U, 
  k_ra8_sci_ccr3_bit_rxdesel = 15U, 
  k_ra8_sci_ccr3_shift_mod   = 16U, 
  k_ra8_sci_ccr3_bit_mp      = 19U, 
  k_ra8_sci_ccr3_bit_fm      = 20U, 
  k_ra8_sci_ccr3_bit_den     = 21U, 
  k_ra8_sci_ccr3_shift_cke   = 24U, 
  k_ra8_sci_ccr3_bit_acs0    = 26U, 
  k_ra8_sci_ccr3_bit_gm      = 28U, 
  k_ra8_sci_ccr3_bit_blk     = 29U, 
} ra8_sci_ccr3_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_ccr3_chr_9bit_a = 0x0U, 
  k_ra8_sci_ccr3_chr_9bit_b = 0x1U, 
  k_ra8_sci_ccr3_chr_8bit   = 0x2U, 
  k_ra8_sci_ccr3_chr_7bit   = 0x3U, 
} ra8_sci_ccr3_chr_t;

typedef enum : uint32_t {
  k_ra8_sci_ccr3_mod_async      = 0x0U, 
  k_ra8_sci_ccr3_mod_smartcard  = 0x1U, 
  k_ra8_sci_ccr3_mod_clocksync  = 0x2U, 
  k_ra8_sci_ccr3_mod_simple_spi = 0x3U, 
  k_ra8_sci_ccr3_mod_simple_iic = 0x4U, 
  k_ra8_sci_ccr3_mod_manchester = 0x5U, 
  k_ra8_sci_ccr3_mod_simple_lin = 0x6U, 
} ra8_sci_ccr3_mod_t;

typedef enum : uint32_t {
  k_ra8_sci_ccr3_mask_mod = 0x00070000U, 
} ra8_sci_ccr3_mod_mask_t;
 
/* =============================================================================
 * XCR0 / XCR1 / XCR2 -- Simple LIN control registers
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_xcr0_shift_tcss  = 0U,  
  k_ra8_sci_xcr0_bit_bfe     = 8U,  
  k_ra8_sci_xcr0_bit_cf0re   = 9U,  
  k_ra8_sci_xcr0_shift_cf1ds = 10U, 
  k_ra8_sci_xcr0_bit_pibe    = 12U, 
  k_ra8_sci_xcr0_shift_pibs  = 13U, 
  k_ra8_sci_xcr0_bit_bfoie   = 16U, 
  k_ra8_sci_xcr0_bit_bcdie   = 17U, 
  k_ra8_sci_xcr0_bit_bfdie   = 20U, 
  k_ra8_sci_xcr0_bit_cofie   = 21U, 
  k_ra8_sci_xcr0_bit_aedie   = 22U, 
  k_ra8_sci_xcr0_shift_bccs  = 24U, 
} ra8_sci_xcr0_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_xcr0_tcss_div4  = 0x1U, 
  k_ra8_sci_xcr0_tcss_div16 = 0x2U, 
  k_ra8_sci_xcr0_tcss_div64 = 0x3U, 
} ra8_sci_xcr0_tcss_t;

typedef enum : uint8_t {
  k_ra8_sci_xcr1_bit_tcst    = 0U,  
  k_ra8_sci_xcr1_bit_sdst    = 4U,  
  k_ra8_sci_xcr1_bit_bmen    = 5U,  
  k_ra8_sci_xcr1_shift_pcf1d = 8U,  
  k_ra8_sci_xcr1_shift_scf1d = 16U, 
  k_ra8_sci_xcr1_shift_cf1ce = 24U, 
} ra8_sci_xcr1_bit_t;

typedef enum : uint8_t {
  k_ra8_sci_xcr2_shift_cf0d  = 0U,  
  k_ra8_sci_xcr2_shift_cf0ce = 8U,  
  k_ra8_sci_xcr2_shift_bflw  = 16U, 
} ra8_sci_xcr2_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_xcr2_bflw_reset = 0xFFFEU, 
  k_ra8_sci_xcr2_bflw_max   = 0xFFFEU, 
} ra8_sci_xcr2_bflw_t;
 
/* =============================================================================
 * XSR0 / XSR1 -- Simple LIN status registers
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_xsr0_bit_sfsf  = 0U,  
  k_ra8_sci_xsr0_bit_rxdsf = 1U,  
  k_ra8_sci_xsr0_bit_bfof  = 8U,  
  k_ra8_sci_xsr0_bit_bcdf  = 9U,  
  k_ra8_sci_xsr0_bit_bfdf  = 10U, 
  k_ra8_sci_xsr0_bit_cf0mf = 11U, 
  k_ra8_sci_xsr0_bit_cf1mf = 12U, 
  k_ra8_sci_xsr0_bit_pibdf = 13U, 
  k_ra8_sci_xsr0_bit_cof   = 14U, 
  k_ra8_sci_xsr0_bit_aedf  = 15U, 
} ra8_sci_xsr0_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_xsr1_shift_tcnt = 0U,      
  k_ra8_sci_xsr1_mask_tcnt  = 0xFFFFU, 
} ra8_sci_xsr1_field_t;
 
/* =============================================================================
 * XFCLR -- Simple LIN Flag Clear Register
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_xfclr_bit_bfoc  = 8U,  
  k_ra8_sci_xfclr_bit_bcdc  = 9U,  
  k_ra8_sci_xfclr_bit_bfdc  = 10U, 
  k_ra8_sci_xfclr_bit_cf0mc = 11U, 
  k_ra8_sci_xfclr_bit_cf1mc = 12U, 
  k_ra8_sci_xfclr_bit_pibdc = 13U, 
  k_ra8_sci_xfclr_bit_cofc  = 14U, 
  k_ra8_sci_xfclr_bit_aedc  = 15U, 
} ra8_sci_xfclr_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_xfclr_default = 0x0000FF00U, 
} ra8_sci_xfclr_default_t;
 
/* =============================================================================
 * CSR -- Common Status Register
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_csr_bit_ers    = 4U,  
  k_ra8_sci_csr_bit_rxdmon = 15U, 
  k_ra8_sci_csr_bit_dcmf   = 16U, 
  k_ra8_sci_csr_bit_dper   = 17U, 
  k_ra8_sci_csr_bit_dfer   = 18U, 
  k_ra8_sci_csr_bit_orer   = 24U, 
  k_ra8_sci_csr_bit_mff    = 26U, 
  k_ra8_sci_csr_bit_per    = 27U, 
  k_ra8_sci_csr_bit_fer    = 28U, 
  k_ra8_sci_csr_bit_tdre   = 29U, 
  k_ra8_sci_csr_bit_tend   = 30U, 
  k_ra8_sci_csr_bit_rdrf   = 31U, 
} ra8_sci_csr_bit_t;
 
/* =============================================================================
 * CFCLR -- Common Flag Clear Register
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_cfclr_bit_ersc  = 4U,  
  k_ra8_sci_cfclr_bit_dcmfc = 16U, 
  k_ra8_sci_cfclr_bit_dperc = 17U, 
  k_ra8_sci_cfclr_bit_dferc = 18U, 
  k_ra8_sci_cfclr_bit_orerc = 24U, 
  k_ra8_sci_cfclr_bit_mffc  = 26U, 
  k_ra8_sci_cfclr_bit_perc  = 27U, 
  k_ra8_sci_cfclr_bit_ferc  = 28U, 
  k_ra8_sci_cfclr_bit_tdrec = 29U, 
  k_ra8_sci_cfclr_bit_rdrfc = 31U, 
} ra8_sci_cfclr_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_cfclr_default = 0x9D070010U, 
} ra8_sci_cfclr_default_t;
 
/* =============================================================================
 * FFCLR -- FIFO Flag Clear Register
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sci_ffclr_bit_drc = 0U, 
} ra8_sci_ffclr_bit_t;

typedef enum : uint32_t {
  k_ra8_sci_ffclr_default = 0x00000001U, 
} ra8_sci_ffclr_default_t;
 
/* =============================================================================
 * RDR / TDR field masks
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_sci_rdr_mask_data8 = 0xFFU, 
  k_ra8_sci_tdr_mask_data8 = 0xFFU, 
} ra8_sci_data_mask_t;
 
#ifdef __cplusplus
}
#endif