ra8_rtc_regs.h File Reference

Real-Time Clock (RTC) register layout for the Renesas RA8D2. More...

#include <stddef.h>
#include <stdint.h>

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Data Structures
struct	r_rtc_regs_t
	RTC register window matching FSP R_RTC_Type byte-for-byte. More...

Enumerations
enum	ra8_rtc_addr_t : uintptr_t { k_ra8_rtc_base_addr = 0x40202000UL }
enum	ra8_rtc_layout_t : uint8_t {   k_ra8_rtc_layout_size = 0x80U ,   k_ra8_rtc_layout_off_rcr1 = 0x22U ,   k_ra8_rtc_layout_off_rcr2 = 0x24U ,   k_ra8_rtc_layout_off_rcr4 = 0x28U ,   k_ra8_rtc_layout_off_rfrh = 0x2AU ,   k_ra8_rtc_layout_off_radj = 0x2EU ,   k_ra8_rtc_layout_off_rtccr = 0x40U ,   k_ra8_rtc_layout_off_cp = 0x50U }
	Authoritative struct offsets used by the layout asserts below. More...
enum	ra8_rcr1_bit_t : uint8_t {   k_ra8_rcr1_bit_aie = 0U ,   k_ra8_rcr1_bit_cie = 1U ,   k_ra8_rcr1_bit_pie = 2U ,   k_ra8_rcr1_bit_rtcos = 3U ,   k_ra8_rcr1_bit_pes_lo = 4U }
	Bit positions in RCR1 (HUM Ch 26.2.3 p 1229). More...
enum	ra8_rcr2_bit_t : uint8_t {   k_ra8_rcr2_bit_start = 0U ,   k_ra8_rcr2_bit_reset = 1U ,   k_ra8_rcr2_bit_adj30 = 2U ,   k_ra8_rcr2_bit_rtcoe = 3U ,   k_ra8_rcr2_bit_aadje = 4U ,   k_ra8_rcr2_bit_aadjp = 5U ,   k_ra8_rcr2_bit_hr24 = 6U ,   k_ra8_rcr2_bit_cntmd = 7U }
	Bit positions in RCR2 (HUM Ch 26.2.4 p 1230). More...
enum	ra8_rcr4_bit_t : uint8_t {   k_ra8_rcr4_bit_rcksel = 0U ,   k_ra8_rcr4_bit_ropsel = 7U }
	Bit positions in RCR4 (HUM Ch 26.2.6 p 1232 area). More...

Functions
static volatile r_rtc_regs_t *	ra8_rtc (void)
	Get pointer to the RTC block.

Detailed Description

Real-Time Clock (RTC) register layout for the Renesas RA8D2.

RTC block at 0x40202000. Layout re-derived against FSP R_RTC_Type (BSP header R7KA8D2KF_core0.h, size 128 / 0x80) and cross-checked against HUM Ch 26 "Realtime Clock (RTC)" pages 1219..1255.

Two operating modes:

• Calendar mode (BCD): year / month / day / day-of-week / hour / minute / second registers (RSECCNT..RYRCNT).
• Binary counter mode: 32-bit up-counter aliased over the calendar registers as BCNT0..BCNT3.

Important offset notes vs the older spin of this header:

• There is no RCR3 register on RA8D2. The control registers are RCR1 (+0x22), RCR2 (+0x24), and RCR4 (+0x28). The slot at +0x26 is reserved.
• RCR2 bit assignments per HUM Ch 26.2.4 are START.0, RESET.1, ADJ30.2, RTCOE.3, AADJE.4, AADJP.5, HR24.6, CNTMD.7.

All time/date count and alarm registers are BCD-encoded. The RTC clock source is selected in CGC (sub-clock or LOCO) before this driver is brought up.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_rtc_regs.h.

Enumeration Type Documentation

ra8_rcr1_bit_t

enum ra8_rcr1_bit_t : uint8_t

Bit positions in RCR1 (HUM Ch 26.2.3 p 1229).

Enumerator
k_ra8_rcr1_bit_aie	Alarm interrupt enable.
k_ra8_rcr1_bit_cie	Carry interrupt enable.
k_ra8_rcr1_bit_pie	Periodic interrupt enable.
k_ra8_rcr1_bit_rtcos	RTCOUT output select.
k_ra8_rcr1_bit_pes_lo	PES[3:0] periodic select (b4..b7).

Definition at line 168 of file ra8_rtc_regs.h.

ra8_rcr2_bit_t

enum ra8_rcr2_bit_t : uint8_t

Bit positions in RCR2 (HUM Ch 26.2.4 p 1230).

Re-derived against FSP R_RTC_Type::RCR2_b: START.0, RESET.1, ADJ30.2, RTCOE.3, AADJE.4, AADJP.5, HR24.6, CNTMD.7. The previous spin of this enum had aadje at bit 5; that was wrong – bit 4 is AADJE, bit 5 is AADJP.

Enumerator
k_ra8_rcr2_bit_start	0=stop, 1=run.
k_ra8_rcr2_bit_reset	Software reset (write 1, auto-clear).
k_ra8_rcr2_bit_adj30	30-second adjustment.
k_ra8_rcr2_bit_rtcoe	RTCOUT output enable.
k_ra8_rcr2_bit_aadje	Auto-adjust enable.
k_ra8_rcr2_bit_aadjp	Auto-adjust period select.
k_ra8_rcr2_bit_hr24	1=24h, 0=12h.
k_ra8_rcr2_bit_cntmd	0=calendar, 1=binary.

Definition at line 186 of file ra8_rtc_regs.h.

ra8_rcr4_bit_t

enum ra8_rcr4_bit_t : uint8_t

Bit positions in RCR4 (HUM Ch 26.2.6 p 1232 area).

Enumerator
k_ra8_rcr4_bit_rcksel	Count source select.
k_ra8_rcr4_bit_ropsel	RTC operation mode select.

Definition at line 201 of file ra8_rtc_regs.h.

ra8_rtc_addr_t

enum ra8_rtc_addr_t : uintptr_t

Enumerator
k_ra8_rtc_base_addr	RA8 rtc base address.

Definition at line 42 of file ra8_rtc_regs.h.

ra8_rtc_layout_t

enum ra8_rtc_layout_t : uint8_t

Authoritative struct offsets used by the layout asserts below.

Mirrors FSP R_RTC_Type (BSP R7KA8D2KF_core0.h, total size 0x80). Kept as a typed enum so the static_assert lines below do not contain magic numbers (clang-tidy readability-magic-numbers).

Enumerator
k_ra8_rtc_layout_size	Block size in bytes.
k_ra8_rtc_layout_off_rcr1	RCR1 offset.
k_ra8_rtc_layout_off_rcr2	RCR2 offset.
k_ra8_rtc_layout_off_rcr4	RCR4 offset.
k_ra8_rtc_layout_off_rfrh	RFRH offset.
k_ra8_rtc_layout_off_radj	RADJ offset.
k_ra8_rtc_layout_off_rtccr	RTCCR[0] offset.
k_ra8_rtc_layout_off_cp	CP[0] offset.

Definition at line 135 of file ra8_rtc_regs.h.

Function Documentation

ra8_rtc()

volatile r_rtc_regs_t * ra8_rtc ( void )

inlinestatic

Get pointer to the RTC block.

Definition at line 159 of file ra8_rtc_regs.h.

References k_ra8_rtc_base_addr.

Referenced by ra8_rtc_clear_status(), ra8_rtc_clock_init(), ra8_rtc_deinit(), ra8_rtc_dispatch(), ra8_rtc_enter_stop(), ra8_rtc_exit_stop(), ra8_rtc_get(), ra8_rtc_get_status(), ra8_rtc_init(), ra8_rtc_set(), ra8_rtc_set_alarm(), and ra8_rtc_set_irq_enable().