ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_rtc_regs.h
Go to the documentation of this file.
1
32
33#pragma once
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#include <stddef.h>
40#include <stdint.h>
41
42typedef enum : uintptr_t {
43 k_ra8_rtc_base_addr = 0x40202000UL,
45
61typedef struct {
62 volatile uint8_t R64CNT;
63 volatile uint8_t _r0;
64 volatile uint8_t RSECCNT;
65 volatile uint8_t _r1;
66 volatile uint8_t RMINCNT;
67 volatile uint8_t _r2;
68 volatile uint8_t RHRCNT;
69 volatile uint8_t _r3;
70 volatile uint8_t RWKCNT;
71 volatile uint8_t _r4;
72 volatile uint8_t RDAYCNT;
73 volatile uint8_t _r5;
74 volatile uint8_t RMONCNT;
75 volatile uint8_t _r6;
76 volatile uint16_t RYRCNT;
77
78 volatile uint8_t RSECAR;
79 volatile uint8_t _r7;
80 volatile uint8_t RMINAR;
81 volatile uint8_t _r8;
82 volatile uint8_t RHRAR;
83 volatile uint8_t _r9;
84 volatile uint8_t RWKAR;
85 volatile uint8_t _ra;
86 volatile uint8_t RDAYAR;
87 volatile uint8_t _rb;
88 volatile uint8_t RMONAR;
89 volatile uint8_t _rc;
90 volatile uint16_t RYRAR;
91 volatile uint8_t RYRAREN;
92 volatile uint8_t _rd;
93
94 volatile uint8_t _r10[2];
95 volatile uint8_t RCR1;
96 volatile uint8_t _r11;
97 volatile uint8_t RCR2;
98 volatile uint8_t _r12[3];
99 volatile uint8_t RCR4;
100 volatile uint8_t _r13;
101 volatile uint16_t RFRH;
102 volatile uint16_t RFRL;
103 volatile uint8_t RADJ;
104 volatile uint8_t _r14;
105 volatile uint16_t RADJ2;
106
107 /* +0x32..+0x3F reserved (7 x uint16_t in FSP). */
108 volatile uint16_t _r15[7];
109
115 volatile uint8_t RTCCR[12];
116 /* +0x4C..+0x4F reserved (5 halfwords minus RTCCR overlap = 2 hw). */
117 volatile uint16_t _r16[2];
118
123 volatile uint8_t CP[48];
125
145
146/* Compile-time check that the layout matches FSP R_RTC_Type. */
147static_assert(sizeof(r_rtc_regs_t) == (size_t)k_ra8_rtc_layout_size,
148 "r_rtc_regs_t must be 128 bytes");
149static_assert(offsetof(r_rtc_regs_t, RCR1) == (size_t)k_ra8_rtc_layout_off_rcr1, "RCR1 at +0x22");
150static_assert(offsetof(r_rtc_regs_t, RCR2) == (size_t)k_ra8_rtc_layout_off_rcr2, "RCR2 at +0x24");
151static_assert(offsetof(r_rtc_regs_t, RCR4) == (size_t)k_ra8_rtc_layout_off_rcr4, "RCR4 at +0x28");
152static_assert(offsetof(r_rtc_regs_t, RFRH) == (size_t)k_ra8_rtc_layout_off_rfrh, "RFRH at +0x2A");
153static_assert(offsetof(r_rtc_regs_t, RADJ) == (size_t)k_ra8_rtc_layout_off_radj, "RADJ at +0x2E");
154static_assert(offsetof(r_rtc_regs_t, RTCCR) == (size_t)k_ra8_rtc_layout_off_rtccr,
155 "RTCCR at +0x40");
156static_assert(offsetof(r_rtc_regs_t, CP) == (size_t)k_ra8_rtc_layout_off_cp, "CP at +0x50");
157
159static inline volatile r_rtc_regs_t* ra8_rtc(void)
160{
161 return (volatile r_rtc_regs_t*)k_ra8_rtc_base_addr;
162}
163
175
196
201typedef enum : uint8_t {
205
206#ifdef __cplusplus
207}
208#endif
ra8_rcr1_bit_t
Bit positions in RCR1 (HUM Ch 26.2.3 p 1229).
@ k_ra8_rcr1_bit_cie
Carry interrupt enable.
@ k_ra8_rcr1_bit_pes_lo
PES[3:0] periodic select (b4..b7).
@ k_ra8_rcr1_bit_aie
Alarm interrupt enable.
@ k_ra8_rcr1_bit_rtcos
RTCOUT output select.
@ k_ra8_rcr1_bit_pie
Periodic interrupt enable.
ra8_rcr2_bit_t
Bit positions in RCR2 (HUM Ch 26.2.4 p 1230).
@ k_ra8_rcr2_bit_cntmd
0=calendar, 1=binary.
@ k_ra8_rcr2_bit_aadjp
Auto-adjust period select.
@ k_ra8_rcr2_bit_adj30
30-second adjustment.
@ k_ra8_rcr2_bit_reset
Software reset (write 1, auto-clear).
@ k_ra8_rcr2_bit_aadje
Auto-adjust enable.
@ k_ra8_rcr2_bit_hr24
1=24h, 0=12h.
@ k_ra8_rcr2_bit_rtcoe
RTCOUT output enable.
@ k_ra8_rcr2_bit_start
0=stop, 1=run.
ra8_rcr4_bit_t
Bit positions in RCR4 (HUM Ch 26.2.6 p 1232 area).
@ k_ra8_rcr4_bit_rcksel
Count source select.
@ k_ra8_rcr4_bit_ropsel
RTC operation mode select.
ra8_rtc_layout_t
Authoritative struct offsets used by the layout asserts below.
@ k_ra8_rtc_layout_size
Block size in bytes.
@ k_ra8_rtc_layout_off_radj
RADJ offset.
@ k_ra8_rtc_layout_off_rcr1
RCR1 offset.
@ k_ra8_rtc_layout_off_rcr2
RCR2 offset.
@ k_ra8_rtc_layout_off_rcr4
RCR4 offset.
@ k_ra8_rtc_layout_off_cp
CP[0] offset.
@ k_ra8_rtc_layout_off_rtccr
RTCCR[0] offset.
@ k_ra8_rtc_layout_off_rfrh
RFRH offset.
static volatile r_rtc_regs_t * ra8_rtc(void)
Get pointer to the RTC block.
ra8_rtc_addr_t
@ k_ra8_rtc_base_addr
RA8 rtc base address.
RTC register window matching FSP R_RTC_Type byte-for-byte.
volatile uint8_t _r1
+0x03 reserved.
volatile uint8_t RTCCR[12]
+0x40..+0x4F: RTCCR[3] – Time Capture Control Register (3 ch x 0x04 stride).
volatile uint8_t RWKCNT
+0x08 Day-of-Week Counter / BCNT3.
volatile uint8_t R64CNT
+0x00 64 Hz Counter (read-only).
volatile uint16_t _r16[2]
Reserved.
volatile uint8_t _rd
+0x1F reserved.
volatile uint8_t RHRAR
+0x14 Hour Alarm (BCD) / BCNT2AR.
volatile uint8_t RMINCNT
+0x04 Minute Counter (BCD) / BCNT1.
volatile uint8_t RSECCNT
+0x02 Second Counter (BCD) / BCNT0.
volatile uint8_t _r7
+0x11 reserved.
volatile uint8_t _r9
+0x15 reserved.
volatile uint8_t _r12[3]
+0x25..+0x27 reserved.
volatile uint8_t RDAYCNT
+0x0A Day Counter (BCD).
volatile uint8_t _r5
+0x0B reserved.
volatile uint8_t _r4
+0x09 reserved.
volatile uint8_t RMINAR
+0x12 Minute Alarm (BCD) / BCNT1AR.
volatile uint8_t RCR4
+0x28 Control 4 (count source / mode).
volatile uint8_t CP[48]
+0x50..+0x7F: CP[3] – Capture registers (sec, min, hour, day, month).
volatile uint8_t RMONAR
+0x1A Month Alarm (BCD) / BCNT1AER.
volatile uint16_t _r15[7]
Reserved.
volatile uint8_t RYRAREN
+0x1E Year Alarm Enable / BCNT3AER.
volatile uint8_t _r6
+0x0D reserved.
volatile uint8_t RCR1
+0x22 Control 1 (IRQ enables, PES).
volatile uint8_t RCR2
+0x24 Control 2 (START/RESET/HR24/...).
volatile uint16_t RYRCNT
+0x0E Year Counter (BCD, 16-bit).
volatile uint8_t RADJ
+0x2E Time Error Adjustment.
volatile uint8_t _rb
+0x19 reserved.
volatile uint8_t _r11
+0x23 reserved.
volatile uint8_t _rc
+0x1B reserved.
volatile uint8_t RHRCNT
+0x06 Hour Counter (BCD) / BCNT2.
volatile uint8_t _ra
+0x17 reserved.
volatile uint8_t _r0
+0x01 reserved.
volatile uint8_t RWKAR
+0x16 Day-of-Week Alarm / BCNT3AR.
volatile uint16_t RFRL
+0x2C Frequency Register L (RFC[15:0]).
volatile uint16_t RYRAR
+0x1C Year Alarm (BCD) / BCNT2AER.
volatile uint8_t RDAYAR
+0x18 Day Alarm (BCD) / BCNT0AER.
volatile uint8_t _r10[2]
+0x20..+0x21 reserved.
volatile uint8_t RSECAR
+0x10 Second Alarm (BCD) / BCNT0AR.
volatile uint8_t _r3
+0x07 reserved.
volatile uint8_t _r13
+0x29 reserved.
volatile uint16_t RADJ2
+0x30 Time Error Adjustment 2 (FADJ).
volatile uint8_t _r8
+0x13 reserved.
volatile uint8_t RMONCNT
+0x0C Month Counter (BCD).
volatile uint16_t RFRH
+0x2A Frequency Register H (RFC16).
volatile uint8_t _r2
+0x05 reserved.
volatile uint8_t _r14
+0x2F reserved.