ra8_rsip_regs_fields.h

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#pragma once
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_rsip_regs_offsets.h"
 
#ifdef __cplusplus
extern "C" {
#endif

typedef enum : uint8_t {
  k_ra8_rsip_ctrl_bit_enable   = 0U, 
  k_ra8_rsip_ctrl_bit_bist     = 1U, 
  k_ra8_rsip_ctrl_bit_reset    = 2U, 
  k_ra8_rsip_ctrl_bit_dpa_arm  = 3U, 
  k_ra8_rsip_ctrl_bit_irq_glob = 4U, 
} ra8_rsip_ctrl_bits_t;

typedef enum : uint8_t {
  k_ra8_rsip_status_bit_ready   = 0U, 
  k_ra8_rsip_status_bit_busy    = 1U, 
  k_ra8_rsip_status_bit_bist_ok = 2U, 
  k_ra8_rsip_status_bit_kv_ok   = 3U, 
  k_ra8_rsip_status_bit_huk_ok  = 4U, 
  k_ra8_rsip_status_bit_dpa_on  = 5U, 
  k_ra8_rsip_status_bit_err     = 7U, 
} ra8_rsip_status_bits_t;

typedef enum : uint8_t {
  k_ra8_rsip_isr_bit_done      = 0U, 
  k_ra8_rsip_isr_bit_rnd       = 1U, 
  k_ra8_rsip_isr_bit_hash      = 2U, 
  k_ra8_rsip_isr_bit_asym_done = 3U, 
  k_ra8_rsip_isr_bit_kv_done   = 4U, 
  k_ra8_rsip_isr_bit_kdf_done  = 5U, 
  k_ra8_rsip_isr_bit_err       = 6U, 
  k_ra8_rsip_isr_bit_tamper    = 7U, 
} ra8_rsip_isr_bits_t;

typedef enum : uint32_t {
  k_ra8_rsip_mask_ctrl_enable   = 0x00000001UL, 
  k_ra8_rsip_mask_ctrl_bist     = 0x00000002UL, 
  k_ra8_rsip_mask_ctrl_reset    = 0x00000004UL, 
  k_ra8_rsip_mask_ctrl_dpa_arm  = 0x00000008UL, 
  k_ra8_rsip_mask_ctrl_irq_glob = 0x00000010UL, 
  k_ra8_rsip_mask_status_ready  = 0x00000001UL, 
  k_ra8_rsip_mask_status_busy   = 0x00000002UL, 
  k_ra8_rsip_mask_status_bistok = 0x00000004UL, 
  k_ra8_rsip_mask_status_kvok   = 0x00000008UL, 
  k_ra8_rsip_mask_status_hukok  = 0x00000010UL, 
  k_ra8_rsip_mask_status_dpa_on = 0x00000020UL, 
  k_ra8_rsip_mask_status_err    = 0x00000080UL, 
  k_ra8_rsip_mask_isr_done      = 0x00000001UL, 
  k_ra8_rsip_mask_isr_rnd       = 0x00000002UL, 
  k_ra8_rsip_mask_isr_hash      = 0x00000004UL, 
  k_ra8_rsip_mask_isr_asym_done = 0x00000008UL, 
  k_ra8_rsip_mask_isr_kv_done   = 0x00000010UL, 
  k_ra8_rsip_mask_isr_kdf_done  = 0x00000020UL, 
  k_ra8_rsip_mask_isr_err       = 0x00000040UL, 
  k_ra8_rsip_mask_isr_tamper    = 0x00000080UL, 
  k_ra8_rsip_mask_isr_all       = 0x000000FFUL, 
  k_ra8_rsip_mask_kv_busy       = 0x80000000UL, 
  k_ra8_rsip_mask_kv_ready      = 0x80000000UL, 
} ra8_rsip_mask_t;

typedef enum : uint32_t {
  k_ra8_rsip_hash_sha224     = 0x00000001UL, 
  k_ra8_rsip_hash_sha256     = 0x00000002UL, 
  k_ra8_rsip_hash_sha384     = 0x00000003UL, 
  k_ra8_rsip_hash_sha512     = 0x00000004UL, 
  k_ra8_rsip_hash_sha512_224 = 0x00000005UL, 
  k_ra8_rsip_hash_sha512_256 = 0x00000006UL, 
  k_ra8_rsip_hash_sha3_224   = 0x00000011UL, 
  k_ra8_rsip_hash_sha3_256   = 0x00000012UL, 
  k_ra8_rsip_hash_sha3_384   = 0x00000013UL, 
  k_ra8_rsip_hash_sha3_512   = 0x00000014UL, 
  k_ra8_rsip_hash_shake128   = 0x00000018UL, 
  k_ra8_rsip_hash_shake256   = 0x00000019UL, 
} ra8_rsip_hash_alg_t;

typedef enum : uint32_t {
  k_ra8_rsip_oem_cmd_invalid             = 0U,  
  k_ra8_rsip_oem_cmd_aes128              = 5U,  
  k_ra8_rsip_oem_cmd_aes192              = 6U,  
  k_ra8_rsip_oem_cmd_aes256              = 7U,  
  k_ra8_rsip_oem_cmd_aes128_xts          = 8U,  
  k_ra8_rsip_oem_cmd_aes256_xts          = 9U,  
  k_ra8_rsip_oem_cmd_rsa2048_priv        = 13U, 
  k_ra8_rsip_oem_cmd_rsa3072_priv        = 15U, 
  k_ra8_rsip_oem_cmd_rsa4096_priv        = 17U, 
  k_ra8_rsip_oem_cmd_ecc_secp256r1_priv  = 23U, 
  k_ra8_rsip_oem_cmd_ecc_secp384r1_priv  = 25U, 
  k_ra8_rsip_oem_cmd_hmac_sha224         = 26U, 
  k_ra8_rsip_oem_cmd_hmac_sha256         = 27U, 
  k_ra8_rsip_oem_cmd_ecc_brain256r1_priv = 29U, 
  k_ra8_rsip_oem_cmd_ecc_brain384r1_priv = 31U, 
  k_ra8_rsip_oem_cmd_ecc_brain512r1_priv = 33U, 
  k_ra8_rsip_oem_cmd_ecc_secp256k1_priv  = 35U, 
  k_ra8_rsip_oem_cmd_ecc_secp521r1_priv  = 37U, 
  k_ra8_rsip_oem_cmd_ecc_ed25519_priv    = 39U, 
  k_ra8_rsip_oem_cmd_hmac_sha384         = 40U, 
  k_ra8_rsip_oem_cmd_hmac_sha512         = 41U, 
  k_ra8_rsip_oem_cmd_hmac_sha512_224     = 42U, 
  k_ra8_rsip_oem_cmd_hmac_sha512_256     = 43U, 
  k_ra8_rsip_oem_cmd_chacha20            = 48U, 
} ra8_rsip_oem_cmd_t;

typedef enum : uint32_t {
  k_ra8_rsip_kv_op_idle  = 0x00000000UL, 
  k_ra8_rsip_kv_op_read  = 0x00000001UL, 
  k_ra8_rsip_kv_op_write = 0x00000002UL, 
  k_ra8_rsip_kv_op_erase = 0x00000003UL, 
  k_ra8_rsip_kv_op_count = 0x00000004UL, 
} ra8_rsip_kv_op_t;

typedef enum : uint8_t {
  k_ra8_rsip_sym_alg_aes128   = 1U, 
  k_ra8_rsip_sym_alg_aes192   = 2U, 
  k_ra8_rsip_sym_alg_aes256   = 3U, 
  k_ra8_rsip_sym_alg_chacha20 = 4U, 
} ra8_rsip_sym_alg_t;

typedef enum : uint16_t {
  k_ra8_rsip_handle_words_aes128       = 8U,   
  k_ra8_rsip_handle_words_aes192       = 12U,  
  k_ra8_rsip_handle_words_aes256       = 12U,  
  k_ra8_rsip_handle_words_chacha20     = 12U,  
  k_ra8_rsip_handle_words_hmac_sha224  = 12U,  
  k_ra8_rsip_handle_words_hmac_sha256  = 12U,  
  k_ra8_rsip_handle_words_hmac_sha384  = 16U,  
  k_ra8_rsip_handle_words_hmac_sha512  = 20U,  
  k_ra8_rsip_handle_words_ecc256_priv  = 12U,  
  k_ra8_rsip_handle_words_ecc384_priv  = 16U,  
  k_ra8_rsip_handle_words_ecc521_priv  = 24U,  
  k_ra8_rsip_handle_words_rsa2048_priv = 132U, 
  k_ra8_rsip_handle_words_rsa3072_priv = 196U, 
  k_ra8_rsip_handle_words_rsa4096_priv = 260U, 
} ra8_rsip_handle_word_t;

typedef enum : uint32_t {
  k_ra8_rsip_kw_op_wrap   = 0x00000001UL, 
  k_ra8_rsip_kw_op_unwrap = 0x00000002UL, 
} ra8_rsip_kw_op_t;

typedef enum : uint32_t {
  k_ra8_rsip_dotf_off = 0x00000000UL, 
  k_ra8_rsip_dotf_on  = 0x00000001UL, 
} ra8_rsip_dotf_route_t;

typedef enum : uint32_t {
  k_ra8_rsip_kdf_op_huk_label   = 0x00000001UL, 
  k_ra8_rsip_kdf_op_uid_label   = 0x00000002UL, 
  k_ra8_rsip_kdf_op_hkdf_sha256 = 0x00000010UL, 
  k_ra8_rsip_kdf_op_hkdf_sha384 = 0x00000011UL, 
  k_ra8_rsip_kdf_op_hkdf_sha512 = 0x00000012UL, 
} ra8_rsip_kdf_op_t;

typedef enum : uint32_t {
  k_ra8_rsip_life_cm     = 0x00000000UL, 
  k_ra8_rsip_life_ssd    = 0x00000001UL, 
  k_ra8_rsip_life_nsecsd = 0x00000002UL, 
  k_ra8_rsip_life_dpl    = 0x00000003UL, 
  k_ra8_rsip_life_lcm    = 0x00000004UL, 
  k_ra8_rsip_life_rma    = 0x00000005UL, 
} ra8_rsip_life_state_t;

typedef enum : uint8_t {
  k_ra8_rsip_debug_al0 = 0U, 
  k_ra8_rsip_debug_al1 = 1U, 
  k_ra8_rsip_debug_al2 = 2U, 
} ra8_rsip_debug_level_t;

typedef enum : uint8_t {
  k_ra8_rsip_aes_mode_ecb  = 0U, 
  k_ra8_rsip_aes_mode_cbc  = 1U, 
  k_ra8_rsip_aes_mode_ctr  = 2U, 
  k_ra8_rsip_aes_mode_gcm  = 3U, 
  k_ra8_rsip_aes_mode_ccm  = 4U, 
  k_ra8_rsip_aes_mode_xts  = 5U, 
  k_ra8_rsip_aes_mode_cmac = 6U, 
  k_ra8_rsip_aes_mode_gmac = 7U, 
} ra8_rsip_aes_mode_t;

typedef enum : uint8_t {
  k_ra8_rsip_dir_encrypt = 0U, 
  k_ra8_rsip_dir_decrypt = 1U, 
} ra8_rsip_aes_dir_t;

typedef enum : uint8_t {
  k_ra8_rsip_curve_secp192r1  = 0U, 
  k_ra8_rsip_curve_secp224r1  = 1U, 
  k_ra8_rsip_curve_secp256r1  = 2U, 
  k_ra8_rsip_curve_secp384r1  = 3U, 
  k_ra8_rsip_curve_secp521r1  = 4U, 
  k_ra8_rsip_curve_brain256r1 = 5U, 
  k_ra8_rsip_curve_brain384r1 = 6U, 
  k_ra8_rsip_curve_brain512r1 = 7U, 
  k_ra8_rsip_curve_ed25519    = 8U, 
  k_ra8_rsip_curve_secp256k1  = 9U, 
} ra8_rsip_curve_t;

typedef enum : uint16_t {
  k_ra8_rsip_rsa_1024 = 1024U, 
  k_ra8_rsip_rsa_2048 = 2048U, 
  k_ra8_rsip_rsa_3072 = 3072U, 
  k_ra8_rsip_rsa_4096 = 4096U, 
} ra8_rsip_rsa_size_t;

typedef enum : uint32_t {
  k_ra8_rsip_asym_op_rsa_sign     = 0x00000001UL, 
  k_ra8_rsip_asym_op_rsa_verify   = 0x00000002UL, 
  k_ra8_rsip_asym_op_rsa_encrypt  = 0x00000003UL, 
  k_ra8_rsip_asym_op_rsa_decrypt  = 0x00000004UL, 
  k_ra8_rsip_asym_op_ecdsa_sign   = 0x00000005UL, 
  k_ra8_rsip_asym_op_ecdsa_verify = 0x00000006UL, 
  k_ra8_rsip_asym_op_ecdh_compute = 0x00000007UL, 
  k_ra8_rsip_asym_op_ecc_keygen   = 0x00000008UL, 
  k_ra8_rsip_asym_op_eddsa_sign   = 0x00000009UL, 
  k_ra8_rsip_asym_op_eddsa_verify = 0x0000000AUL, 
} ra8_rsip_asym_op_t;

typedef enum : uint32_t {
  k_ra8_rsip_rsa_pad_pkcs1 = 0x00000001UL, 
  k_ra8_rsip_rsa_pad_oaep  = 0x00000002UL, 
} ra8_rsip_rsa_pad_t;

typedef enum : uint32_t {
  k_ra8_rsip_tamper_src_ext0 = 0x00000001UL, 
  k_ra8_rsip_tamper_src_ext1 = 0x00000002UL, 
  k_ra8_rsip_tamper_src_ext2 = 0x00000004UL, 
  k_ra8_rsip_tamper_src_ext3 = 0x00000008UL, 
  k_ra8_rsip_tamper_src_ext4 = 0x00000010UL, 
  k_ra8_rsip_tamper_src_ext5 = 0x00000020UL, 
  k_ra8_rsip_tamper_src_volt = 0x00010000UL, 
  k_ra8_rsip_tamper_src_clk  = 0x00020000UL, 
  k_ra8_rsip_tamper_src_self = 0x00040000UL, 
  k_ra8_rsip_tamper_src_all  = 0x0007003FUL, 
} ra8_rsip_tamper_src_t;

typedef enum : uint32_t {
  k_ra8_rsip_chacha_op_encrypt      = 0x00000001UL, 
  k_ra8_rsip_chacha_op_decrypt      = 0x00000002UL, 
  k_ra8_rsip_chacha_op_aead_encrypt = 0x00000003UL, 
  k_ra8_rsip_chacha_op_aead_decrypt = 0x00000004UL, 
  k_ra8_rsip_chacha_op_poly1305_mac = 0x00000005UL, 
} ra8_rsip_chacha_op_t;

typedef enum : uint16_t {
  k_ra8_rsip_sha224_digest_bytes     = 28U, 
  k_ra8_rsip_sha256_digest_bytes     = 32U, 
  k_ra8_rsip_sha256_digest_words     = 8U,  
  k_ra8_rsip_sha384_digest_bytes     = 48U, 
  k_ra8_rsip_sha512_digest_bytes     = 64U, 
  k_ra8_rsip_sha512_224_digest_bytes = 28U, 
  k_ra8_rsip_sha512_256_digest_bytes = 32U, 
  k_ra8_rsip_sha3_224_digest_bytes   = 28U, 
  k_ra8_rsip_sha3_256_digest_bytes   = 32U, 
  k_ra8_rsip_sha3_384_digest_bytes   = 48U, 
  k_ra8_rsip_sha3_512_digest_bytes   = 64U, 
  k_ra8_rsip_aes_block_bytes         = 16U, 
  k_ra8_rsip_aes128_key_bytes        = 16U, 
  k_ra8_rsip_aes192_key_bytes        = 24U, 
  k_ra8_rsip_aes256_key_bytes        = 32U, 
  k_ra8_rsip_chacha_key_bytes        = 32U, 
  k_ra8_rsip_chacha_nonce_bytes      = 12U, 
  k_ra8_rsip_poly1305_tag_bytes      = 16U, 
  k_ra8_rsip_gcm_tag_bytes           = 16U, 
  k_ra8_rsip_ccm_tag_bytes           = 16U, 
  k_ra8_rsip_huk_bytes               = 32U, 
  k_ra8_rsip_uid_bytes               = 16U, 
  k_ra8_rsip_trng_word_bytes         = 4U,  
  k_ra8_rsip_kv_slot_bytes           = 64U, 
  k_ra8_rsip_kv_slot_count           = 16U, 
} ra8_rsip_sizes_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_rsip_reg32(ra8_rsip_off_t offset)
{
  return (volatile uint32_t*)(k_ra8_rsip_base_addr + (uintptr_t)offset);
}
 
#ifdef __cplusplus
}
#endif